<div dir="ltr">Sorry, I've reverted this patch in r242992 because it broke compilation and I needed to make progress.<div><br></div><div>Bots were broken: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_clang-2Dx86-5F64-2Ddebian-2Dfast_builds_28956&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=Y6XHDfyyAAdN1QEo5TSrIjJ-lqvjLYCHWpenEOFJNYI&e=">http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/28956</a></div><div><br></div><div>When changing the core DAG bits, you'll need to test with all the targets enabled before committing.</div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Jul 23, 2015 at 12:42 AM Igor Breger <<a href="mailto:igor.breger@intel.com">igor.breger@intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ibreger<br>
Date: Thu Jul 23 02:39:21 2015<br>
New Revision: 242990<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D242990-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=O4fF9zQBP_VAn0RBUFuXqqzD46HbnX6CvLmQC64VmDc&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=242990&view=rev</a><br>
Log:<br>
AVX-512: Implemented encoding , DAG lowering and intrinsics for Integer Truncate with/without saturation<br>
Added tests for DAG lowering ,encoding and intrinsic<br>
<br>
Differential Revision: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D11218&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=z6UpXyl6rYP3Gb9gcsYAsHGx_zB3SIjmZx0xV8J5cVI&e=" rel="noreferrer" target="_blank">http://reviews.llvm.org/D11218</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/avx512-ext.ll<br>
- copied, changed from r242987, llvm/trunk/test/CodeGen/X86/avx512-trunc-ext.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-trunc.ll<br>
Removed:<br>
llvm/trunk/test/CodeGen/X86/avx512-trunc-ext.ll<br>
Modified:<br>
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll<br>
llvm/trunk/test/CodeGen/X86/masked_memop.ll<br>
llvm/trunk/test/MC/X86/x86-64-avx512bw.s<br>
llvm/trunk/test/MC/X86/x86-64-avx512bw_vl.s<br>
llvm/trunk/test/MC/X86/x86-64-avx512f_vl.s<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_IR_IntrinsicsX86.td-3Frev-3D242990-26r1-3D242989-26r2-3D242990-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=p9bgAXTKwDuH02TyHiSZ4AbOHhg6hVpOUIN0biVEViI&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=242990&r1=242989&r2=242990&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Thu Jul 23 02:39:21 2015<br>
@@ -5816,6 +5816,550 @@ let TargetPrefix = "x86" in {<br>
llvm_i8_ty], [IntrReadArgMem]>;<br>
<br>
}<br>
+<br>
+// truncate<br>
+let TargetPrefix = "x86" in {<br>
+ def int_x86_avx512_mask_pmov_qb_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v2i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qb_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qb_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v2i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qb_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qb_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v2i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qb_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qb_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v4i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qb_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qb_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v4i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qb_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qb_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v4i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qb_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qb_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqb512_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qb_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qb_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqb512_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qb_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qb_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqb512_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i64_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qb_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qw_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqw128_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v2i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qw_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqw128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qw_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqw128_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v2i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qw_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqw128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qw_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqw128_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v2i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qw_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqw128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qw_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqw256_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v4i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qw_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqw256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qw_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqw256_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v4i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qw_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqw256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qw_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqw256_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v4i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qw_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqw256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qw_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqw512_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v8i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qw_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqw512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qw_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqw512_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v8i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qw_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqw512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qw_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqw512_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v8i64_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qw_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqw512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qd_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqd128_mask">,<br>
+ Intrinsic<[llvm_v4i32_ty],<br>
+ [llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qd_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqd128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qd_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqd128_mask">,<br>
+ Intrinsic<[llvm_v4i32_ty],<br>
+ [llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qd_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqd128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qd_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqd128_mask">,<br>
+ Intrinsic<[llvm_v4i32_ty],<br>
+ [llvm_v2i64_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qd_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqd128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v2i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qd_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqd256_mask">,<br>
+ Intrinsic<[llvm_v4i32_ty],<br>
+ [llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qd_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqd256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qd_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqd256_mask">,<br>
+ Intrinsic<[llvm_v4i32_ty],<br>
+ [llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qd_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqd256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qd_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqd256_mask">,<br>
+ Intrinsic<[llvm_v4i32_ty],<br>
+ [llvm_v4i64_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qd_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqd256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_qd_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqd512_mask">,<br>
+ Intrinsic<[llvm_v8i32_ty],<br>
+ [llvm_v8i64_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_qd_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovqd512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qd_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqd512_mask">,<br>
+ Intrinsic<[llvm_v8i32_ty],<br>
+ [llvm_v8i64_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_qd_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsqd512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qd_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqd512_mask">,<br>
+ Intrinsic<[llvm_v8i32_ty],<br>
+ [llvm_v8i64_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_qd_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusqd512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i64_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_db_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v4i32_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_db_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_db_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v4i32_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_db_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_db_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v4i32_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_db_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_db_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i32_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_db_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_db_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i32_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_db_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_db_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i32_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_db_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_db_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdb512_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v16i32_ty, llvm_v16i8_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_db_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_db_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdb512_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v16i32_ty, llvm_v16i8_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_db_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_db_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdb512_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v16i32_ty, llvm_v16i8_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_db_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_dw_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdw128_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v4i32_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_dw_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdw128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_dw_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdw128_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v4i32_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_dw_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdw128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_dw_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdw128_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v4i32_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_dw_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdw128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v4i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_dw_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdw256_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v8i32_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_dw_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdw256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_dw_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdw256_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v8i32_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_dw_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdw256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_dw_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdw256_mask">,<br>
+ Intrinsic<[llvm_v8i16_ty],<br>
+ [llvm_v8i32_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_dw_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdw256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i32_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_dw_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdw512_mask">,<br>
+ Intrinsic<[llvm_v16i16_ty],<br>
+ [llvm_v16i32_ty, llvm_v16i16_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_dw_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovdw512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_dw_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdw512_mask">,<br>
+ Intrinsic<[llvm_v16i16_ty],<br>
+ [llvm_v16i32_ty, llvm_v16i16_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_dw_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovsdw512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_dw_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdw512_mask">,<br>
+ Intrinsic<[llvm_v16i16_ty],<br>
+ [llvm_v16i32_ty, llvm_v16i16_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_dw_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovusdw512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i32_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_wb_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovwb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i16_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_wb_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovwb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_wb_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovswb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i16_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_wb_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovswb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_wb_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovuswb128_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v8i16_ty, llvm_v16i8_ty, llvm_i8_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_wb_mem_128 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovuswb128mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v8i16_ty, llvm_i8_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_wb_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovwb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v16i16_ty, llvm_v16i8_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_wb_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovwb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_wb_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovswb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v16i16_ty, llvm_v16i8_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_wb_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovswb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_wb_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovuswb256_mask">,<br>
+ Intrinsic<[llvm_v16i8_ty],<br>
+ [llvm_v16i16_ty, llvm_v16i8_ty, llvm_i16_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_wb_mem_256 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovuswb256mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v16i16_ty, llvm_i16_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmov_wb_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovwb512_mask">,<br>
+ Intrinsic<[llvm_v32i8_ty],<br>
+ [llvm_v32i16_ty, llvm_v32i8_ty, llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmov_wb_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovwb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovs_wb_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovswb512_mask">,<br>
+ Intrinsic<[llvm_v32i8_ty],<br>
+ [llvm_v32i16_ty, llvm_v32i8_ty, llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovs_wb_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovswb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+ def int_x86_avx512_mask_pmovus_wb_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovuswb512_mask">,<br>
+ Intrinsic<[llvm_v32i8_ty],<br>
+ [llvm_v32i16_ty, llvm_v32i8_ty, llvm_i32_ty],<br>
+ [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_pmovus_wb_mem_512 :<br>
+ GCCBuiltin<"__builtin_ia32_pmovuswb512mem_mask">,<br>
+ Intrinsic<[],<br>
+ [llvm_ptr_ty, llvm_v32i16_ty, llvm_i32_ty],<br>
+ [IntrReadWriteArgMem]>;<br>
+}<br>
// Misc.<br>
let TargetPrefix = "x86" in {<br>
def int_x86_avx512_mask_cmp_ps_512 :<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_Target_TargetSelectionDAG.td-3Frev-3D242990-26r1-3D242989-26r2-3D242990-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=1N1PlU-VTBho751qt3qcs0wMgKU9qsrshbhTFSRceGM&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=242990&r1=242989&r2=242990&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu Jul 23 02:39:21 2015<br>
@@ -493,9 +493,10 @@ def atomic_load : SDNode<"ISD::ATOM<br>
def atomic_store : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,<br>
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;<br>
<br>
-def masked_store : SDNode<"ISD::MSTORE", SDTMaskedStore,<br>
+// Do not use mld, mst directly. Use masked_store masked_load, masked_truncstore<br>
+def mst : SDNode<"ISD::MSTORE", SDTMaskedStore,<br>
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;<br>
-def masked_load : SDNode<"ISD::MLOAD", SDTMaskedLoad,<br>
+def mld : SDNode<"ISD::MLOAD", SDTMaskedLoad,<br>
[SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;<br>
def masked_scatter : SDNode<"ISD::MSCATTER", SDTMaskedScatter,<br>
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;<br>
@@ -680,6 +681,12 @@ def load : PatFrag<(ops node:$ptr), (uni<br>
return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;<br>
}]>;<br>
<br>
+// masked load fragments.<br>
+def masked_load : PatFrag<(ops node:$src1, node:$src2, node:$src3),<br>
+ (mld node:$src1, node:$src2, node:$src3), [{<br>
+ return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;<br>
+}]>;<br>
+<br>
// extending load fragments.<br>
def extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{<br>
return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;<br>
@@ -791,6 +798,12 @@ def store : PatFrag<(ops node:$val, node<br>
return !cast<StoreSDNode>(N)->isTruncatingStore();<br>
}]>;<br>
<br>
+// masked store fragments.<br>
+def masked_store : PatFrag<(ops node:$src1, node:$src2, node:$src3),<br>
+ (mst node:$src1, node:$src2, node:$src3), [{<br>
+ return !cast<MaskedStoreSDNode>(N)->isTruncatingStore();<br>
+}]>;<br>
+<br>
// truncstore fragments.<br>
def truncstore : PatFrag<(ops node:$val, node:$ptr),<br>
(unindexedstore node:$val, node:$ptr), [{<br>
@@ -817,6 +830,21 @@ def truncstoref64 : PatFrag<(ops node:$v<br>
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f64;<br>
}]>;<br>
<br>
+def truncstorevi8 : PatFrag<(ops node:$val, node:$ptr),<br>
+ (truncstore node:$val, node:$ptr), [{<br>
+ return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;<br>
+}]>;<br>
+<br>
+def truncstorevi16 : PatFrag<(ops node:$val, node:$ptr),<br>
+ (truncstore node:$val, node:$ptr), [{<br>
+ return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;<br>
+}]>;<br>
+<br>
+def truncstorevi32 : PatFrag<(ops node:$val, node:$ptr),<br>
+ (truncstore node:$val, node:$ptr), [{<br>
+ return cast<StoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;<br>
+}]>;<br>
+<br>
// indexed store fragments.<br>
def istore : PatFrag<(ops node:$val, node:$base, node:$offset),<br>
(ist node:$val, node:$base, node:$offset), [{<br>
@@ -891,6 +919,27 @@ def post_truncstf32 : PatFrag<(ops node:<br>
return cast<StoreSDNode>(N)->getMemoryVT() == MVT::f32;<br>
}]>;<br>
<br>
+// masked truncstore fragments<br>
+def masked_truncstore : PatFrag<(ops node:$src1, node:$src2, node:$src3),<br>
+ (mst node:$src1, node:$src2, node:$src3), [{<br>
+ return cast<MaskedStoreSDNode>(N)->isTruncatingStore();<br>
+}]>;<br>
+def masked_truncstorevi8 :<br>
+ PatFrag<(ops node:$src1, node:$src2, node:$src3),<br>
+ (masked_truncstore node:$src1, node:$src2, node:$src3), [{<br>
+ return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i8;<br>
+}]>;<br>
+def masked_truncstorevi16 :<br>
+ PatFrag<(ops node:$src1, node:$src2, node:$src3),<br>
+ (masked_truncstore node:$src1, node:$src2, node:$src3), [{<br>
+ return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i16;<br>
+}]>;<br>
+def masked_truncstorevi32 :<br>
+ PatFrag<(ops node:$src1, node:$src2, node:$src3),<br>
+ (masked_truncstore node:$src1, node:$src2, node:$src3), [{<br>
+ return cast<MaskedStoreSDNode>(N)->getMemoryVT().getScalarType() == MVT::i32;<br>
+}]>;<br>
+<br>
// setcc convenience fragments.<br>
def setoeq : PatFrag<(ops node:$lhs, node:$rhs),<br>
(setcc node:$lhs, node:$rhs, SETOEQ)>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86ISelLowering.cpp-3Frev-3D242990-26r1-3D242989-26r2-3D242990-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=JpLbLqwPJvSPansYixm6hrooCyCABSXDN2Ax3RIcv7o&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=242990&r1=242989&r2=242990&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jul 23 02:39:21 2015<br>
@@ -1348,6 +1348,24 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FP_ROUND, MVT::v8f32, Legal);<br>
setOperationAction(ISD::FP_EXTEND, MVT::v8f32, Legal);<br>
<br>
+ setTruncStoreAction(MVT::v8i64, MVT::v8i8, Legal);<br>
+ setTruncStoreAction(MVT::v8i64, MVT::v8i16, Legal);<br>
+ setTruncStoreAction(MVT::v8i64, MVT::v8i32, Legal);<br>
+ setTruncStoreAction(MVT::v16i32, MVT::v16i8, Legal);<br>
+ setTruncStoreAction(MVT::v16i32, MVT::v16i16, Legal);<br>
+ if (Subtarget->hasVLX()){<br>
+ setTruncStoreAction(MVT::v4i64, MVT::v4i8, Legal);<br>
+ setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal);<br>
+ setTruncStoreAction(MVT::v4i64, MVT::v4i32, Legal);<br>
+ setTruncStoreAction(MVT::v8i32, MVT::v8i8, Legal);<br>
+ setTruncStoreAction(MVT::v8i32, MVT::v8i16, Legal);<br>
+<br>
+ setTruncStoreAction(MVT::v2i64, MVT::v2i8, Legal);<br>
+ setTruncStoreAction(MVT::v2i64, MVT::v2i16, Legal);<br>
+ setTruncStoreAction(MVT::v2i64, MVT::v2i32, Legal);<br>
+ setTruncStoreAction(MVT::v4i32, MVT::v4i8, Legal);<br>
+ setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal);<br>
+ }<br>
setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);<br>
setOperationAction(ISD::TRUNCATE, MVT::v16i8, Custom);<br>
setOperationAction(ISD::TRUNCATE, MVT::v8i32, Custom);<br>
@@ -1556,6 +1574,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::VSELECT, MVT::v64i8, Legal);<br>
setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom);<br>
setOperationAction(ISD::TRUNCATE, MVT::v64i1, Custom);<br>
+ setOperationAction(ISD::TRUNCATE, MVT::v32i8, Custom);<br>
<br>
setOperationAction(ISD::SMAX, MVT::v64i8, Legal);<br>
setOperationAction(ISD::SMAX, MVT::v32i16, Legal);<br>
@@ -1566,6 +1585,11 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UMIN, MVT::v64i8, Legal);<br>
setOperationAction(ISD::UMIN, MVT::v32i16, Legal);<br>
<br>
+ setTruncStoreAction(MVT::v32i16, MVT::v32i8, Legal);<br>
+ setTruncStoreAction(MVT::v16i16, MVT::v16i8, Legal);<br>
+ if (Subtarget->hasVLX())<br>
+ setTruncStoreAction(MVT::v8i16, MVT::v8i8, Legal);<br>
+<br>
for (int i = MVT::v32i8; i != MVT::v8i64; ++i) {<br>
const MVT VT = (MVT::SimpleValueType)i;<br>
<br>
@@ -12485,10 +12509,8 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
Subtarget->hasDQI() && Subtarget->hasVLX())<br>
return Op; // legal, will go to VPMOVB2M, VPMOVQ2M<br>
}<br>
- if (InVT.is512BitVector() || VT.getVectorElementType() == MVT::i1) {<br>
- if (VT.getVectorElementType().getSizeInBits() >=8)<br>
- return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);<br>
<br>
+ if (VT.getVectorElementType() == MVT::i1) {<br>
assert(VT.getVectorElementType() == MVT::i1 && "Unexpected vector type");<br>
unsigned NumElts = InVT.getVectorNumElements();<br>
assert ((NumElts == 8 || NumElts == 16) && "Unexpected vector type");<br>
@@ -12504,6 +12526,11 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
return DAG.getNode(X86ISD::TESTM, DL, VT, And, And);<br>
}<br>
<br>
+ // vpmovqb/w/d, vpmovdb/w, vpmovwb<br>
+ if (((!InVT.is512BitVector() && Subtarget->hasVLX()) || InVT.is512BitVector()) &&<br>
+ (InVT.getVectorElementType() != MVT::i16 || Subtarget->hasBWI()))<br>
+ return DAG.getNode(X86ISD::VTRUNC, DL, VT, In);<br>
+<br>
if ((VT == MVT::v4i32) && (InVT == MVT::v4i64)) {<br>
// On AVX2, v4i64 -> v4i32 becomes VPERMD.<br>
if (Subtarget->hasInt256()) {<br>
@@ -15220,7 +15247,7 @@ static SDValue getTargetVShiftNode(unsig<br>
<br>
/// \brief Return (and \p Op, \p Mask) for compare instructions or<br>
/// (vselect \p Mask, \p Op, \p PreservedSrc) for others along with the<br>
-/// necessary casting for \p Mask when lowering masking intrinsics.<br>
+/// necessary casting or extending for \p Mask when lowering masking intrinsics<br>
static SDValue getVectorMaskingNode(SDValue Op, SDValue Mask,<br>
SDValue PreservedSrc,<br>
const X86Subtarget *Subtarget,<br>
@@ -15228,8 +15255,8 @@ static SDValue getVectorMaskingNode(SDVa<br>
EVT VT = Op.getValueType();<br>
EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),<br>
MVT::i1, VT.getVectorNumElements());<br>
- EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,<br>
- Mask.getValueType().getSizeInBits());<br>
+ SDValue VMask = SDValue();<br>
+ unsigned OpcodeSelect = ISD::VSELECT;<br>
SDLoc dl(Op);<br>
<br>
assert(MaskVT.isSimple() && "invalid mask type");<br>
@@ -15237,11 +15264,20 @@ static SDValue getVectorMaskingNode(SDVa<br>
if (isAllOnes(Mask))<br>
return Op;<br>
<br>
- // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements<br>
- // are extracted by EXTRACT_SUBVECTOR.<br>
- SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
- DAG.getBitcast(BitcastVT, Mask),<br>
- DAG.getIntPtrConstant(0, dl));<br>
+ if (MaskVT.bitsGT(Mask.getValueType())) {<br>
+ EVT newMaskVT = EVT::getIntegerVT(*DAG.getContext(),<br>
+ MaskVT.getSizeInBits());<br>
+ VMask = DAG.getBitcast(MaskVT,<br>
+ DAG.getNode(ISD::ANY_EXTEND, dl, newMaskVT, Mask));<br>
+ } else {<br>
+ EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,<br>
+ Mask.getValueType().getSizeInBits());<br>
+ // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements<br>
+ // are extracted by EXTRACT_SUBVECTOR.<br>
+ VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
+ DAG.getBitcast(BitcastVT, Mask),<br>
+ DAG.getIntPtrConstant(0, dl));<br>
+ }<br>
<br>
switch (Op.getOpcode()) {<br>
default: break;<br>
@@ -15250,10 +15286,18 @@ static SDValue getVectorMaskingNode(SDVa<br>
case X86ISD::CMPM:<br>
case X86ISD::CMPMU:<br>
return DAG.getNode(ISD::AND, dl, VT, Op, VMask);<br>
+ case X86ISD::VTRUNC:<br>
+ case X86ISD::VTRUNCS:<br>
+ case X86ISD::VTRUNCUS:<br>
+ // We can't use ISD::VSELECT here because it is not always "Legal"<br>
+ // for the destination type. For example vpmovqb require only AVX512<br>
+ // and vselect that can operate on byte element type require BWI<br>
+ OpcodeSelect = X86ISD::SELECT;<br>
+ break;<br>
}<br>
if (PreservedSrc.getOpcode() == ISD::UNDEF)<br>
PreservedSrc = getZeroVector(VT, Subtarget, DAG, dl);<br>
- return DAG.getNode(ISD::VSELECT, dl, VT, VMask, Op, PreservedSrc);<br>
+ return DAG.getNode(OpcodeSelect, dl, VT, VMask, Op, PreservedSrc);<br>
}<br>
<br>
/// \brief Creates an SDNode for a predicated scalar operation.<br>
@@ -16111,6 +16155,45 @@ static SDValue LowerSEHRESTOREFRAME(SDVa<br>
return Chain;<br>
}<br>
<br>
+/// \brief Lower intrinsics for TRUNCATE_TO_MEM case<br>
+/// return truncate Store/MaskedStore Node<br>
+static SDValue LowerINTRINSIC_TRUNCATE_TO_MEM(const SDValue & Op,<br>
+ SelectionDAG &DAG,<br>
+ MVT ElementType) {<br>
+ SDLoc dl(Op);<br>
+ SDValue Mask = Op.getOperand(4);<br>
+ SDValue DataToTruncate = Op.getOperand(3);<br>
+ SDValue Addr = Op.getOperand(2);<br>
+ SDValue Chain = Op.getOperand(0);<br>
+<br>
+ EVT VT = DataToTruncate.getValueType();<br>
+ EVT SVT = EVT::getVectorVT(*DAG.getContext(),<br>
+ ElementType, VT.getVectorNumElements());<br>
+<br>
+ if (isAllOnes(Mask)) // return just a truncate store<br>
+ return DAG.getTruncStore(Chain, dl, DataToTruncate, Addr,<br>
+ MachinePointerInfo(), SVT, false, false,<br>
+ SVT.getScalarSizeInBits()/8);<br>
+<br>
+ EVT MaskVT = EVT::getVectorVT(*DAG.getContext(),<br>
+ MVT::i1, VT.getVectorNumElements());<br>
+ EVT BitcastVT = EVT::getVectorVT(*DAG.getContext(), MVT::i1,<br>
+ Mask.getValueType().getSizeInBits());<br>
+ // In case when MaskVT equals v2i1 or v4i1, low 2 or 4 elements<br>
+ // are extracted by EXTRACT_SUBVECTOR.<br>
+ SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
+ DAG.getBitcast(BitcastVT, Mask),<br>
+ DAG.getIntPtrConstant(0, dl));<br>
+<br>
+ MachineMemOperand *MMO = DAG.getMachineFunction().<br>
+ getMachineMemOperand(MachinePointerInfo(),<br>
+ MachineMemOperand::MOStore, SVT.getStoreSize(),<br>
+ SVT.getScalarSizeInBits()/8);<br>
+<br>
+ return DAG.getMaskedStore(Chain, dl, DataToTruncate, Addr,<br>
+ VMask, SVT, MMO, true);<br>
+}<br>
+<br>
static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,<br>
SelectionDAG &DAG) {<br>
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();<br>
@@ -16244,6 +16327,12 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD<br>
MachinePointerInfo(), false, false,<br>
VT.getScalarSizeInBits()/8);<br>
}<br>
+ case TRUNCATE_TO_MEM_VI8:<br>
+ return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i8);<br>
+ case TRUNCATE_TO_MEM_VI16:<br>
+ return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i16);<br>
+ case TRUNCATE_TO_MEM_VI32:<br>
+ return LowerINTRINSIC_TRUNCATE_TO_MEM(Op, DAG, MVT::i32);<br>
case EXPAND_FROM_MEM: {<br>
SDLoc dl(Op);<br>
SDValue Mask = Op.getOperand(4);<br>
@@ -18954,7 +19043,8 @@ const char *X86TargetLowering::getTarget<br>
case X86ISD::VZEXT: return "X86ISD::VZEXT";<br>
case X86ISD::VSEXT: return "X86ISD::VSEXT";<br>
case X86ISD::VTRUNC: return "X86ISD::VTRUNC";<br>
- case X86ISD::VTRUNCM: return "X86ISD::VTRUNCM";<br>
+ case X86ISD::VTRUNCS: return "X86ISD::VTRUNCS";<br>
+ case X86ISD::VTRUNCUS: return "X86ISD::VTRUNCUS";<br>
case X86ISD::VINSERT: return "X86ISD::VINSERT";<br>
case X86ISD::VFPEXT: return "X86ISD::VFPEXT";<br>
case X86ISD::VFPROUND: return "X86ISD::VFPROUND";<br>
@@ -24093,6 +24183,15 @@ static SDValue PerformMSTORECombine(SDNo<br>
unsigned FromSz = VT.getVectorElementType().getSizeInBits();<br>
unsigned ToSz = StVT.getVectorElementType().getSizeInBits();<br>
<br>
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
+<br>
+ // The truncating store is legal in some cases. For example<br>
+ // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw<br>
+ // are designated for truncate store.<br>
+ // In this case we don't need any further transformations.<br>
+ if (TLI.isTruncStoreLegal(VT, StVT))<br>
+ return SDValue();<br>
+<br>
// From, To sizes and ElemCount must be pow of two<br>
assert (isPowerOf2_32(NumElems * FromSz * ToSz) &&<br>
"Unexpected size for truncating masked store");<br>
@@ -24204,6 +24303,13 @@ static SDValue PerformSTORECombine(SDNod<br>
unsigned FromSz = VT.getVectorElementType().getSizeInBits();<br>
unsigned ToSz = StVT.getVectorElementType().getSizeInBits();<br>
<br>
+ // The truncating store is legal in some cases. For example<br>
+ // vpmovqb, vpmovqw, vpmovqd, vpmovdb, vpmovdw<br>
+ // are designated for truncate store.<br>
+ // In this case we don't need any further transformations.<br>
+ if (TLI.isTruncStoreLegal(VT, StVT))<br>
+ return SDValue();<br>
+<br>
// From, To sizes and ElemCount must be pow of two<br>
if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue();<br>
// We are going to use the original vector elt for storing.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86ISelLowering.h-3Frev-3D242990-26r1-3D242989-26r2-3D242990-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=s_aflHZVBu_UtJuIwM5O7vatyJZL6bZ4_373NQ7Nlr4&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=242990&r1=242989&r2=242990&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Jul 23 02:39:21 2015<br>
@@ -282,9 +282,8 @@ namespace llvm {<br>
<br>
// Vector integer truncate.<br>
VTRUNC,<br>
-<br>
- // Vector integer truncate with mask.<br>
- VTRUNCM,<br>
+ // Vector integer truncate with unsigned/signed saturation.<br>
+ VTRUNCUS, VTRUNCS,<br>
<br>
// Vector FP extend.<br>
VFPEXT,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrAVX512.td-3Frev-3D242990-26r1-3D242989-26r2-3D242990-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=djoHSEeOTtWaQ_tRcDLDzScU5SY2tCjpKypIKvGK4Jk&s=HeudS_FIgb7btDbxwHE4LRsUpah9addBpDbRjqFgSEw&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=242990&r1=242989&r2=242990&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Thu Jul 23 02:39:21 2015<br>
@@ -5571,82 +5571,217 @@ defm VRNDSCALESD : avx512_rndscale_scala<br>
// Integer truncate and extend operations<br>
//-------------------------------------------------<br>
<br>
-multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,<br>
- RegisterClass dstRC, RegisterClass srcRC,<br>
- RegisterClass KRC, X86MemOperand x86memop> {<br>
- def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),<br>
- (ins srcRC:$src),<br>
- !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"),<br>
+multiclass avx512_trunc_common<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
+ X86VectorVTInfo SrcInfo, X86VectorVTInfo DestInfo,<br>
+ X86MemOperand x86memop> {<br>
+<br>
+ defm rr : AVX512_maskable<opc, MRMDestReg, DestInfo, (outs DestInfo.RC:$dst),<br>
+ (ins SrcInfo.RC:$src1), OpcodeStr ,"$src1", "$src1",<br>
+ (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1)))>,<br>
+ EVEX, T8XS;<br>
+<br>
+ // for intrinsic patter match<br>
+ def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,<br>
+ (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),<br>
+ undef)),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,<br>
+ SrcInfo.RC:$src1)>;<br>
+<br>
+ def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,<br>
+ (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),<br>
+ DestInfo.ImmAllZerosV)),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrkz) DestInfo.KRCWM:$mask ,<br>
+ SrcInfo.RC:$src1)>;<br>
+<br>
+ def : Pat<(DestInfo.VT (X86select DestInfo.KRCWM:$mask,<br>
+ (DestInfo.VT (OpNode (SrcInfo.VT SrcInfo.RC:$src1))),<br>
+ DestInfo.RC:$src0)),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##rrk) DestInfo.RC:$src0,<br>
+ DestInfo.KRCWM:$mask ,<br>
+ SrcInfo.RC:$src1)>;<br>
+<br>
+ let mayStore = 1 in {<br>
+ def mr : AVX512XS8I<opc, MRMDestMem, (outs),<br>
+ (ins x86memop:$dst, SrcInfo.RC:$src),<br>
+ OpcodeStr # "\t{$src, $dst |$dst, $src}",<br>
[]>, EVEX;<br>
<br>
- def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),<br>
- (ins KRC:$mask, srcRC:$src),<br>
- !strconcat(OpcodeStr,<br>
- "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),<br>
+ def mrk : AVX512XS8I<opc, MRMDestMem, (outs),<br>
+ (ins x86memop:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src),<br>
+ OpcodeStr # "\t{$src, $dst {${mask}} |$dst {${mask}}, $src}",<br>
[]>, EVEX, EVEX_K;<br>
+ }//mayStore = 1<br>
+}<br>
<br>
- def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),<br>
- (ins KRC:$mask, srcRC:$src),<br>
- !strconcat(OpcodeStr,<br>
- "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),<br>
- []>, EVEX, EVEX_KZ;<br>
+multiclass avx512_trunc_mr_lowering<X86VectorVTInfo SrcInfo,<br>
+ X86VectorVTInfo DestInfo,<br>
+ PatFrag truncFrag, PatFrag mtruncFrag > {<br>
+<br>
+ def : Pat<(truncFrag (SrcInfo.VT SrcInfo.RC:$src), addr:$dst),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr)<br>
+ addr:$dst, SrcInfo.RC:$src)>;<br>
+<br>
+ def : Pat<(mtruncFrag addr:$dst, SrcInfo.KRCWM:$mask,<br>
+ (SrcInfo.VT SrcInfo.RC:$src)),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk)<br>
+ addr:$dst, SrcInfo.KRCWM:$mask, SrcInfo.RC:$src)>;<br>
+}<br>
<br>
- def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),<br>
- !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),<br>
- []>, EVEX;<br>
+multiclass avx512_trunc_sat_mr_lowering<X86VectorVTInfo SrcInfo,<br>
+ X86VectorVTInfo DestInfo, string sat > {<br>
<br>
- def mrk : AVX512XS8I<opc, MRMDestMem, (outs),<br>
- (ins x86memop:$dst, KRC:$mask, srcRC:$src),<br>
- !strconcat(OpcodeStr, "\t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),<br>
- []>, EVEX, EVEX_K;<br>
+ def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#<br>
+ DestInfo.Suffix#"_mem_"#SrcInfo.Size)<br>
+ addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), SrcInfo.MRC:$mask),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mrk) addr:$ptr,<br>
+ (COPY_TO_REGCLASS SrcInfo.MRC:$mask, SrcInfo.KRCWM),<br>
+ (SrcInfo.VT SrcInfo.RC:$src))>;<br>
+<br>
+ def: Pat<(!cast<Intrinsic>("int_x86_avx512_mask_pmov"#sat#"_"#SrcInfo.Suffix#<br>
+ DestInfo.Suffix#"_mem_"#SrcInfo.Size)<br>
+ addr:$ptr, (SrcInfo.VT SrcInfo.RC:$src), -1),<br>
+ (!cast<Instruction>(NAME#SrcInfo.ZSuffix##mr) addr:$ptr,<br>
+ (SrcInfo.VT SrcInfo.RC:$src))>;<br>
+}<br>
+<br>
+multiclass avx512_trunc<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
+ AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,<br>
+ X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,<br>
+ X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,<br>
+ X86MemOperand x86memopZ, PatFrag truncFrag, PatFrag mtruncFrag,<br>
+ Predicate prd = HasAVX512>{<br>
+<br>
+ let Predicates = [HasVLX, prd] in {<br>
+ defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,<br>
+ DestInfoZ128, x86memopZ128>,<br>
+ avx512_trunc_mr_lowering<VTSrcInfo.info128, DestInfoZ128,<br>
+ truncFrag, mtruncFrag>, EVEX_V128;<br>
+<br>
+ defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,<br>
+ DestInfoZ256, x86memopZ256>,<br>
+ avx512_trunc_mr_lowering<VTSrcInfo.info256, DestInfoZ256,<br>
+ truncFrag, mtruncFrag>, EVEX_V256;<br>
+ }<br>
+ let Predicates = [prd] in<br>
+ defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,<br>
+ DestInfoZ, x86memopZ>,<br>
+ avx512_trunc_mr_lowering<VTSrcInfo.info512, DestInfoZ,<br>
+ truncFrag, mtruncFrag>, EVEX_V512;<br>
+}<br>
<br>
+multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
+ AVX512VLVectorVTInfo VTSrcInfo, X86VectorVTInfo DestInfoZ128,<br>
+ X86VectorVTInfo DestInfoZ256, X86VectorVTInfo DestInfoZ,<br>
+ X86MemOperand x86memopZ128, X86MemOperand x86memopZ256,<br>
+ X86MemOperand x86memopZ, string sat, Predicate prd = HasAVX512>{<br>
+<br>
+ let Predicates = [HasVLX, prd] in {<br>
+ defm Z128: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info128,<br>
+ DestInfoZ128, x86memopZ128>,<br>
+ avx512_trunc_sat_mr_lowering<VTSrcInfo.info128, DestInfoZ128,<br>
+ sat>, EVEX_V128;<br>
+<br>
+ defm Z256: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info256,<br>
+ DestInfoZ256, x86memopZ256>,<br>
+ avx512_trunc_sat_mr_lowering<VTSrcInfo.info256, DestInfoZ256,<br>
+ sat>, EVEX_V256;<br>
+ }<br>
+ let Predicates = [prd] in<br>
+ defm Z: avx512_trunc_common<opc, OpcodeStr, OpNode, VTSrcInfo.info512,<br>
+ DestInfoZ, x86memopZ>,<br>
+ avx512_trunc_sat_mr_lowering<VTSrcInfo.info512, DestInfoZ,<br>
+ sat>, EVEX_V512;<br>
+}<br>
+<br>
+multiclass avx512_trunc_qb<bits<8> opc, string OpcodeStr, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,<br>
+ v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,<br>
+ truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VO>;<br>
+}<br>
+multiclass avx512_trunc_sat_qb<bits<8> opc, string sat, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qb", OpNode, avx512vl_i64_info,<br>
+ v16i8x_info, v16i8x_info, v16i8x_info, i16mem, i32mem, i64mem,<br>
+ sat>, EVEX_CD8<8, CD8VO>;<br>
+}<br>
+<br>
+multiclass avx512_trunc_qw<bits<8> opc, string OpcodeStr, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,<br>
+ v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,<br>
+ truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VQ>;<br>
+}<br>
+multiclass avx512_trunc_sat_qw<bits<8> opc, string sat, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qw", OpNode, avx512vl_i64_info,<br>
+ v8i16x_info, v8i16x_info, v8i16x_info, i32mem, i64mem, i128mem,<br>
+ sat>, EVEX_CD8<16, CD8VQ>;<br>
+}<br>
+<br>
+multiclass avx512_trunc_qd<bits<8> opc, string OpcodeStr, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i64_info,<br>
+ v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,<br>
+ truncstorevi32, masked_truncstorevi32>, EVEX_CD8<32, CD8VH>;<br>
+}<br>
+multiclass avx512_trunc_sat_qd<bits<8> opc, string sat, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"qd", OpNode, avx512vl_i64_info,<br>
+ v4i32x_info, v4i32x_info, v8i32x_info, i64mem, i128mem, i256mem,<br>
+ sat>, EVEX_CD8<32, CD8VH>;<br>
+}<br>
+<br>
+multiclass avx512_trunc_db<bits<8> opc, string OpcodeStr, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,<br>
+ v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,<br>
+ truncstorevi8, masked_truncstorevi8>, EVEX_CD8<8, CD8VQ>;<br>
+}<br>
+multiclass avx512_trunc_sat_db<bits<8> opc, string sat, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"db", OpNode, avx512vl_i32_info,<br>
+ v16i8x_info, v16i8x_info, v16i8x_info, i32mem, i64mem, i128mem,<br>
+ sat>, EVEX_CD8<8, CD8VQ>;<br>
+}<br>
+<br>
+multiclass avx512_trunc_dw<bits<8> opc, string OpcodeStr, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i32_info,<br>
+ v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,<br>
+ truncstorevi16, masked_truncstorevi16>, EVEX_CD8<16, CD8VH>;<br>
+}<br>
+multiclass avx512_trunc_sat_dw<bits<8> opc, string sat, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"dw", OpNode, avx512vl_i32_info,<br>
+ v8i16x_info, v8i16x_info, v16i16x_info, i64mem, i128mem, i256mem,<br>
+ sat>, EVEX_CD8<16, CD8VH>;<br>
+}<br>
+<br>
+multiclass avx512_trunc_wb<bits<8> opc, string OpcodeStr, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc<opc, OpcodeStr, OpNode, avx512vl_i16_info,<br>
+ v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,<br>
+ truncstorevi8, masked_truncstorevi8,HasBWI>, EVEX_CD8<16, CD8VH>;<br>
+}<br>
+multiclass avx512_trunc_sat_wb<bits<8> opc, string sat, SDNode OpNode> {<br>
+ defm NAME: avx512_trunc_sat<opc, "vpmov"##sat##"wb", OpNode, avx512vl_i16_info,<br>
+ v16i8x_info, v16i8x_info, v32i8x_info, i64mem, i128mem, i256mem,<br>
+ sat, HasBWI>, EVEX_CD8<16, CD8VH>;<br>
}<br>
-defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,<br>
- i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;<br>
-defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,<br>
- i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;<br>
-defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,<br>
- i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;<br>
-defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,<br>
- i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;<br>
-defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,<br>
- i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;<br>
-defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,<br>
- i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;<br>
-defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,<br>
- i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;<br>
-defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,<br>
- i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;<br>
-defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,<br>
- </blockquote></div>