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[+ Asghar, whose patch this was]
<div><br>
<div>
<div>On 20 Jul 2015, at 19:32, Mikhail Zolotukhin <<a href="mailto:mzolotukhin@apple.com">mzolotukhin@apple.com</a>> wrote:</div>
<br class="Apple-interchange-newline">
<blockquote type="cite">
<blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
<br class="Apple-interchange-newline">
On Jul 16, 2015, at 8:22 AM, James Molloy <<a href="mailto:James.Molloy@arm.com">James.Molloy@arm.com</a>> wrote:<br>
<br>
Author: jamesm<br>
Date: Thu Jul 16 10:22:46 2015<br>
New Revision: 242409<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D242409-26view-3Drev&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=090uCQXZqv-iXjthDS1yqqMXQ42Ei0saHZHN_3gQxYQ&e=">http://llvm.org/viewvc/llvm-project?rev=242409&view=rev</a><br>
Log:<br>
[Codegen] Add intrinsics 'absdiff' and corresponding SDNodes for absolute difference operation<br>
<br>
This adds new intrinsics "*absdiff" for absolute difference ops to facilitate efficient code generation for "sum of absolute differences" operation.<br>
The patch also contains the introduction of corresponding SDNodes and basic legalization support.Sanity of the generated code is tested on X86.<br>
<br>
This is 1st of the three patches.<br>
<br>
Patch by Shahid Asghar-ahmad!<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/absdiff_expand.ll<br>
Modified:<br>
llvm/trunk/docs/LangRef.rst<br>
llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h<br>
llvm/trunk/include/llvm/IR/Intrinsics.td<br>
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br>
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
<br>
Modified: llvm/trunk/docs/LangRef.rst<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_docs_LangRef.rst-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=i2oLhr11yNpJBVSs9fLJty9frTQRVm9dWPwUfEJMm3U&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.rst?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/docs/LangRef.rst (original)<br>
+++ llvm/trunk/docs/LangRef.rst Thu Jul 16 10:22:46 2015<br>
@@ -10328,6 +10328,65 @@ Examples:<br>
<br>
%r2 = call float @llvm.fmuladd.f32(float %a, float %b, float %c) ; yields float:r2 = (a * b) + c<br>
<br>
+<br>
+'``llvm.uabsdiff.*``' and '``llvm.sabsdiff.*``' Intrinsics<br>
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^<br>
+<br>
+Syntax:<br>
+"""""""<br>
+This is an overloaded intrinsic. The loaded data is a vector of any integer bit width.<br>
+<br>
+.. code-block:: llvm<br>
+<br>
+ declare <4 x integer> @llvm.uabsdiff.v4i32(<4 x integer> %a, <4 x integer> %b)<br>
+<br>
+<br>
+Overview:<br>
+"""""""""<br>
+<br>
+The ``llvm.uabsdiff`` intrinsic returns a vector result of the absolute difference of the two operands,<br>
+treating them both as unsigned integers.<br>
+<br>
+The ``llvm.sabsdiff`` intrinsic returns a vector result of the absolute difference of the two operands,<br>
+treating them both as signed integers.<br>
+<br>
+.. note::<br>
+<br>
+ These intrinsics are primarily used during the code generation stage of compilation.<br>
+ They are generated by compiler passes such as the Loop and SLP <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__vectorizers.it&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=eL7nNlT3WRXX3WYjcyCaWzU4L6Au_CIcCW26K2aCczA&e=">
vectorizers.it</a> is not<br>
+ recommended for users to create them manually.<br>
+<br>
+Arguments:<br>
+""""""""""<br>
+<br>
+Both intrinsics take two integer of the same bitwidth.<br>
+<br>
+Semantics:<br>
+""""""""""<br>
+<br>
+The expression::<br>
+<br>
+ call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)<br>
+<br>
+is equivalent to::<br>
+<br>
+ %sub = sub <4 x i32> %a, %b<br>
+ %ispos = icmp ugt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1><br>
</blockquote>
<span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">Isn't
it always 'false'?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
<br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
<blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
+ %neg = sub <4 x i32> zeroinitializer, %sub<br>
+ %1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg<br>
+<br>
+Similarly the expression::<br>
+<br>
+ call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a, <4 x i32> %b)<br>
+<br>
+is equivalent to::<br>
+<br>
+ %sub = sub nsw <4 x i32> %a, %b<br>
+ %ispos = icmp sgt <4 x i32> %sub, <i32 -1, i32 -1, i32 -1, i32 -1><br>
</blockquote>
<span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">Wouldn't
it be more readable if we use "icmp sge <4 x i32> %sub, zeroinitializer"?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
<blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
+ %neg = sub nsw <4 x i32> zeroinitializer, %sub<br>
+ %1 = select <4 x i1> %ispos, <4 x i32> %sub, <4 x i32> %neg<br>
+<br>
+<br>
Half Precision Floating Point Intrinsics<br>
----------------------------------------<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_CodeGen_ISDOpcodes.h-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=NEsjH1qPi4M2lM2T6IvazfqgFoFJ8N3cwT6wZyatrUE&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Thu Jul 16 10:22:46 2015<br>
@@ -334,6 +334,10 @@ namespace ISD {<br>
/// Byte Swap and Counting operators.<br>
BSWAP, CTTZ, CTLZ, CTPOP,<br>
<br>
+ /// [SU]ABSDIFF - Signed/Unsigned absolute difference of two input integer<br>
+ /// vector. These nodes are generated from llvm.*absdiff* intrinsics.<br>
+ SABSDIFF, UABSDIFF,<br>
+<br>
/// Bit counting operators with an undefined result for zero inputs.<br>
CTTZ_ZERO_UNDEF, CTLZ_ZERO_UNDEF,<br>
<br>
<br>
Modified: llvm/trunk/include/llvm/IR/Intrinsics.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_IR_Intrinsics.td-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=RzUe97WjSD2XUwN_lKJo5I5kvaI7Od_KApLhPpcLQsM&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/Intrinsics.td?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/Intrinsics.td (original)<br>
+++ llvm/trunk/include/llvm/IR/Intrinsics.td Thu Jul 16 10:22:46 2015<br>
@@ -605,6 +605,12 @@ def int_convertuu : Intrinsic<[llvm_any<br>
def int_clear_cache : Intrinsic<[], [llvm_ptr_ty, llvm_ptr_ty],<br>
[], "llvm.clear_cache">;<br>
<br>
+// Calculate the Absolute Differences of the two input vectors.<br>
+def int_sabsdiff : Intrinsic<[llvm_anyvector_ty],<br>
+ [ LLVMMatchType<0>, LLVMMatchType<0> ], [IntrNoMem]>;<br>
+def int_uabsdiff : Intrinsic<[llvm_anyvector_ty],<br>
+ [ LLVMMatchType<0>, LLVMMatchType<0> ], [IntrNoMem]>;<br>
+<br>
//===-------------------------- Masked Intrinsics -------------------------===//<br>
//<br>
def int_masked_store : Intrinsic<[], [llvm_anyvector_ty, LLVMPointerTo<0>,<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_include_llvm_Target_TargetSelectionDAG.td-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=P6hV55emWKVDDg3NZk76sIiWsslaVGF3ZAoUH1D0yVY&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Thu Jul 16 10:22:46 2015<br>
@@ -386,6 +386,8 @@ def smax : SDNode<"ISD::SMAX"<br>
def umin : SDNode<"ISD::UMIN" , SDTIntBinOp>;<br>
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp>;<br>
<br>
+def sabsdiff : SDNode<"ISD::SABSDIFF" , SDTIntBinOp>;<br>
+def uabsdiff : SDNode<"ISD::UABSDIFF" , SDTIntBinOp>;<br>
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;<br>
def bswap : SDNode<"ISD::BSWAP" , SDTIntUnaryOp>;<br>
def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDAG_LegalizeIntegerTypes.cpp-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=VCpvfpXV1TyRWh7gQsf9-1V9RI0aOQTS4HftnrFcFbA&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Thu Jul 16 10:22:46 2015<br>
@@ -146,6 +146,10 @@ void DAGTypeLegalizer::PromoteIntegerRes<br>
case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:<br>
Res = PromoteIntRes_AtomicCmpSwap(cast<AtomicSDNode>(N), ResNo);<br>
break;<br>
+ case ISD::UABSDIFF:<br>
+ case ISD::SABSDIFF:<br>
+ Res = PromoteIntRes_SimpleIntBinOp(N);<br>
+ break;<br>
}<br>
<br>
// If the result is null then the sub-method took care of registering it.<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDAG_LegalizeVectorOps.cpp-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=KlSJcNWhixHni2MsgXS9Hh3ZDODMTp2NHxSjLzsyOBA&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Thu Jul 16 10:22:46 2015<br>
@@ -105,6 +105,7 @@ class VectorLegalizer {<br>
SDValue ExpandLoad(SDValue Op);<br>
SDValue ExpandStore(SDValue Op);<br>
SDValue ExpandFNEG(SDValue Op);<br>
+ SDValue ExpandABSDIFF(SDValue Op);<br>
<br>
/// \brief Implements vector promotion.<br>
///<br>
@@ -326,6 +327,8 @@ SDValue VectorLegalizer::LegalizeOp(SDVa<br>
case ISD::SMAX:<br>
case ISD::UMIN:<br>
case ISD::UMAX:<br>
+ case ISD::UABSDIFF:<br>
+ case ISD::SABSDIFF:<br>
QueryType = Node->getValueType(0);<br>
break;<br>
case ISD::FP_ROUND_INREG:<br>
@@ -708,11 +711,36 @@ SDValue VectorLegalizer::Expand(SDValue<br>
return ExpandFNEG(Op);<br>
case ISD::SETCC:<br>
return UnrollVSETCC(Op);<br>
+ case ISD::UABSDIFF:<br>
+ case ISD::SABSDIFF:<br>
+ return ExpandABSDIFF(Op);<br>
default:<br>
return DAG.UnrollVectorOp(Op.getNode());<br>
}<br>
}<br>
<br>
+SDValue VectorLegalizer::ExpandABSDIFF(SDValue Op) {<br>
+ SDLoc dl(Op);<br>
+ SDValue Tmp1, Tmp2, Tmp3, Tmp4;<br>
+ EVT VT = Op.getValueType();<br>
+ SDNodeFlags Flags;<br>
+ Flags.setNoSignedWrap(Op->getOpcode() == ISD::SABSDIFF);<br>
+<br>
+ Tmp2 = Op.getOperand(0);<br>
+ Tmp3 = Op.getOperand(1);<br>
+ Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp3, &Flags);<br>
+ Tmp2 =<br>
+ DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, dl, VT), Tmp1, &Flags);<br>
+ Tmp4 = DAG.getNode(<br>
+ ISD::SETCC, dl,<br>
+ TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT), Tmp2,<br>
+ DAG.getConstant(0, dl, VT),<br>
+ DAG.getCondCode(Op->getOpcode() == ISD::SABSDIFF ? ISD::SETLT<br>
+ : ISD::SETULT));<br>
+ Tmp1 = DAG.getNode(ISD::VSELECT, dl, VT, Tmp4, Tmp1, Tmp2);<br>
+ return Tmp1;<br>
+}<br>
+<br>
SDValue VectorLegalizer::ExpandSELECT(SDValue Op) {<br>
// Lower a select instruction where the condition is a scalar and the<br>
// operands are vectors. Lower this select to VSELECT and implement it<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDAG_LegalizeVectorTypes.cpp-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=lhcIZXr1fCTwmSeMBX6nGJsIrW7gFsGnN1Od-yKLVH4&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Thu Jul 16 10:22:46 2015<br>
@@ -678,6 +678,8 @@ void DAGTypeLegalizer::SplitVectorResult<br>
case ISD::SMAX:<br>
case ISD::UMIN:<br>
case ISD::UMAX:<br>
+ case ISD::UABSDIFF:<br>
+ case ISD::SABSDIFF:<br>
SplitVecRes_BinOp(N, Lo, Hi);<br>
break;<br>
case ISD::FMA:<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDAG_SelectionDAGBuilder.cpp-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=VXL0buWqSV4iYlnkYMxbIuyXDihfG_hYunAopjM8Ksc&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jul 16 10:22:46 2015<br>
@@ -4646,6 +4646,18 @@ SelectionDAGBuilder::visitIntrinsicCall(<br>
getValue(I.getArgOperand(0)).getValueType(),<br>
getValue(I.getArgOperand(0))));<br>
return nullptr;<br>
+ case Intrinsic::uabsdiff:<br>
+ setValue(&I, DAG.getNode(ISD::UABSDIFF, sdl,<br>
+ getValue(I.getArgOperand(0)).getValueType(),<br>
+ getValue(I.getArgOperand(0)),<br>
+ getValue(I.getArgOperand(1))));<br>
+ return nullptr;<br>
+ case Intrinsic::sabsdiff:<br>
+ setValue(&I, DAG.getNode(ISD::SABSDIFF, sdl,<br>
+ getValue(I.getArgOperand(0)).getValueType(),<br>
+ getValue(I.getArgOperand(0)),<br>
+ getValue(I.getArgOperand(1))));<br>
+ return nullptr;<br>
case Intrinsic::cttz: {<br>
SDValue Arg = getValue(I.getArgOperand(0));<br>
ConstantInt *CI = cast<ConstantInt>(I.getArgOperand(1));<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_SelectionDAG_SelectionDAGDumper.cpp-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=0P7CCF6nZ8LgOdIb2cL-tvpqeD474N_XlOdczKvrebA&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp Thu Jul 16 10:22:46 2015<br>
@@ -225,6 +225,8 @@ std::string SDNode::getOperationName(con<br>
case ISD::SHL_PARTS: return "shl_parts";<br>
case ISD::SRA_PARTS: return "sra_parts";<br>
case ISD::SRL_PARTS: return "srl_parts";<br>
+ case ISD::UABSDIFF: return "uabsdiff";<br>
+ case ISD::SABSDIFF: return "sabsdiff";<br>
<br>
// Conversion operators.<br>
case ISD::SIGN_EXTEND: return "sign_extend";<br>
<br>
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_TargetLoweringBase.cpp-3Frev-3D242409-26r1-3D242408-26r2-3D242409-26view-3Ddiff&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=ruBVXcN05mT-T4iDDytjDh4QDPIbba0fRcuL0b_1q4k&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=242409&r1=242408&r2=242409&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Thu Jul 16 10:22:46 2015<br>
@@ -827,6 +827,8 @@ void TargetLoweringBase::initActions() {<br>
setOperationAction(ISD::USUBO, VT, Expand);<br>
setOperationAction(ISD::SMULO, VT, Expand);<br>
setOperationAction(ISD::UMULO, VT, Expand);<br>
+ setOperationAction(ISD::UABSDIFF, VT, Expand);<br>
+ setOperationAction(ISD::SABSDIFF, VT, Expand);<br>
<br>
// These library functions default to expand.<br>
setOperationAction(ISD::FROUND, VT, Expand);<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/absdiff_expand.ll<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_absdiff-5Fexpand.ll-3Frev-3D242409-26view-3Dauto&d=AwMF-g&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=HbJllLVFFv8CEB1WmickY-eIwe3cI9wWGcF8_3AfqlY&s=Z1OfBrqKiCPnNe_Yg5O3hvN09yAspjTME_RRTugIVDY&e=">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/absdiff_expand.ll?rev=242409&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/absdiff_expand.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/absdiff_expand.ll Thu Jul 16 10:22:46 2015<br>
@@ -0,0 +1,242 @@<br>
+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK<br>
+<br>
+declare <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8>, <4 x i8>)<br>
+<br>
+define <4 x i8> @test_uabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v4i8_expand<br>
+; CHECK: psubd %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: psubd %xmm0, %xmm1<br>
+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br>
+; CHECK-NEXT: movdqa %xmm1, %xmm3<br>
+; CHECK-NEXT: pxor %xmm2, %xmm3<br>
+; CHECK-NEXT: pcmpgtd %xmm3, %xmm2<br>
+; CHECK-NEXT: pand %xmm2, %xmm0<br>
+; CHECK-NEXT: pandn %xmm1, %xmm2<br>
+; CHECK-NEXT: por %xmm2, %xmm0<br>
+; CHECK-NEXT: retq<br>
+<br>
+ %1 = call <4 x i8> @llvm.uabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)<br>
+ ret <4 x i8> %1<br>
+}<br>
+<br>
+declare <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8>, <4 x i8>)<br>
+<br>
+define <4 x i8> @test_sabsdiff_v4i8_expand(<4 x i8> %a1, <4 x i8> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v4i8_expand<br>
+; CHECK: psubd %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: pxor %xmm2, %xmm2<br>
+; CHECK-NEXT: psubd %xmm0, %xmm2<br>
+; CHECK-NEXT: pcmpgtd %xmm2, %xmm1<br>
+; CHECK-NEXT: pand %xmm1, %xmm0<br>
+; CHECK-NEXT: pandn %xmm2, %xmm1<br>
+; CHECK-NEXT: por %xmm1, %xmm0<br>
+; CHECK-NEXT: retq<br>
+<br>
+ %1 = call <4 x i8> @llvm.sabsdiff.v4i8(<4 x i8> %a1, <4 x i8> %a2)<br>
+ ret <4 x i8> %1<br>
+}<br>
+<br>
+<br>
+declare <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8>, <8 x i8>)<br>
+<br>
+define <8 x i8> @test_sabsdiff_v8i8_expand(<8 x i8> %a1, <8 x i8> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v8i8_expand<br>
+; CHECK: psubw %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: pxor %xmm2, %xmm2<br>
+; CHECK-NEXT: psubw %xmm0, %xmm2<br>
+; CHECK-NEXT: pcmpgtw %xmm2, %xmm1<br>
+; CHECK-NEXT: pand %xmm1, %xmm0<br>
+; CHECK-NEXT: pandn %xmm2, %xmm1<br>
+; CHECK-NEXT: por %xmm1, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <8 x i8> @llvm.sabsdiff.v8i8(<8 x i8> %a1, <8 x i8> %a2)<br>
+ ret <8 x i8> %1<br>
+}<br>
+<br>
+declare <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8>, <16 x i8>)<br>
+<br>
+define <16 x i8> @test_uabsdiff_v16i8_expand(<16 x i8> %a1, <16 x i8> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v16i8_expand<br>
+; CHECK: psubb %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: psubb %xmm0, %xmm1<br>
+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br>
+; CHECK-NEXT: movdqa %xmm1, %xmm3<br>
+; CHECK-NEXT: pxor %xmm2, %xmm3<br>
+; CHECK-NEXT: pcmpgtb %xmm3, %xmm2<br>
+; CHECK-NEXT: pand %xmm2, %xmm0<br>
+; CHECK-NEXT: pandn %xmm1, %xmm2<br>
+; CHECK-NEXT: por %xmm2, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <16 x i8> @llvm.uabsdiff.v16i8(<16 x i8> %a1, <16 x i8> %a2)<br>
+ ret <16 x i8> %1<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16>, <8 x i16>)<br>
+<br>
+define <8 x i16> @test_uabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v8i16_expand<br>
+; CHECK: psubw %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: psubw %xmm0, %xmm1<br>
+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br>
+; CHECK-NEXT: movdqa %xmm1, %xmm3<br>
+; CHECK-NEXT: pxor %xmm2, %xmm3<br>
+; CHECK-NEXT: pcmpgtw %xmm3, %xmm2<br>
+; CHECK-NEXT: pand %xmm2, %xmm0<br>
+; CHECK-NEXT: pandn %xmm1, %xmm2<br>
+; CHECK-NEXT: por %xmm2, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <8 x i16> @llvm.uabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)<br>
+ ret <8 x i16> %1<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16>, <8 x i16>)<br>
+<br>
+define <8 x i16> @test_sabsdiff_v8i16_expand(<8 x i16> %a1, <8 x i16> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v8i16_expand<br>
+; CHECK: psubw %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: pxor %xmm2, %xmm2<br>
+; CHECK-NEXT: psubw %xmm0, %xmm2<br>
+; CHECK-NEXT: pcmpgtw %xmm2, %xmm1<br>
+; CHECK-NEXT: pand %xmm1, %xmm0<br>
+; CHECK-NEXT: pandn %xmm2, %xmm1<br>
+; CHECK-NEXT: por %xmm1, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <8 x i16> @llvm.sabsdiff.v8i16(<8 x i16> %a1, <8 x i16> %a2)<br>
+ ret <8 x i16> %1<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32>, <4 x i32>)<br>
+<br>
+define <4 x i32> @test_sabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v4i32_expand<br>
+; CHECK: psubd %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: pxor %xmm2, %xmm2<br>
+; CHECK-NEXT: psubd %xmm0, %xmm2<br>
+; CHECK-NEXT: pcmpgtd %xmm2, %xmm1<br>
+; CHECK-NEXT: pand %xmm1, %xmm0<br>
+; CHECK-NEXT: pandn %xmm2, %xmm1<br>
+; CHECK-NEXT: por %xmm1, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <4 x i32> @llvm.sabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)<br>
+ ret <4 x i32> %1<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32>, <4 x i32>)<br>
+<br>
+define <4 x i32> @test_uabsdiff_v4i32_expand(<4 x i32> %a1, <4 x i32> %a2) {<br>
+; CHECK-LABEL: test_uabsdiff_v4i32_expand<br>
+; CHECK: psubd %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: psubd %xmm0, %xmm1<br>
+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br>
+; CHECK-NEXT: movdqa %xmm1, %xmm3<br>
+; CHECK-NEXT: pxor %xmm2, %xmm3<br>
+; CHECK-NEXT: pcmpgtd %xmm3, %xmm2<br>
+; CHECK-NEXT: pand %xmm2, %xmm0<br>
+; CHECK-NEXT: pandn %xmm1, %xmm2<br>
+; CHECK-NEXT: por %xmm2, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <4 x i32> @llvm.uabsdiff.v4i32(<4 x i32> %a1, <4 x i32> %a2)<br>
+ ret <4 x i32> %1<br>
+}<br>
+<br>
+declare <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32>, <2 x i32>)<br>
+<br>
+define <2 x i32> @test_sabsdiff_v2i32_expand(<2 x i32> %a1, <2 x i32> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v2i32_expand<br>
+; CHECK: psubq %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: psubq %xmm0, %xmm1<br>
+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br>
+; CHECK-NEXT: movdqa %xmm1, %xmm3<br>
+; CHECK-NEXT: pxor %xmm2, %xmm3<br>
+; CHECK-NEXT: movdqa %xmm2, %xmm4<br>
+; CHECK-NEXT: pcmpgtd %xmm3, %xmm4<br>
+; CHECK-NEXT: pshufd $160, %xmm4, %xmm5 # xmm5 = xmm4[0,0,2,2]<br>
+; CHECK-NEXT: pcmpeqd %xmm2, %xmm3<br>
+; CHECK-NEXT: pshufd $245, %xmm3, %xmm2 # xmm2 = xmm3[1,1,3,3]<br>
+; CHECK-NEXT: pand %xmm5, %xmm2<br>
+; CHECK-NEXT: pshufd $245, %xmm4, %xmm3 # xmm3 = xmm4[1,1,3,3]<br>
+; CHECK-NEXT: por %xmm2, %xmm3<br>
+; CHECK-NEXT: pand %xmm3, %xmm0<br>
+; CHECK-NEXT: pandn %xmm1, %xmm3<br>
+; CHECK-NEXT: por %xmm3, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <2 x i32> @llvm.sabsdiff.v2i32(<2 x i32> %a1, <2 x i32> %a2)<br>
+ ret <2 x i32> %1<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64>, <2 x i64>)<br>
+<br>
+define <2 x i64> @test_sabsdiff_v2i64_expand(<2 x i64> %a1, <2 x i64> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v2i64_expand<br>
+; CHECK: psubq %xmm1, %xmm0<br>
+; CHECK-NEXT: pxor %xmm1, %xmm1<br>
+; CHECK-NEXT: psubq %xmm0, %xmm1<br>
+; CHECK-NEXT: movdqa .LCPI{{[0-9_]*}}<br>
+; CHECK-NEXT: movdqa %xmm1, %xmm3<br>
+; CHECK-NEXT: pxor %xmm2, %xmm3<br>
+; CHECK-NEXT: movdqa %xmm2, %xmm4<br>
+; CHECK-NEXT: pcmpgtd %xmm3, %xmm4<br>
+; CHECK-NEXT: pshufd $160, %xmm4, %xmm5 # xmm5 = xmm4[0,0,2,2]<br>
+; CHECK-NEXT: pcmpeqd %xmm2, %xmm3<br>
+; CHECK-NEXT: pshufd $245, %xmm3, %xmm2 # xmm2 = xmm3[1,1,3,3]<br>
+; CHECK-NEXT: pand %xmm5, %xmm2<br>
+; CHECK-NEXT: pshufd $245, %xmm4, %xmm3 # xmm3 = xmm4[1,1,3,3]<br>
+; CHECK-NEXT: por %xmm2, %xmm3<br>
+; CHECK-NEXT: pand %xmm3, %xmm0<br>
+; CHECK-NEXT: pandn %xmm1, %xmm3<br>
+; CHECK-NEXT: por %xmm3, %xmm0<br>
+; CHECK-NEXT: retq<br>
+ %1 = call <2 x i64> @llvm.sabsdiff.v2i64(<2 x i64> %a1, <2 x i64> %a2)<br>
+ ret <2 x i64> %1<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.sabsdiff.v16i32(<16 x i32>, <16 x i32>)<br>
+<br>
+define <16 x i32> @test_sabsdiff_v16i32_expand(<16 x i32> %a1, <16 x i32> %a2) {<br>
+; CHECK-LABEL: test_sabsdiff_v16i32_expand<br>
+; CHECK: psubd %xmm4, %xmm0<br>
+; CHECK-NEXT: pxor %xmm8, %xmm8<br>
+; CHECK-NEXT: pxor %xmm9, %xmm9<br>
+; CHECK-NEXT: psubd %xmm0, %xmm9<br>
+; CHECK-NEXT: pxor %xmm4, %xmm4<br>
+; CHECK-NEXT: pcmpgtd %xmm9, %xmm4<br>
+; CHECK-NEXT: pand %xmm4, %xmm0<br>
+; CHECK-NEXT: pandn %xmm9, %xmm4<br>
+; CHECK-NEXT: por %xmm4, %xmm0<br>
+; CHECK-NEXT: psubd %xmm5, %xmm1<br>
+; CHECK-NEXT: pxor %xmm4, %xmm4<br>
+; CHECK-NEXT: psubd %xmm1, %xmm4<br>
+; CHECK-NEXT: pxor %xmm5, %xmm5<br>
+; CHECK-NEXT: pcmpgtd %xmm4, %xmm5<br>
+; CHECK-NEXT: pand %xmm5, %xmm1<br>
+; CHECK-NEXT: pandn %xmm4, %xmm5<br>
+; CHECK-NEXT: por %xmm5, %xmm1<br>
+; CHECK-NEXT: psubd %xmm6, %xmm2<br>
+; CHECK-NEXT: pxor %xmm4, %xmm4<br>
+; CHECK-NEXT: psubd %xmm2, %xmm4<br>
+; CHECK-NEXT: pxor %xmm5, %xmm5<br>
+; CHECK-NEXT: pcmpgtd %xmm4, %xmm5<br>
+; CHECK-NEXT: pand %xmm5, %xmm2<br>
+; CHECK-NEXT: pandn %xmm4, %xmm5<br>
+; CHECK-NEXT: por %xmm5, %xmm2<br>
+; CHECK-NEXT: psubd %xmm7, %xmm3<br>
+; CHECK-NEXT: pxor %xmm4, %xmm4<br>
+; CHECK-NEXT: psubd %xmm3, %xmm4<br>
+; CHECK-NEXT: pcmpgtd %xmm4, %xmm8<br>
+; CHECK-NEXT: pand %xmm8, %xmm3<br>
+; CHECK-NEXT: pandn %xmm4, %xmm8<br>
+; CHECK-NEXT: por %xmm8, %xmm3<br>
+; CHECK-NEXT: req<br>
</blockquote>
<span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;">The
tests look very fragile, should we make them more relaxed in terms of register names?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
<blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">
+ %1 = call <16 x i32> @llvm.sabsdiff.v16i32(<16 x i32> %a1, <16 x i32> %a2)<br>
+ ret <16 x i32> %1<br>
+}<br>
+<br>
<br>
<br>
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