<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">2015-07-09 13:14 GMT-07:00 Duncan P. N. Exon Smith <span dir="ltr"><<a href="mailto:dexonsmith@apple.com" target="_blank">dexonsmith@apple.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div class=""><div class="h5"><br>
> On 2015-Jul-09, at 12:59, Alex Lorenz <<a href="mailto:arphaman@gmail.com">arphaman@gmail.com</a>> wrote:<br>
><br>
> arphaman updated this revision to Diff 29375.<br>
> arphaman added a comment.<br>
><br>
> I've rebased this patch on ToT.<br>
><br>
><br>
> Repository:<br>
> rL LLVM<br>
><br>
> <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D10981&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=YfFKRCrfxWbJc5L4JQkm1C-7aX_gYWpW05k4I7gDGi0&s=JcWhowqTG4E-rf9ukTj37twXQxidUpR99p31XlnDOtk&e=" rel="noreferrer" target="_blank">http://reviews.llvm.org/D10981</a><br>
><br>
> Files:<br>
> include/llvm/CodeGen/MIRYamlMapping.h<br>
> lib/CodeGen/MIRParser/MIRParser.cpp<br>
> lib/CodeGen/MIRPrinter.cpp<br>
> test/CodeGen/MIR/X86/undefined-register-class.mir<br>
> test/CodeGen/MIR/X86/virtual-registers.mir<br>
><br>
</div></div>> <D10981.29375.patch><br>
<br>
> Index: lib/CodeGen/MIRParser/MIRParser.cpp<br>
> ===================================================================<br>
> --- lib/CodeGen/MIRParser/MIRParser.cpp<br>
> +++ lib/CodeGen/MIRParser/MIRParser.cpp<br>
> @@ -315,14 +326,27 @@<br>
> }<br>
><br>
> bool MIRParserImpl::initializeRegisterInfo(<br>
> - MachineRegisterInfo &RegInfo, const yaml::MachineFunction &YamlMF) {<br>
> + const MachineFunction &MF, MachineRegisterInfo &RegInfo,<br>
> + const yaml::MachineFunction &YamlMF) {<br>
> assert(RegInfo.isSSA());<br>
> if (!YamlMF.IsSSA)<br>
> RegInfo.leaveSSA();<br>
> assert(RegInfo.tracksLiveness());<br>
> if (!YamlMF.TracksRegLiveness)<br>
> RegInfo.invalidateLiveness();<br>
> RegInfo.enableSubRegLiveness(YamlMF.TracksSubRegLiveness);<br>
> +<br>
> + // Parse the virtual register information.<br>
> + for (const auto &VReg : YamlMF.VirtualRegisters) {<br>
> + const auto *RC = getRegClass(MF, VReg.Class.Value);<br>
> + if (!RC)<br>
> + return error(VReg.Class.SourceRange.Start,<br>
> + Twine("use of undefined register class '") +<br>
> + VReg.Class.Value + "'");<br>
> + // TODO: create the mapping from IDs to registers so that the virtual<br>
> + // register references can be parsed corretly.<br>
<br>
s/corretly/correctly/</blockquote><div><br></div><div>Thanks, I missed this typo.</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<br>
I'm not following this TODO. How is that different from the mapping<br>
used in `getRegClass()`?<br></blockquote><div><br></div><div>The mapping in getRegClass maps from strings to register classes, this TODO mapping has to map from</div><div>register IDs as specified in the source to register numbers. </div><div><br></div><div>The IDs can be arbitrary numbers, they don't have to correspond to the actual virtual register numbers</div><div>used internally. The IDs are used for references as well, so when we are parsing the references, we</div><div>have to map from IDs to the virtual register numbers, that's why we need the mapping.</div><div><br></div><div>My follow up patch <span style="line-height:normal"><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D11005&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=YfFKRCrfxWbJc5L4JQkm1C-7aX_gYWpW05k4I7gDGi0&s=jYSzaABIeEyPsfGCiizM1eIk48lo3boAxq8f_XxSbeg&e=">http://reviews.llvm.org/D11005</a> (MIR Serialization: serialize virtual register machine operands.)</span></div><div><span style="line-height:normal">has an example of this:</span></div><div><span style="line-height:normal"><br></span></div><div><div>---</div><div># CHECK: registers:</div><div># CHECK-NEXT: - { id: 0, class: gr32 }</div><div># CHECK-NEXT: - { id: 1, class: gr32 }</div><div># CHECK-NEXT: - { id: 2, class: gr32 }</div><div>registers:</div><div> - { id: 2, class: gr32 }</div><div> - { id: 0, class: gr32 }</div><div> - { id: 10, class: gr32 }</div><div>body:</div><div> - id: 0</div><div> name: entry</div><div> # CHECK: %0 = COPY %edi</div><div> # CHECK-NEXT: %1 = SUB32ri8 %0, 10</div><div> instructions:</div><div> - '%2 = COPY %edi'</div><div> - '%0 = SUB32ri8 %2, 10, implicit-def %eflags'</div><div>...</div></div><div><br></div><div>Notice how the printed register IDs are different than the ones we parsed - that's because the printed IDs use the virtual register numbers, but the in this case the parsed IDs are just arbitrary numbers set by the user.</div><div><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<br>
> + RegInfo.createVirtualRegister(RC);<br>
> + }<br>
> return false;<br>
> }<br>
><br>
> @@ -392,6 +416,26 @@<br>
> Error.getFixIts());<br>
> }<br>
><br>
> +void MIRParserImpl::initNames2RegClasses(const MachineFunction &MF) {<br>
> + if (!Names2RegClasses.empty())<br>
> + return;<br>
> + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();<br>
> + for (unsigned I = 0, E = TRI->getNumRegClasses(); I < E; ++I) {<br>
> + const auto *RC = TRI->getRegClass(I);<br>
> + Names2RegClasses.insert(<br>
> + std::make_pair(StringRef(TRI->getRegClassName(RC)).lower(), RC));<br>
> + }<br>
> +}<br>
> +<br>
> +const TargetRegisterClass *MIRParserImpl::getRegClass(const MachineFunction &MF,<br>
> + StringRef Name) {<br>
> + initNames2RegClasses(MF);<br>
> + auto RegClassInfo = Names2RegClasses.find(Name);<br>
> + if (RegClassInfo == Names2RegClasses.end())<br>
> + return nullptr;<br>
> + return RegClassInfo->getValue();<br>
> +}<br>
> +<br>
> MIRParser::MIRParser(std::unique_ptr<MIRParserImpl> Impl)<br>
> : Impl(std::move(Impl)) {}<br>
><br>
<br>
</blockquote></div><br></div></div>