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<span style="font-family:Calibri,Arial,Helvetica,sans-serif; font-size:11pt; color:black">LGTM<br>
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<span style="color:black">-----Original Message----- <br>
<b>From:</b> Jingyue Wu [jingyue@google.com]<br>
<b>Received:</b> Thursday, 09 Jul 2015, 6:51PM<br>
<b>To:</b> jingyue@google.com [jingyue@google.com]; Justin Holewinski [jholewinski@nvidia.com]<br>
<b>CC:</b> llvm-commits@cs.uiuc.edu [llvm-commits@cs.uiuc.edu]<br>
<b>Subject:</b> [PATCH] D11089: [NVPTX] declare no vector registers<br>
<br>
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<div class="PlainText">jingyue created this revision.<br>
jingyue added a reviewer: jholewinski.<br>
jingyue added a subscriber: llvm-commits.<br>
Herald added a subscriber: jholewinski.<br>
<br>
Without this patch, LoopVectorizer in certain cases (see loop-vectorize.ll)<br>
produces code with complex control flow which hurts later optimizations. Since<br>
NVPTX doesn't have vector registers in LLVM's sense<br>
(NVPTXTTI::getRegisterBitWidth(true) == 32), we for now declare no vector<br>
registers to effectively disable loop vectorization.<br>
<br>
<a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D11089&d=AwMFAg&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=CE_5qflcwo4-BDnrw6Y3NcPOcs37zrNLyj5SBtppQSM&s=rEX_kzFR-58HQE7AgHV-wYdHUySNHboJkVjh4iGX3Q0&e=">http://reviews.llvm.org/D11089</a><br>
<br>
Files:<br>
lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp<br>
lib/Target/NVPTX/NVPTXTargetTransformInfo.h<br>
test/CodeGen/NVPTX/loop-vectorize.ll<br>
<br>
Index: test/CodeGen/NVPTX/loop-vectorize.ll<br>
===================================================================<br>
--- /dev/null<br>
+++ test/CodeGen/NVPTX/loop-vectorize.ll<br>
@@ -0,0 +1,39 @@<br>
+; RUN: opt < %s -O3 -S | FileCheck %s<br>
+<br>
+target datalayout = "e-i64:64-v16:16-v32:32-n16:32:64"<br>
+target triple = "nvptx64-nvidia-cuda"<br>
+<br>
+define void @no_vectorization(i32 %n, i32 %a, i32 %b) {<br>
+; CHECK-LABEL: no_vectorization(<br>
+; CHECK-NOT: <4 x i32><br>
+; CHECK-NOT: <4 x i1><br>
+entry:<br>
+ %cmp.5 = icmp sgt i32 %n, 0<br>
+ br i1 %cmp.5, label %for.body.preheader, label %for.cond.cleanup<br>
+<br>
+for.body.preheader: ; preds = %entry<br>
+ br label %for.body<br>
+<br>
+for.cond.cleanup.loopexit: ; preds = %for.body<br>
+ br label %for.cond.cleanup<br>
+<br>
+for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry<br>
+ ret void<br>
+<br>
+for.body: ; preds = %for.body.preheader, %for.body<br>
+ %i.06 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]<br>
+ %add = add nsw i32 %i.06, %a<br>
+ %mul = mul nsw i32 %add, %b<br>
+ %cmp1 = icmp sgt i32 %mul, -1<br>
+ tail call void @llvm.assume(i1 %cmp1)<br>
+ %inc = add nuw nsw i32 %i.06, 1<br>
+ %exitcond = icmp eq i32 %inc, %n<br>
+ br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body<br>
+}<br>
+<br>
+declare void @llvm.assume(i1) #0<br>
+<br>
+attributes #0 = { nounwind }<br>
+<br>
+!nvvm.annotations = !{!0}<br>
+!0 = !{void (i32, i32, i32)* @no_vectorization, !"kernel", i32 1}<br>
Index: lib/Target/NVPTX/NVPTXTargetTransformInfo.h<br>
===================================================================<br>
--- lib/Target/NVPTX/NVPTXTargetTransformInfo.h<br>
+++ lib/Target/NVPTX/NVPTXTargetTransformInfo.h<br>
@@ -69,6 +69,8 @@<br>
TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,<br>
TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,<br>
TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);<br>
+<br>
+ unsigned getNumberOfRegisters(bool Vector);<br>
};<br>
<br>
} // end namespace llvm<br>
Index: lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp<br>
===================================================================<br>
--- lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp<br>
+++ lib/Target/NVPTX/NVPTXTargetTransformInfo.cpp<br>
@@ -117,3 +117,9 @@<br>
Opd1PropInfo, Opd2PropInfo);<br>
}<br>
}<br>
+<br>
+unsigned NVPTXTTIImpl::getNumberOfRegisters(bool Vector) {<br>
+ if (Vector)<br>
+ return 0;<br>
+ return BaseT::getNumberOfRegisters(Vector);<br>
+}<br>
<br>
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