<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Jul 4, 2015, at 11:53 PM, Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com" class="">elena.demikhovsky@intel.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">><span class="Apple-converted-space"> </span></span>If you'll always want to use the avx512 encoding it seems a little wasteful<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Yes, you are right. But we choose AVX-512 form on instruction selection phase, it gives more registers - 32 instead of 16.<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">We are adding “NoVLX” , “UseAVX” and other predicates to AVX patterns to switch them off in KNL/SKX modes.<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">We’ll need to add a pass after register allocation and replace the long AVX-512 encoding with AVX encoding when possible, but we are not there yet.</div></div></div></blockquote><div><br class=""></div><div>IIRC, ARM does something similar for thumb. Making we can factorize this pass into something generic with hooks?</div><div><br class=""></div><div>My 2c.</div><div><br class=""></div><div>Cheers,</div><div>Q</div><br class=""><blockquote type="cite" class=""><div class=""><div class="WordSection1" style="page: WordSection1; font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span></div><div style="margin: 0cm 0cm 0.0001pt 36pt; font-size: 12pt; font-family: 'Times New Roman', serif; text-indent: -18pt;" class=""><span style="font-family: Calibri, sans-serif; color: rgb(49, 132, 155);" class=""><span class="">-<span style="font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-family: 'Times New Roman';" class=""> <span class="Apple-converted-space"> </span></span></span></span><span dir="LTR" class=""></span><b class=""><i class=""><span style="color: rgb(49, 132, 155);" class=""> Elena<o:p class=""></o:p></span></i></b></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span style="font-size: 10pt; font-family: Tahoma, sans-serif;" class="">From:</span></b><span style="font-size: 10pt; font-family: Tahoma, sans-serif;" class=""><span class="Apple-converted-space"> </span>Eric Christopher [<a href="mailto:echristo@gmail.com" style="color: purple; text-decoration: underline;" class="">mailto:echristo@gmail.com</a>]<span class="Apple-converted-space"> </span><br class=""><b class="">Sent:</b><span class="Apple-converted-space"> </span>Saturday, July 04, 2015 22:10<br class=""><b class="">To:</b><span class="Apple-converted-space"> </span>Badouh, Asaf;<span class="Apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu" style="color: purple; text-decoration: underline;" class="">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br class=""><b class="">Subject:</b><span class="Apple-converted-space"> </span>Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.<o:p class=""></o:p></span></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div><div class=""><p class="MsoNormal" style="margin: 0cm 0cm 12pt; font-size: 12pt; font-family: 'Times New Roman', serif;"><o:p class=""> </o:p></p><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">On Thu, Jul 2, 2015 at 7:04 AM Badouh, Asaf <<a href="mailto:asaf.badouh@intel.com" style="color: purple; text-decoration: underline;" class="">asaf.badouh@intel.com</a>> wrote:<o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin-left: 4.8pt; margin-right: 0cm;" class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">The registers are not always zmm, they might be xmm/ymm as well.</span><o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">Same for the K masks, not always exists.</span><o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">That’s why we thought the best way is to check the prefix.</span><o:p class=""></o:p></div></div></div></blockquote><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Sure, but let's say you're implementing an assembler, how do you know which encoding to use if you get one using xmm/ymm and no k mask?<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">If you'll always want to use the avx512 encoding it seems a little wasteful, but you could also verify that you're assembling correctly via an MC test. If you'll want to base it upon the existence of the register or a k mask then you can do that by checking the assembly and not the encoding.<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">I could be missing something though? :)<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><o:p class=""> </o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">-eric<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin-left: 4.8pt; margin-right: 0cm;" class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class="">-Asaf</span><o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><a name="msg-f:1505593521080878408__MailEndCompos" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span></a><o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">From:</span></b><span style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span class="Apple-converted-space"> </span>Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" target="_blank" style="color: purple; text-decoration: underline;" class="">echristo@gmail.com</a>]<span class="Apple-converted-space"> </span><br class=""><b class="">Sent:</b><span class="Apple-converted-space"> </span>Thursday, July 02, 2015 00:56</span><o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""><br class=""><b class="">To:</b><span class="Apple-converted-space"> </span>Badouh, Asaf;<span class="Apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank" style="color: purple; text-decoration: underline;" class="">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br class=""><b class="">Subject:</b><span class="Apple-converted-space"> </span>Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.</span><o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div><div class=""><p class="MsoNormal" style="margin: 0cm 0cm 12pt; font-size: 12pt; font-family: 'Times New Roman', serif;"> <o:p class=""></o:p></p><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">On Sun, Jun 21, 2015 at 4:28 AM Badouh, Asaf <<a href="mailto:asaf.badouh@intel.com" target="_blank" style="color: purple; text-decoration: underline;" class="">asaf.badouh@intel.com</a>> wrote:<o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin: 5pt 0cm 5pt 4.8pt;" class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Hey Eric,<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">That part of the test is not new, it just moved from other part of the file.<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Anyway (ElenaD & I) agree, it will be better to keep the encoding part out of these tests.<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">But we think we should keep the prefix of the encoding to make sure it’s generate AVX512 code. E.g:<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">+ ; CHECK: vpmaxsq {{.*}}encoding: [0x62<o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">is that ok with you?<o:p class=""></o:p></div></div></div></blockquote><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Can't you just check the register here or whether or not the k mask exists? (I mean, for this instruction in particular it's always going to be avx512 so not an issue, but the general idea applies).<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">I guess if it's not deducible otherwise, sure, but I find it hard to believe it's completely unknowable from text.<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">-eric<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin: 5pt 0cm 5pt 4.8pt;" class=""><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">-Asaf<o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><a name="msg-f:1505593521080878408_msg-f:15045871" class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif; color: rgb(31, 73, 125);" class=""> </span></a><o:p class=""></o:p></div><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><b class=""><span style="font-size: 11pt; font-family: Calibri, sans-serif;" class="">From:</span></b><span style="font-size: 11pt; font-family: Calibri, sans-serif;" class=""><span class="Apple-converted-space"> </span>Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" target="_blank" style="color: purple; text-decoration: underline;" class="">echristo@gmail.com</a>]<span class="Apple-converted-space"> </span><br class=""><b class="">Sent:</b><span class="Apple-converted-space"> </span>Friday, June 19, 2015 03:55<br class=""><b class="">To:</b><span class="Apple-converted-space"> </span>Badouh, Asaf;<span class="Apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank" style="color: purple; text-decoration: underline;" class="">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br class=""><b class="">Subject:</b><span class="Apple-converted-space"> </span>Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.</span><o:p class=""></o:p></div></div></div><div class=""><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Hi Asaf,<o:p class=""></o:p></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">I have a question here:<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div><div class=""><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin: 5pt 0cm 5pt 4.8pt;" class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""><br class="">+<br class="">+define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {<br class="">+ ; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]<o:p class=""></o:p></div></blockquote><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">Why are you checking the encoding of instructions in the CodeGen tests? This sort of thing belongs in the MC tests for the instructions. It looks like there are already encoding tests so I'm not sure what you're attempting to check here? You don't appear to be checking the actual operands to the instruction.<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">-eric<o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><div class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class=""> <o:p class=""></o:p></div></div><blockquote style="border-style: none none none solid; border-left-color: rgb(204, 204, 204); border-left-width: 1pt; padding: 0cm 0cm 0cm 6pt; margin: 5pt 0cm 5pt 4.8pt;" class=""><div style="margin: 0cm 0cm 0.0001pt; font-size: 12pt; font-family: 'Times New Roman', serif;" class="">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,<br class="">+ <8 x i64>zeroinitializer, i8 -1)<br class="">+ ret <8 x i64> %res<br class="">+}<br class="">+declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br class="">+<br class="">+define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {<br class="">+ ; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]<br class="">+ %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %a0, <16 x i32> %a1,<br class="">+ <16 x i32>zeroinitializer, i16 -1)<br class="">+ ret <16 x i32> %res<br class="">+}<br class="">+declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br class="">+<br class="">+define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {<br class="">+ ; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]<br class="">+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %a0, <16 x i32> %a1,<br class="">+ <16 x i32>zeroinitializer, i16 -1)<br class="">+ ret <16 x i32> %res<br class="">+}<br class="">+declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsd %zmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i32>@test_int_x86_avx512_mask_pmaxs_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br class="">+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br class="">+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br class="">+ %res2 = add <16 x i32> %res, %res1<br class="">+ ret <16 x i32> %res2<br class="">+}<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsq %zmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br class="">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br class="">+ %res2 = add <8 x i64> %res, %res1<br class="">+ ret <8 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxud %zmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i32>@test_int_x86_avx512_mask_pmaxu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br class="">+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br class="">+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br class="">+ %res2 = add <16 x i32> %res, %res1<br class="">+ ret <16 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxuq %zmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br class="">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br class="">+ %res2 = add <8 x i64> %res, %res1<br class="">+ ret <8 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsd %zmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i32>@test_int_x86_avx512_mask_pmins_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br class="">+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br class="">+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br class="">+ %res2 = add <16 x i32> %res, %res1<br class="">+ ret <16 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsq %zmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br class="">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br class="">+ %res2 = add <8 x i64> %res, %res1<br class="">+ ret <8 x i64> %res2<br class="">+}<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminud %zmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i32>@test_int_x86_avx512_mask_pminu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br class="">+ %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br class="">+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br class="">+ %res2 = add <16 x i32> %res, %res1<br class="">+ ret <16 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminuq %zmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br class="">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br class="">+ %res2 = add <8 x i64> %res, %res1<br class="">+ ret <8 x i64> %res2<br class="">+}<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bw-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=l2CfvWbH5zN6oCcS_BQGHT9gvjP9HJeuucNqMArPh6E&e=" target="_blank" style="color: purple; text-decoration: underline;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Tue Jun 16 03:39:27 2015<br class="">@@ -788,3 +788,107 @@ define <32 x i16> @test_mask_subs_epu16_<br class=""> }<br class=""><br class=""> declare <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br class="">+<br class="">+declare <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsb %zmm<br class="">+; CHECK: {%k1}<br class="">+define <64 x i8>@test_int_x86_avx512_mask_pmaxs_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br class="">+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br class="">+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br class="">+ %res2 = add <64 x i8> %res, %res1<br class="">+ ret <64 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsw %zmm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i16>@test_int_x86_avx512_mask_pmaxs_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br class="">+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br class="">+ %res2 = add <32 x i16> %res, %res1<br class="">+ ret <32 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxub %zmm<br class="">+; CHECK: {%k1}<br class="">+define <64 x i8>@test_int_x86_avx512_mask_pmaxu_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br class="">+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br class="">+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br class="">+ %res2 = add <64 x i8> %res, %res1<br class="">+ ret <64 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxuw %zmm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i16>@test_int_x86_avx512_mask_pmaxu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br class="">+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br class="">+ %res2 = add <32 x i16> %res, %res1<br class="">+ ret <32 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsb %zmm<br class="">+; CHECK: {%k1}<br class="">+define <64 x i8>@test_int_x86_avx512_mask_pmins_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br class="">+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br class="">+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br class="">+ %res2 = add <64 x i8> %res, %res1<br class="">+ ret <64 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsw %zmm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i16>@test_int_x86_avx512_mask_pmins_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br class="">+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br class="">+ %res2 = add <32 x i16> %res, %res1<br class="">+ ret <32 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminub %zmm<br class="">+; CHECK: {%k1}<br class="">+define <64 x i8>@test_int_x86_avx512_mask_pminu_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br class="">+ %res = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br class="">+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br class="">+ %res2 = add <64 x i8> %res, %res1<br class="">+ ret <64 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_512<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminuw %zmm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i16>@test_int_x86_avx512_mask_pminu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br class="">+ %res = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br class="">+ %res2 = add <32 x i16> %res, %res1<br class="">+ ret <32 x i16> %res2<br class="">+}<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bwvl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=MtmaJB0CzZzn3oacEiXC67zfqRtscKdLRstzKzdNyIk&e=" target="_blank" style="color: purple; text-decoration: underline;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Tue Jun 16 03:39:27 2015<br class="">@@ -2667,4 +2667,212 @@ define <32 x i8> @test_mask_subs_epu8_rm<br class=""> ret <32 x i8> %res<br class=""> }<br class=""><br class="">-declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br class="">\ No newline at end of file<br class="">+declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br class="">+<br class="">+declare <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsb %xmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i8>@test_int_x86_avx512_mask_pmaxs_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br class="">+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2 ,i16 %mask)<br class="">+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i8> %res, %res1<br class="">+ ret <16 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsb %ymm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i8>@test_int_x86_avx512_mask_pmaxs_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br class="">+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br class="">+ %res2 = add <32 x i8> %res, %res1<br class="">+ ret <32 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsw %xmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i16>@test_int_x86_avx512_mask_pmaxs_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br class="">+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br class="">+ %res2 = add <8 x i16> %res, %res1<br class="">+ ret <8 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsw %ymm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i16>@test_int_x86_avx512_mask_pmaxs_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br class="">+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i16> %res, %res1<br class="">+ ret <16 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxub %xmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i8>@test_int_x86_avx512_mask_pmaxu_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2,i16 %mask) {<br class="">+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i8> %res, %res1<br class="">+ ret <16 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxub %ymm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i8>@test_int_x86_avx512_mask_pmaxu_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br class="">+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br class="">+ %res2 = add <32 x i8> %res, %res1<br class="">+ ret <32 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxuw %xmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i16>@test_int_x86_avx512_mask_pmaxu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br class="">+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br class="">+ %res2 = add <8 x i16> %res, %res1<br class="">+ ret <8 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxuw %ymm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i16>@test_int_x86_avx512_mask_pmaxu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br class="">+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i16> %res, %res1<br class="">+ ret <16 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsb %xmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i8>@test_int_x86_avx512_mask_pmins_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br class="">+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i8> %res, %res1<br class="">+ ret <16 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsb %ymm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i8>@test_int_x86_avx512_mask_pmins_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br class="">+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br class="">+ %res2 = add <32 x i8> %res, %res1<br class="">+ ret <32 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsw %xmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i16>@test_int_x86_avx512_mask_pmins_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br class="">+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br class="">+ %res2 = add <8 x i16> %res, %res1<br class="">+ ret <8 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsw %ymm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i16>@test_int_x86_avx512_mask_pmins_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br class="">+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i16> %res, %res1<br class="">+ ret <16 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminub %xmm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i8>@test_int_x86_avx512_mask_pminu_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br class="">+ %res = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i8> %res, %res1<br class="">+ ret <16 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminub %ymm<br class="">+; CHECK: {%k1}<br class="">+define <32 x i8>@test_int_x86_avx512_mask_pminu_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br class="">+ %res = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br class="">+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br class="">+ %res2 = add <32 x i8> %res, %res1<br class="">+ ret <32 x i8> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminuw %xmm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i16>@test_int_x86_avx512_mask_pminu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br class="">+ %res = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br class="">+ %res2 = add <8 x i16> %res, %res1<br class="">+ ret <8 x i16> %res2<br class="">+}<br class="">+<br class="">+declare <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminuw %ymm<br class="">+; CHECK: {%k1}<br class="">+define <16 x i16>@test_int_x86_avx512_mask_pminu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br class="">+ %res = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br class="">+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br class="">+ %res2 = add <16 x i16> %res, %res1<br class="">+ ret <16 x i16> %res2<br class="">+}<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512vl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMGaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=UIMllYOV9zVvdH0EELVtf4VoGaWlr305iU8ikomVKlw&s=zwhhFLV2ynU3ASlzxB54u4fXW6WuknAXsqatLJz0MFs&e=" target="_blank" style="color: purple; text-decoration: underline;" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Tue Jun 16 03:39:27 2015<br class="">@@ -2586,4 +2586,212 @@ define <8 x float> @test_getexp_ps_256(<<br class=""> %res = call <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 -1)<br class=""> ret <8 x float> %res<br class=""> }<br class="">-declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br class="">\ No newline at end of file<br class="">+declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br class="">+<br class="">+declare <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsd %xmm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i32>@test_int_x86_avx512_mask_pmaxs_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br class="">+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2 ,i8 %mask)<br class="">+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i32> %res, %res1<br class="">+ ret <4 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsd %ymm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i32>@test_int_x86_avx512_mask_pmaxs_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br class="">+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br class="">+ %res2 = add <8 x i32> %res, %res1<br class="">+ ret <8 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsq %xmm<br class="">+; CHECK: {%k1}<br class="">+define <2 x i64>@test_int_x86_avx512_mask_pmaxs_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br class="">+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br class="">+ %res2 = add <2 x i64> %res, %res1<br class="">+ ret <2 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxsq %ymm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i64>@test_int_x86_avx512_mask_pmaxs_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br class="">+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i64> %res, %res1<br class="">+ ret <4 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxud %xmm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i32>@test_int_x86_avx512_mask_pmaxu_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2,i8 %mask) {<br class="">+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i32> %res, %res1<br class="">+ ret <4 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxud %ymm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i32>@test_int_x86_avx512_mask_pmaxu_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br class="">+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br class="">+ %res2 = add <8 x i32> %res, %res1<br class="">+ ret <8 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxuq %xmm<br class="">+; CHECK: {%k1}<br class="">+define <2 x i64>@test_int_x86_avx512_mask_pmaxu_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br class="">+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br class="">+ %res2 = add <2 x i64> %res, %res1<br class="">+ ret <2 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpmaxuq %ymm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i64>@test_int_x86_avx512_mask_pmaxu_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br class="">+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i64> %res, %res1<br class="">+ ret <4 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsd %xmm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i32>@test_int_x86_avx512_mask_pmins_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br class="">+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i32> %res, %res1<br class="">+ ret <4 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsd %ymm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i32>@test_int_x86_avx512_mask_pmins_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br class="">+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br class="">+ %res2 = add <8 x i32> %res, %res1<br class="">+ ret <8 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsq %xmm<br class="">+; CHECK: {%k1}<br class="">+define <2 x i64>@test_int_x86_avx512_mask_pmins_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br class="">+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br class="">+ %res2 = add <2 x i64> %res, %res1<br class="">+ ret <2 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminsq %ymm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i64>@test_int_x86_avx512_mask_pmins_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br class="">+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i64> %res, %res1<br class="">+ ret <4 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminud %xmm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i32>@test_int_x86_avx512_mask_pminu_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br class="">+ %res = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i32> %res, %res1<br class="">+ ret <4 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminud %ymm<br class="">+; CHECK: {%k1}<br class="">+define <8 x i32>@test_int_x86_avx512_mask_pminu_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br class="">+ %res = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br class="">+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br class="">+ %res2 = add <8 x i32> %res, %res1<br class="">+ ret <8 x i32> %res2<br class="">+}<br class="">+<br class="">+declare <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_128<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminuq %xmm<br class="">+; CHECK: {%k1}<br class="">+define <2 x i64>@test_int_x86_avx512_mask_pminu_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br class="">+ %res = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br class="">+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br class="">+ %res2 = add <2 x i64> %res, %res1<br class="">+ ret <2 x i64> %res2<br class="">+}<br class="">+<br class="">+declare <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br class="">+<br class="">+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_256<br class="">+; CHECK-NOT: call<br class="">+; CHECK: vpminuq %ymm<br class="">+; CHECK: {%k1}<br class="">+define <4 x i64>@test_int_x86_avx512_mask_pminu_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br class="">+ %res = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br class="">+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br class="">+ %res2 = add <4 x i64> %res, %res1<br class="">+ ret <4 x i64> %res2<br class="">+}<br class="">\ No newline at end of file<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank" style="color: purple; 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