<div dir="ltr"><br><br><div class="gmail_quote"><div dir="ltr">On Thu, Jul 2, 2015 at 7:04 AM Badouh, Asaf <<a href="mailto:asaf.badouh@intel.com">asaf.badouh@intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">The registers are not always zmm, they might be xmm/ymm as well.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">Same for the K masks, not always exists.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">That’s why we thought the best way is to check the prefix.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"></span></p></div></div></blockquote><div>Sure, but let's say you're implementing an assembler, how do you know which encoding to use if you get one using xmm/ymm and no k mask?</div><div><br></div><div>If you'll always want to use the avx512 encoding it seems a little wasteful, but you could also verify that you're assembling correctly via an MC test. If you'll want to base it upon the existence of the register or a k mask then you can do that by checking the assembly and not the encoding.</div><div><br></div><div>I could be missing something though? :)</div><div><br></div><div>-eric</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div lang="EN-US" link="blue" vlink="purple"><div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d">-Asaf<u></u><u></u></span></p>
<p class="MsoNormal"><a name="msg-f:1505593521080878408__MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"><u></u> <u></u></span></a></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>]
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<b>Sent:</b> Thursday, July 02, 2015 00:56</span></p></div></div><div lang="EN-US" link="blue" vlink="purple"><div><p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"><br>
<b>To:</b> Badouh, Asaf; <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br>
<b>Subject:</b> Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.<u></u><u></u></span></p></div></div><div lang="EN-US" link="blue" vlink="purple"><div>
<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal" style="margin-bottom:12.0pt"><u></u> <u></u></p>
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<p class="MsoNormal">On Sun, Jun 21, 2015 at 4:28 AM Badouh, Asaf <<a href="mailto:asaf.badouh@intel.com" target="_blank">asaf.badouh@intel.com</a>> wrote:<u></u><u></u></p>
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<p class="MsoNormal">Hey Eric,<u></u><u></u></p>
<p class="MsoNormal">That part of the test is not new, it just moved from other part of the file.<u></u><u></u></p>
<p class="MsoNormal">Anyway (ElenaD & I) agree, it will be better to keep the encoding part out of these tests.<u></u><u></u></p>
<p class="MsoNormal">But we think we should keep the prefix of the encoding to make sure it’s generate AVX512 code. E.g:
<u></u><u></u></p>
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<p class="MsoNormal">+ ; CHECK: vpmaxsq {{.*}}encoding: [0x62<u></u><u></u></p>
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<p class="MsoNormal">is that ok with you?<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">Can't you just check the register here or whether or not the k mask exists? (I mean, for this instruction in particular it's always going to be avx512 so not an issue, but the general idea applies).<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">I guess if it's not deducible otherwise, sure, but I find it hard to believe it's completely unknowable from text.<u></u><u></u></p>
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<p class="MsoNormal"><u></u> <u></u></p>
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<p class="MsoNormal">-eric<u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal">-Asaf<u></u><u></u></p>
<p class="MsoNormal"><a name="msg-f:1505593521080878408_msg-f:1504587132581731956__MailEndCompos"><span style="font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1f497d"> </span></a><u></u><u></u></p>
<p class="MsoNormal"><b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif">From:</span></b><span style="font-size:11.0pt;font-family:"Calibri",sans-serif"> Eric Christopher [mailto:<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>]
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<b>Sent:</b> Friday, June 19, 2015 03:55<br>
<b>To:</b> Badouh, Asaf; <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">
llvm-commits@cs.uiuc.edu</a>; Demikhovsky, Elena<br>
<b>Subject:</b> Re: [llvm] r239806 - [AVX512] add integer min/max intrinsics support.</span><u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal">Hi Asaf,<u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal">I have a question here:<u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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+<br>
+define <8 x i64> @test_vpmaxq(<8 x i64> %a0, <8 x i64> %a1) {<br>
+ ; CHECK: vpmaxsq {{.*}}encoding: [0x62,0xf2,0xfd,0x48,0x3d,0xc1]<u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal">Why are you checking the encoding of instructions in the CodeGen tests? This sort of thing belongs in the MC tests for the instructions. It looks like there are already encoding
tests so I'm not sure what you're attempting to check here? You don't appear to be checking the actual operands to the instruction.<u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal">-eric<u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal"> <u></u><u></u></p>
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<p class="MsoNormal">+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %a0, <8 x i64> %a1,<br>
+ <8 x i64>zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+declare <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>
+<br>
+define <16 x i32> @test_vpminud(<16 x i32> %a0, <16 x i32> %a1) {<br>
+ ; CHECK: vpminud {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3b,0xc1]<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %a0, <16 x i32> %a1,<br>
+ <16 x i32>zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+declare <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>
+<br>
+define <16 x i32> @test_vpmaxsd(<16 x i32> %a0, <16 x i32> %a1) {<br>
+ ; CHECK: vpmaxsd {{.*}}encoding: [0x62,0xf2,0x7d,0x48,0x3d,0xc1]<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %a0, <16 x i32> %a1,<br>
+ <16 x i32>zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+declare <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsd %zmm<br>
+; CHECK: {%k1}<br>
+define <16 x i32>@test_int_x86_avx512_mask_pmaxs_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>
+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxs.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>
+ %res2 = add <16 x i32> %res, %res1<br>
+ ret <16 x i32> %res2<br>
+}<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsq %zmm<br>
+; CHECK: {%k1}<br>
+define <8 x i64>@test_int_x86_avx512_mask_pmaxs_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>
+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxs.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>
+ %res2 = add <8 x i64> %res, %res1<br>
+ ret <8 x i64> %res2<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxud %zmm<br>
+; CHECK: {%k1}<br>
+define <16 x i32>@test_int_x86_avx512_mask_pmaxu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>
+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmaxu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>
+ %res2 = add <16 x i32> %res, %res1<br>
+ ret <16 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxuq %zmm<br>
+; CHECK: {%k1}<br>
+define <8 x i64>@test_int_x86_avx512_mask_pmaxu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>
+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmaxu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>
+ %res2 = add <8 x i64> %res, %res1<br>
+ ret <8 x i64> %res2<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32>, <16 x i32>, <16 x i32>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsd %zmm<br>
+; CHECK: {%k1}<br>
+define <16 x i32>@test_int_x86_avx512_mask_pmins_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>
+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pmins.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>
+ %res2 = add <16 x i32> %res, %res1<br>
+ ret <16 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsq %zmm<br>
+; CHECK: {%k1}<br>
+define <8 x i64>@test_int_x86_avx512_mask_pmins_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>
+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pmins.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>
+ %res2 = add <8 x i64> %res, %res1<br>
+ ret <8 x i64> %res2<br>
+}<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminud %zmm<br>
+; CHECK: {%k1}<br>
+define <16 x i32>@test_int_x86_avx512_mask_pminu_d_512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3) {<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 %x3)<br>
+ %res1 = call <16 x i32> @llvm.x86.avx512.mask.pminu.d.512(<16 x i32> %x0, <16 x i32> %x1, <16 x i32> %x2, i16 -1)<br>
+ %res2 = add <16 x i32> %res, %res1<br>
+ ret <16 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64>, <8 x i64>, <8 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminuq %zmm<br>
+; CHECK: {%k1}<br>
+define <8 x i64>@test_int_x86_avx512_mask_pminu_q_512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3) {<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 %x3)<br>
+ %res1 = call <8 x i64> @llvm.x86.avx512.mask.pminu.q.512(<8 x i64> %x0, <8 x i64> %x1, <8 x i64> %x2, i8 -1)<br>
+ %res2 = add <8 x i64> %res, %res1<br>
+ ret <8 x i64> %res2<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bw-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=1qKcCeU1Xk1tOZfBupbJ0bsdTY6FpmSDm1E9jQ65Wo8&s=nnwJ4aocwFpa9ONZBDT9Xoo22isWiwXA8n1aU0Oz714&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512bw-intrinsics.ll Tue Jun 16 03:39:27 2015<br>
@@ -788,3 +788,107 @@ define <32 x i16> @test_mask_subs_epu16_<br>
}<br>
<br>
declare <32 x i16> @llvm.x86.avx512.mask.psubus.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>
+<br>
+declare <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsb %zmm<br>
+; CHECK: {%k1}<br>
+define <64 x i8>@test_int_x86_avx512_mask_pmaxs_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>
+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>
+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxs.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>
+ %res2 = add <64 x i8> %res, %res1<br>
+ ret <64 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsw %zmm<br>
+; CHECK: {%k1}<br>
+define <32 x i16>@test_int_x86_avx512_mask_pmaxs_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>
+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxs.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
+ %res2 = add <32 x i16> %res, %res1<br>
+ ret <32 x i16> %res2<br>
+}<br>
+<br>
+declare <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxub %zmm<br>
+; CHECK: {%k1}<br>
+define <64 x i8>@test_int_x86_avx512_mask_pmaxu_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>
+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>
+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmaxu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>
+ %res2 = add <64 x i8> %res, %res1<br>
+ ret <64 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxuw %zmm<br>
+; CHECK: {%k1}<br>
+define <32 x i16>@test_int_x86_avx512_mask_pmaxu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>
+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmaxu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
+ %res2 = add <32 x i16> %res, %res1<br>
+ ret <32 x i16> %res2<br>
+}<br>
+<br>
+declare <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsb %zmm<br>
+; CHECK: {%k1}<br>
+define <64 x i8>@test_int_x86_avx512_mask_pmins_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>
+ %res = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>
+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pmins.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>
+ %res2 = add <64 x i8> %res, %res1<br>
+ ret <64 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsw %zmm<br>
+; CHECK: {%k1}<br>
+define <32 x i16>@test_int_x86_avx512_mask_pmins_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>
+ %res = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pmins.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
+ %res2 = add <32 x i16> %res, %res1<br>
+ ret <32 x i16> %res2<br>
+}<br>
+<br>
+declare <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8>, <64 x i8>, <64 x i8>, i64)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminub %zmm<br>
+; CHECK: {%k1}<br>
+define <64 x i8>@test_int_x86_avx512_mask_pminu_b_512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3) {<br>
+ %res = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 %x3)<br>
+ %res1 = call <64 x i8> @llvm.x86.avx512.mask.pminu.b.512(<64 x i8> %x0, <64 x i8> %x1, <64 x i8> %x2, i64 -1)<br>
+ %res2 = add <64 x i8> %res, %res1<br>
+ ret <64 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16>, <32 x i16>, <32 x i16>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_512<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminuw %zmm<br>
+; CHECK: {%k1}<br>
+define <32 x i16>@test_int_x86_avx512_mask_pminu_w_512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3) {<br>
+ %res = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 %x3)<br>
+ %res1 = call <32 x i16> @llvm.x86.avx512.mask.pminu.w.512(<32 x i16> %x0, <32 x i16> %x1, <32 x i16> %x2, i32 -1)<br>
+ %res2 = add <32 x i16> %res, %res1<br>
+ ret <32 x i16> %res2<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512bwvl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=1qKcCeU1Xk1tOZfBupbJ0bsdTY6FpmSDm1E9jQ65Wo8&s=1RjEQvBdn5oNBdveaRvNoFvrylN0C49PnnyooAmITyk&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512bwvl-intrinsics.ll Tue Jun 16 03:39:27 2015<br>
@@ -2667,4 +2667,212 @@ define <32 x i8> @test_mask_subs_epu8_rm<br>
ret <32 x i8> %res<br>
}<br>
<br>
-declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>
\ No newline at end of file<br>
+declare <32 x i8> @llvm.x86.avx512.mask.psubus.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>
+<br>
+declare <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsb %xmm<br>
+; CHECK: {%k1}<br>
+define <16 x i8>@test_int_x86_avx512_mask_pmaxs_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br>
+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2 ,i16 %mask)<br>
+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxs.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i8> %res, %res1<br>
+ ret <16 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_b_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsb %ymm<br>
+; CHECK: {%k1}<br>
+define <32 x i8>@test_int_x86_avx512_mask_pmaxs_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>
+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>
+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxs.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>
+ %res2 = add <32 x i8> %res, %res1<br>
+ ret <32 x i8> %res2<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsw %xmm<br>
+; CHECK: {%k1}<br>
+define <8 x i16>@test_int_x86_avx512_mask_pmaxs_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>
+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>
+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxs.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>
+ %res2 = add <8 x i16> %res, %res1<br>
+ ret <8 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_w_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsw %ymm<br>
+; CHECK: {%k1}<br>
+define <16 x i16>@test_int_x86_avx512_mask_pmaxs_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>
+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>
+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxs.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i16> %res, %res1<br>
+ ret <16 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxub %xmm<br>
+; CHECK: {%k1}<br>
+define <16 x i8>@test_int_x86_avx512_mask_pmaxu_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2,i16 %mask) {<br>
+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br>
+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmaxu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i8> %res, %res1<br>
+ ret <16 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_b_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxub %ymm<br>
+; CHECK: {%k1}<br>
+define <32 x i8>@test_int_x86_avx512_mask_pmaxu_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>
+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>
+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmaxu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>
+ %res2 = add <32 x i8> %res, %res1<br>
+ ret <32 x i8> %res2<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxuw %xmm<br>
+; CHECK: {%k1}<br>
+define <8 x i16>@test_int_x86_avx512_mask_pmaxu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>
+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>
+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmaxu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>
+ %res2 = add <8 x i16> %res, %res1<br>
+ ret <8 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_w_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxuw %ymm<br>
+; CHECK: {%k1}<br>
+define <16 x i16>@test_int_x86_avx512_mask_pmaxu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>
+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>
+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmaxu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i16> %res, %res1<br>
+ ret <16 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsb %xmm<br>
+; CHECK: {%k1}<br>
+define <16 x i8>@test_int_x86_avx512_mask_pmins_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br>
+ %res = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br>
+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pmins.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i8> %res, %res1<br>
+ ret <16 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_b_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsb %ymm<br>
+; CHECK: {%k1}<br>
+define <32 x i8>@test_int_x86_avx512_mask_pmins_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>
+ %res = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>
+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pmins.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>
+ %res2 = add <32 x i8> %res, %res1<br>
+ ret <32 x i8> %res2<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsw %xmm<br>
+; CHECK: {%k1}<br>
+define <8 x i16>@test_int_x86_avx512_mask_pmins_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>
+ %res = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>
+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pmins.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>
+ %res2 = add <8 x i16> %res, %res1<br>
+ ret <8 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_w_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsw %ymm<br>
+; CHECK: {%k1}<br>
+define <16 x i16>@test_int_x86_avx512_mask_pmins_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>
+ %res = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>
+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pmins.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i16> %res, %res1<br>
+ ret <16 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminub %xmm<br>
+; CHECK: {%k1}<br>
+define <16 x i8>@test_int_x86_avx512_mask_pminu_b_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask) {<br>
+ %res = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %mask)<br>
+ %res1 = call <16 x i8> @llvm.x86.avx512.mask.pminu.b.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i8> %res, %res1<br>
+ ret <16 x i8> %res2<br>
+}<br>
+<br>
+declare <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_b_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminub %ymm<br>
+; CHECK: {%k1}<br>
+define <32 x i8>@test_int_x86_avx512_mask_pminu_b_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {<br>
+ %res = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)<br>
+ %res1 = call <32 x i8> @llvm.x86.avx512.mask.pminu.b.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)<br>
+ %res2 = add <32 x i8> %res, %res1<br>
+ ret <32 x i8> %res2<br>
+}<br>
+<br>
+declare <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16>, <8 x i16>, <8 x i16>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminuw %xmm<br>
+; CHECK: {%k1}<br>
+define <8 x i16>@test_int_x86_avx512_mask_pminu_w_128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3) {<br>
+ %res = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 %x3)<br>
+ %res1 = call <8 x i16> @llvm.x86.avx512.mask.pminu.w.128(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, i8 -1)<br>
+ %res2 = add <8 x i16> %res, %res1<br>
+ ret <8 x i16> %res2<br>
+}<br>
+<br>
+declare <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16>, <16 x i16>, <16 x i16>, i16)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_w_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminuw %ymm<br>
+; CHECK: {%k1}<br>
+define <16 x i16>@test_int_x86_avx512_mask_pminu_w_256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask) {<br>
+ %res = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, i16 %mask)<br>
+ %res1 = call <16 x i16> @llvm.x86.avx512.mask.pminu.w.256(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> zeroinitializer, i16 %mask)<br>
+ %res2 = add <16 x i16> %res, %res1<br>
+ ret <16 x i16> %res2<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_X86_avx512vl-2Dintrinsics.ll-3Frev-3D239806-26r1-3D239805-26r2-3D239806-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=1qKcCeU1Xk1tOZfBupbJ0bsdTY6FpmSDm1E9jQ65Wo8&s=36XaWiI6Cop9PeyNMjKXsxr7nJcjTXGLMkcL2aF6RAk&e=" target="_blank">
http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll?rev=239806&r1=239805&r2=239806&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512vl-intrinsics.ll Tue Jun 16 03:39:27 2015<br>
@@ -2586,4 +2586,212 @@ define <8 x float> @test_getexp_ps_256(<<br>
%res = call <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float> %a0, <8 x float> zeroinitializer, i8 -1)<br>
ret <8 x float> %res<br>
}<br>
-declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br>
\ No newline at end of file<br>
+declare <8 x float> @llvm.x86.avx512.mask.getexp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br>
+<br>
+declare <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsd %xmm<br>
+; CHECK: {%k1}<br>
+define <4 x i32>@test_int_x86_avx512_mask_pmaxs_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br>
+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2 ,i8 %mask)<br>
+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxs.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i32> %res, %res1<br>
+ ret <4 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_d_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsd %ymm<br>
+; CHECK: {%k1}<br>
+define <8 x i32>@test_int_x86_avx512_mask_pmaxs_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>
+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>
+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxs.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>
+ %res2 = add <8 x i32> %res, %res1<br>
+ ret <8 x i32> %res2<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsq %xmm<br>
+; CHECK: {%k1}<br>
+define <2 x i64>@test_int_x86_avx512_mask_pmaxs_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>
+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>
+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxs.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>
+ %res2 = add <2 x i64> %res, %res1<br>
+ ret <2 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxs_q_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxsq %ymm<br>
+; CHECK: {%k1}<br>
+define <4 x i64>@test_int_x86_avx512_mask_pmaxs_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>
+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>
+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxs.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i64> %res, %res1<br>
+ ret <4 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxud %xmm<br>
+; CHECK: {%k1}<br>
+define <4 x i32>@test_int_x86_avx512_mask_pmaxu_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2,i8 %mask) {<br>
+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br>
+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmaxu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i32> %res, %res1<br>
+ ret <4 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_d_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxud %ymm<br>
+; CHECK: {%k1}<br>
+define <8 x i32>@test_int_x86_avx512_mask_pmaxu_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>
+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>
+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmaxu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>
+ %res2 = add <8 x i32> %res, %res1<br>
+ ret <8 x i32> %res2<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxuq %xmm<br>
+; CHECK: {%k1}<br>
+define <2 x i64>@test_int_x86_avx512_mask_pmaxu_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>
+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>
+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmaxu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>
+ %res2 = add <2 x i64> %res, %res1<br>
+ ret <2 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmaxu_q_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpmaxuq %ymm<br>
+; CHECK: {%k1}<br>
+define <4 x i64>@test_int_x86_avx512_mask_pmaxu_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>
+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>
+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmaxu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i64> %res, %res1<br>
+ ret <4 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsd %xmm<br>
+; CHECK: {%k1}<br>
+define <4 x i32>@test_int_x86_avx512_mask_pmins_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br>
+ %res = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br>
+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pmins.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i32> %res, %res1<br>
+ ret <4 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_d_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsd %ymm<br>
+; CHECK: {%k1}<br>
+define <8 x i32>@test_int_x86_avx512_mask_pmins_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>
+ %res = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>
+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pmins.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>
+ %res2 = add <8 x i32> %res, %res1<br>
+ ret <8 x i32> %res2<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsq %xmm<br>
+; CHECK: {%k1}<br>
+define <2 x i64>@test_int_x86_avx512_mask_pmins_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>
+ %res = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>
+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pmins.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>
+ %res2 = add <2 x i64> %res, %res1<br>
+ ret <2 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pmins_q_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminsq %ymm<br>
+; CHECK: {%k1}<br>
+define <4 x i64>@test_int_x86_avx512_mask_pmins_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>
+ %res = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>
+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pmins.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i64> %res, %res1<br>
+ ret <4 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32>, <4 x i32>, <4 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminud %xmm<br>
+; CHECK: {%k1}<br>
+define <4 x i32>@test_int_x86_avx512_mask_pminu_d_128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask) {<br>
+ %res = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> %x2, i8 %mask)<br>
+ %res1 = call <4 x i32> @llvm.x86.avx512.mask.pminu.d.128(<4 x i32> %x0, <4 x i32> %x1, <4 x i32> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i32> %res, %res1<br>
+ ret <4 x i32> %res2<br>
+}<br>
+<br>
+declare <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32>, <8 x i32>, <8 x i32>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_d_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminud %ymm<br>
+; CHECK: {%k1}<br>
+define <8 x i32>@test_int_x86_avx512_mask_pminu_d_256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3) {<br>
+ %res = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 %x3)<br>
+ %res1 = call <8 x i32> @llvm.x86.avx512.mask.pminu.d.256(<8 x i32> %x0, <8 x i32> %x1, <8 x i32> %x2, i8 -1)<br>
+ %res2 = add <8 x i32> %res, %res1<br>
+ ret <8 x i32> %res2<br>
+}<br>
+<br>
+declare <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64>, <2 x i64>, <2 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_128<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminuq %xmm<br>
+; CHECK: {%k1}<br>
+define <2 x i64>@test_int_x86_avx512_mask_pminu_q_128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3) {<br>
+ %res = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 %x3)<br>
+ %res1 = call <2 x i64> @llvm.x86.avx512.mask.pminu.q.128(<2 x i64> %x0, <2 x i64> %x1, <2 x i64> %x2, i8 -1)<br>
+ %res2 = add <2 x i64> %res, %res1<br>
+ ret <2 x i64> %res2<br>
+}<br>
+<br>
+declare <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64>, <4 x i64>, <4 x i64>, i8)<br>
+<br>
+; CHECK-LABEL: @test_int_x86_avx512_mask_pminu_q_256<br>
+; CHECK-NOT: call<br>
+; CHECK: vpminuq %ymm<br>
+; CHECK: {%k1}<br>
+define <4 x i64>@test_int_x86_avx512_mask_pminu_q_256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask) {<br>
+ %res = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> %x2, i8 %mask)<br>
+ %res1 = call <4 x i64> @llvm.x86.avx512.mask.pminu.q.256(<4 x i64> %x0, <4 x i64> %x1, <4 x i64> zeroinitializer, i8 %mask)<br>
+ %res2 = add <4 x i64> %res, %res1<br>
+ ret <4 x i64> %res2<br>
+}<br>
\ No newline at end of file<br>
<br>
<br>
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