<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Jun 23, 2015 at 9:35 AM, Alex Lorenz <span dir="ltr"><<a href="mailto:arphaman@gmail.com" target="_blank">arphaman@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: arphaman<br>
Date: Tue Jun 23 11:35:26 2015<br>
New Revision: 240425<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D240425-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=8Kvnetft3K9CESGUoY4gL6UDE6FwcTsKdRWzJ8vZ5XI&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=240425&view=rev</a><br>
Log:<br>
MIR Serialization: Serialize physical register machine operands.<br>
<br>
This commit introduces functionality that's used to serialize machine operands.<br>
Only the physical register operands are serialized by this commit.<br>
<br>
Reviewers: Duncan P. N. Exon Smith<br>
<br>
Differential Revision: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__reviews.llvm.org_D10525&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=56qXOglINPAnd13BBDpjP6Cf_grOcYLTXoBg2l43D7E&e=" rel="noreferrer" target="_blank">http://reviews.llvm.org/D10525</a><br>
<br>
Added:<br>
    llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir<br>
    llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir<br>
    llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir<br>
    llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir<br>
Modified:<br>
    llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp<br>
    llvm/trunk/lib/CodeGen/MIRParser/MILexer.h<br>
    llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
    llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_MIRParser_MILexer.cpp-3Frev-3D240425-26r1-3D240424-26r2-3D240425-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=K6M_TSFSq2JuW47Ri2pt77mRhPJx0W7a6MxrDt4o5iQ&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp?rev=240425&r1=240424&r2=240425&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp Tue Jun 23 11:35:26 2015<br>
@@ -68,6 +68,33 @@ static Cursor lexIdentifier(Cursor C, MI<br>
   return C;<br>
 }<br>
<br>
+static Cursor lexPercent(Cursor C, MIToken &Token) {<br>
+  auto Range = C;<br>
+  C.advance(); // Skip '%'<br>
+  while (isIdentifierChar(C.peek()))<br>
+    C.advance();<br>
+  Token = MIToken(MIToken::NamedRegister, Range.upto(C));<br>
+  return C;<br>
+}<br>
+<br>
+static MIToken::TokenKind symbolToken(char C) {<br>
+  switch (C) {<br>
+  case ',':<br>
+    return MIToken::comma;<br>
+  case '=':<br>
+    return MIToken::equal;<br>
+  default:<br>
+    return MIToken::Error;<br>
+  }<br>
+}<br>
+<br>
+static Cursor lexSymbol(Cursor C, MIToken::TokenKind Kind, MIToken &Token) {<br>
+  auto Range = C;<br>
+  C.advance();<br>
+  Token = MIToken(Kind, Range.upto(C));<br>
+  return C;<br>
+}<br>
+<br>
 StringRef llvm::lexMIToken(<br>
     StringRef Source, MIToken &Token,<br>
     function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {<br>
@@ -80,6 +107,11 @@ StringRef llvm::lexMIToken(<br>
   auto Char = C.peek();<br>
   if (isalpha(Char) || Char == '_')<br>
     return lexIdentifier(C, Token).remaining();<br>
+  if (Char == '%')<br>
+    return lexPercent(C, Token).remaining();<br>
+  MIToken::TokenKind Kind = symbolToken(Char);<br>
+  if (Kind != MIToken::Error)<br>
+    return lexSymbol(C, Kind, Token).remaining();<br></blockquote><div><br></div><div>If you end up with many more of these cases of "determining what token kind we need to lex requires work that needs to be shared with the actual lexing of the token", you may want to look into this pattern:</div><div>```</div><div><div>if (... = maybeLexFoo(...))</div><div>  return ...;</div></div><div>if (... = maybeLexBar(...))</div><div>  return ...;</div><div>```</div><div><br></div><div>This helps keep the top-level routine having a highly regular structure. Another advantage is that the maybeLex* functions are then completely self-contained as to what they lex (except for a couple nasty cases; IIRC in VHDL the complicated one I ran into was bit string literals vs numeric literals with explicit base).</div><div><br></div><div>-- Sean Silva</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
   Token = MIToken(MIToken::Error, C.remaining());<br>
   ErrorCallback(C.location(),<br>
                 Twine("unexpected character '") + Twine(Char) + "'");<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_MIRParser_MILexer.h-3Frev-3D240425-26r1-3D240424-26r2-3D240425-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=Lq134barqWHBr1YG8Y7EzPFSDxv_riZSNMt1JzkQ9XE&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MILexer.h?rev=240425&r1=240424&r2=240425&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h Tue Jun 23 11:35:26 2015<br>
@@ -30,8 +30,13 @@ struct MIToken {<br>
     Eof,<br>
     Error,<br>
<br>
+    // Tokens with no info.<br>
+    comma,<br>
+    equal,<br>
+<br>
     // Identifier tokens<br>
-    Identifier<br>
+    Identifier,<br>
+    NamedRegister<br>
   };<br>
<br>
 private:<br>
@@ -45,6 +50,8 @@ public:<br>
<br>
   bool isError() const { return Kind == Error; }<br>
<br>
+  bool isRegister() const { return Kind == NamedRegister; }<br>
+<br>
   bool is(TokenKind K) const { return Kind == K; }<br>
<br>
   bool isNot(TokenKind K) const { return Kind != K; }<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_MIRParser_MIParser.cpp-3Frev-3D240425-26r1-3D240424-26r2-3D240425-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=sX_g5TTN7fR181KWA38DpFHiv6PkFEZxDZ1ByzzyAI4&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp?rev=240425&r1=240424&r2=240425&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp Tue Jun 23 11:35:26 2015<br>
@@ -34,6 +34,8 @@ class MIParser {<br>
   MIToken Token;<br>
   /// Maps from instruction names to op codes.<br>
   StringMap<unsigned> Names2InstrOpCodes;<br>
+  /// Maps from register names to registers.<br>
+  StringMap<unsigned> Names2Regs;<br>
<br>
 public:<br>
   MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,<br>
@@ -53,6 +55,10 @@ public:<br>
<br>
   MachineInstr *parse();<br>
<br>
+  bool parseRegister(unsigned &Reg);<br>
+  bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);<br>
+  bool parseMachineOperand(MachineOperand &Dest);<br>
+<br>
 private:<br>
   void initNames2InstrOpCodes();<br>
<br>
@@ -61,6 +67,12 @@ private:<br>
   bool parseInstrName(StringRef InstrName, unsigned &OpCode);<br>
<br>
   bool parseInstruction(unsigned &OpCode);<br>
+<br>
+  void initNames2Regs();<br>
+<br>
+  /// Try to convert a register name to a register number. Return true if the<br>
+  /// register name is invalid.<br>
+  bool getRegisterByName(StringRef RegName, unsigned &Reg);<br>
 };<br>
<br>
 } // end anonymous namespace<br>
@@ -92,13 +104,60 @@ bool MIParser::error(StringRef::iterator<br>
 MachineInstr *MIParser::parse() {<br>
   lex();<br>
<br>
+  // Parse any register operands before '='<br>
+  // TODO: Allow parsing of multiple operands before '='<br>
+  MachineOperand MO = MachineOperand::CreateImm(0);<br>
+  SmallVector<MachineOperand, 8> Operands;<br>
+  if (Token.isRegister()) {<br>
+    if (parseRegisterOperand(MO, /*IsDef=*/true))<br>
+      return nullptr;<br>
+    Operands.push_back(MO);<br>
+    if (Token.isNot(MIToken::equal)) {<br>
+      error("expected '='");<br>
+      return nullptr;<br>
+    }<br>
+    lex();<br>
+  }<br>
+<br>
   unsigned OpCode;<br>
   if (Token.isError() || parseInstruction(OpCode))<br>
     return nullptr;<br>
<br>
-  // TODO: Parse the rest of instruction - machine operands, etc.<br>
+  // TODO: Parse the instruction flags and memory operands.<br>
+<br>
+  // Parse the remaining machine operands.<br>
+  while (Token.isNot(MIToken::Eof)) {<br>
+    if (parseMachineOperand(MO))<br>
+      return nullptr;<br>
+    Operands.push_back(MO);<br>
+    if (Token.is(MIToken::Eof))<br>
+      break;<br>
+    if (Token.isNot(MIToken::comma)) {<br>
+      error("expected ',' before the next machine operand");<br>
+      return nullptr;<br>
+    }<br>
+    lex();<br>
+  }<br>
+<br>
   const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);<br>
-  auto *MI = MF.CreateMachineInstr(MCID, DebugLoc());<br>
+<br>
+  // Verify machine operands.<br>
+  if (!MCID.isVariadic()) {<br>
+    for (size_t I = 0, E = Operands.size(); I < E; ++I) {<br>
+      if (I < MCID.getNumOperands())<br>
+        continue;<br>
+      // Mark this register as implicit to prevent an assertion when it's added<br>
+      // to an instruction. This is a temporary workaround until the implicit<br>
+      // register flag can be parsed.<br>
+      Operands[I].setImplicit();<br>
+    }<br>
+  }<br>
+<br>
+  // TODO: Determine the implicit behaviour when implicit register flags are<br>
+  // parsed.<br>
+  auto *MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);<br>
+  for (const auto &Operand : Operands)<br>
+    MI->addOperand(MF, Operand);<br>
   return MI;<br>
 }<br>
<br>
@@ -108,6 +167,46 @@ bool MIParser::parseInstruction(unsigned<br>
   StringRef InstrName = Token.stringValue();<br>
   if (parseInstrName(InstrName, OpCode))<br>
     return error(Twine("unknown machine instruction name '") + InstrName + "'");<br>
+  lex();<br>
+  return false;<br>
+}<br>
+<br>
+bool MIParser::parseRegister(unsigned &Reg) {<br>
+  switch (Token.kind()) {<br>
+  case MIToken::NamedRegister: {<br>
+    StringRef Name = Token.stringValue().drop_front(1); // Drop the '%'<br>
+    if (getRegisterByName(Name, Reg))<br>
+      return error(Twine("unknown register name '") + Name + "'");<br>
+    break;<br>
+  }<br>
+  // TODO: Parse other register kinds.<br>
+  default:<br>
+    llvm_unreachable("The current token should be a register");<br>
+  }<br>
+  return false;<br>
+}<br>
+<br>
+bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {<br>
+  unsigned Reg;<br>
+  // TODO: Parse register flags.<br>
+  if (parseRegister(Reg))<br>
+    return true;<br>
+  lex();<br>
+  // TODO: Parse subregister.<br>
+  Dest = MachineOperand::CreateReg(Reg, IsDef);<br>
+  return false;<br>
+}<br>
+<br>
+bool MIParser::parseMachineOperand(MachineOperand &Dest) {<br>
+  switch (Token.kind()) {<br>
+  case MIToken::NamedRegister:<br>
+    return parseRegisterOperand(Dest);<br>
+  case MIToken::Error:<br>
+    return true;<br>
+  default:<br>
+    // TODO: parse the other machine operands.<br>
+    return error("expected a machine operand");<br>
+  }<br>
   return false;<br>
 }<br>
<br>
@@ -129,6 +228,29 @@ bool MIParser::parseInstrName(StringRef<br>
   return false;<br>
 }<br>
<br>
+void MIParser::initNames2Regs() {<br>
+  if (!Names2Regs.empty())<br>
+    return;<br>
+  const auto *TRI = MF.getSubtarget().getRegisterInfo();<br>
+  assert(TRI && "Expected target register info");<br>
+  for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {<br>
+    bool WasInserted =<br>
+        Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))<br>
+            .second;<br>
+    (void)WasInserted;<br>
+    assert(WasInserted && "Expected registers to be unique case-insensitively");<br>
+  }<br>
+}<br>
+<br>
+bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {<br>
+  initNames2Regs();<br>
+  auto RegInfo = Names2Regs.find(RegName);<br>
+  if (RegInfo == Names2Regs.end())<br>
+    return true;<br>
+  Reg = RegInfo->getValue();<br>
+  return false;<br>
+}<br>
+<br>
 MachineInstr *llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF,<br>
                                       StringRef Src, SMDiagnostic &Error) {<br>
   return MIParser(SM, MF, Error, Src).parse();<br>
<br>
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_CodeGen_MIRPrinter.cpp-3Frev-3D240425-26r1-3D240424-26r2-3D240425-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=6PEljvB_5ijZhMrPDEN2ZKZX9MDlU8iZbq_Q5CLCMbo&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=240425&r1=240424&r2=240425&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue Jun 23 11:35:26 2015<br>
@@ -50,6 +50,7 @@ public:<br>
   MIPrinter(raw_ostream &OS) : OS(OS) {}<br>
<br>
   void print(const MachineInstr &MI);<br>
+  void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);<br>
 };<br>
<br>
 } // end anonymous namespace<br>
@@ -110,11 +111,58 @@ void MIRPrinter::convert(yaml::MachineBa<br>
<br>
 void MIPrinter::print(const MachineInstr &MI) {<br>
   const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();<br>
+  const auto *TRI = SubTarget.getRegisterInfo();<br>
+  assert(TRI && "Expected target register info");<br>
   const auto *TII = SubTarget.getInstrInfo();<br>
   assert(TII && "Expected target instruction info");<br>
<br>
+  unsigned I = 0, E = MI.getNumOperands();<br>
+  for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&<br>
+         !MI.getOperand(I).isImplicit();<br>
+       ++I) {<br>
+    if (I)<br>
+      OS << ", ";<br>
+    print(MI.getOperand(I), TRI);<br>
+  }<br>
+<br>
+  if (I)<br>
+    OS << " = ";<br>
   OS << TII->getName(MI.getOpcode());<br>
-  // TODO: Print the instruction flags, machine operands, machine mem operands.<br>
+  // TODO: Print the instruction flags, machine mem operands.<br>
+  if (I < E)<br>
+    OS << ' ';<br>
+<br>
+  bool NeedComma = false;<br>
+  for (; I < E; ++I) {<br>
+    if (NeedComma)<br>
+      OS << ", ";<br>
+    print(MI.getOperand(I), TRI);<br>
+    NeedComma = true;<br>
+  }<br>
+}<br>
+<br>
+static void printReg(unsigned Reg, raw_ostream &OS,<br>
+                     const TargetRegisterInfo *TRI) {<br>
+  // TODO: Print Stack Slots.<br>
+  // TODO: Print no register.<br>
+  // TODO: Print virtual registers.<br>
+  if (Reg < TRI->getNumRegs())<br>
+    OS << '%' << StringRef(TRI->getName(Reg)).lower();<br>
+  else<br>
+    llvm_unreachable("Can't print this kind of register yet");<br>
+}<br>
+<br>
+void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {<br>
+  switch (Op.getType()) {<br>
+  case MachineOperand::MO_Register:<br>
+    // TODO: Print register flags.<br>
+    printReg(Op.getReg(), OS, TRI);<br>
+    // TODO: Print sub register.<br>
+    break;<br>
+  default:<br>
+    // TODO: Print the other machine operands.<br>
+    llvm_unreachable("Can't print this machine operand at the moment");<br>
+  }<br>
 }<br>
<br>
 void llvm::printMIR(raw_ostream &OS, const Module &M) {<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_MIR_X86_expected-2Dmachine-2Doperand.mir-3Frev-3D240425-26view-3Dauto&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=nGmUeA7jCP6prOpNP0XCiJyA4M3I8alxkRKe5tYuM-4&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir?rev=240425&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-machine-operand.mir Tue Jun 23 11:35:26 2015<br>
@@ -0,0 +1,20 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+  define i32 @foo() {<br>
+  entry:<br>
+    ret i32 0<br>
+  }<br>
+<br>
+...<br>
+---<br>
+name:            foo<br>
+body:<br>
+ - name:         entry<br>
+   instructions:<br>
+     # CHECK: 1:16: expected a machine operand<br>
+     - '%eax = XOR32rr ='<br>
+     - 'RETQ %eax'<br>
+...<br>
+<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_MIR_X86_missing-2Dcomma.mir-3Frev-3D240425-26view-3Dauto&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=fubaemLEkTz3XQ8Dca791S_AwCPXCtusXrtG4nXLHm8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir?rev=240425&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/missing-comma.mir Tue Jun 23 11:35:26 2015<br>
@@ -0,0 +1,20 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+<br>
+--- |<br>
+<br>
+  define i32 @foo() {<br>
+  entry:<br>
+    ret i32 0<br>
+  }<br>
+<br>
+...<br>
+---<br>
+name:            foo<br>
+body:<br>
+ - name:         entry<br>
+   instructions:<br>
+     # CHECK: 1:21: expected ',' before the next machine operand<br>
+     - '%eax = XOR32rr %eax %eflags'<br>
+     - 'RETQ %eax'<br>
+...<br>
+<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_MIR_X86_named-2Dregisters.mir-3Frev-3D240425-26view-3Dauto&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=gcFVCZYS3ZYSh-gH-dAUJIsm6KVwU2DbilLhfSpKy1E&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir?rev=240425&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/named-registers.mir Tue Jun 23 11:35:26 2015<br>
@@ -0,0 +1,22 @@<br>
+# RUN: llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s | FileCheck %s<br>
+# This test ensures that the MIR parser parses X86 registers correctly.<br>
+<br>
+--- |<br>
+<br>
+  define i32 @foo() {<br>
+  entry:<br>
+    ret i32 0<br>
+  }<br>
+<br>
+...<br>
+---<br>
+# CHECK: name: foo<br>
+name:            foo<br>
+body:<br>
+ - name:         entry<br>
+   instructions:<br>
+     # CHECK:      - '%eax = MOV32r0<br>
+     # CHECK-NEXT: - 'RETQ %eax<br>
+     - '%eax = MOV32r0'<br>
+     - 'RETQ %eax'<br>
+...<br>
<br>
Added: llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_MIR_X86_unknown-2Dregister.mir-3Frev-3D240425-26view-3Dauto&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=8dTm3vgGSBQFGQ2stfymr6MMlQF90Xdvydbtvx_r7bU&s=onZ0CmhbUp13OIssg61DCH8XKKL6ag6qw4OKVLDMZc8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir?rev=240425&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir (added)<br>
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-register.mir Tue Jun 23 11:35:26 2015<br>
@@ -0,0 +1,21 @@<br>
+# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s<br>
+# This test ensures that an error is reported when an unknown register is<br>
+# encountered.<br>
+<br>
+--- |<br>
+<br>
+  define i32 @foo() {<br>
+  entry:<br>
+    ret i32 0<br>
+  }<br>
+<br>
+...<br>
+---<br>
+name:            foo<br>
+body:<br>
+ - name:         entry<br>
+   instructions:<br>
+     # CHECK: 1:1: unknown register name 'xax'<br>
+     - '%xax = MOV32r0'<br>
+     - 'RETQ %xax'<br>
+...<br>
<br>
<br>
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</blockquote></div><br></div></div>