<div dir="ltr">I think I agree, but I'd like to find a way to do this without duplicating the instructions again. Maybe we can keep the register encodings unmodified instead of calling <span style="font-size:12.8000001907349px">getGR32FromGR64, then detect whether we need REX.W in the encoder? May need a new TSFlag to enable this behavior.</span></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Jun 22, 2015 at 5:40 PM, Ahmed Bougacha <span dir="ltr"><<a href="mailto:ahmed.bougacha@gmail.com" target="_blank">ahmed.bougacha@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Craig,<br>
<br>
Forgive the necromancy, but I'm wondering if this is the right thing:<br>
we remove users' freedom to pick encodings (used by some, for padding<br>
and such), for no good reason: with this commit, generated code uses<br>
GR32 encodings, even if the assembly explicitly specified a GR64<br>
register.<br>
<br>
Of course, that's starting from assembly; if the compiler generates<br>
the larger equivalent encoding that should be fixed, but I don't think<br>
that's ever the case, as AFAICT GR32 is preferred by the various<br>
patterns.<br>
<br>
What do you think about restoring the previous behavior?<br>
-Ahmed<br>
<br>
<br>
On Sun, Oct 13, 2013 at 9:55 PM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:<br>
> Author: ctopper<br>
> Date: Sun Oct 13 23:55:01 2013<br>
> New Revision: 192567<br>
><br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D192567-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=r0KnUjpLksDT0Tg3tPg2w4Ip3ooubN3xL6oU6gFyULw&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=192567&view=rev</a><br>
> Log:<br>
> Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
> llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
> llvm/trunk/lib/Target/X86/X86InstrMMX.td<br>
> llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
> llvm/trunk/test/MC/X86/x86-64.s<br>
> llvm/trunk/test/MC/X86/x86_64-avx-encoding.s<br>
> llvm/trunk/test/MC/X86/x86_64-encoding.s<br>
> llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_AsmParser_X86AsmParser.cpp-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=dQKnKxKnlqdvhStrGeE8CIuTvaAiz_cSCIAvoN1QDZk&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp Sun Oct 13 23:55:01 2013<br>
> @@ -869,6 +869,12 @@ struct X86Operand : public MCParsedAsmOp<br>
><br>
> bool isReg() const { return Kind == Register; }<br>
><br>
> + bool isGR32orGR64() const {<br>
> + return Kind == Register &&<br>
> + (X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||<br>
> + X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));<br>
> + }<br>
> +<br>
> void addExpr(MCInst &Inst, const MCExpr *Expr) const {<br>
> // Add as immediates when possible.<br>
> if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))<br>
> @@ -882,6 +888,37 @@ struct X86Operand : public MCParsedAsmOp<br>
> Inst.addOperand(MCOperand::CreateReg(getReg()));<br>
> }<br>
><br>
> + static unsigned getGR32FromGR64(unsigned RegNo) {<br>
> + switch (RegNo) {<br>
> + default: llvm_unreachable("Unexpected register");<br>
> + case X86::RAX: return X86::EAX;<br>
> + case X86::RCX: return X86::ECX;<br>
> + case X86::RDX: return X86::EDX;<br>
> + case X86::RBX: return X86::EBX;<br>
> + case X86::RBP: return X86::EBP;<br>
> + case X86::RSP: return X86::ESP;<br>
> + case X86::RSI: return X86::ESI;<br>
> + case X86::RDI: return X86::EDI;<br>
> + case X86::R8: return X86::R8D;<br>
> + case X86::R9: return X86::R9D;<br>
> + case X86::R10: return X86::R10D;<br>
> + case X86::R11: return X86::R11D;<br>
> + case X86::R12: return X86::R12D;<br>
> + case X86::R13: return X86::R13D;<br>
> + case X86::R14: return X86::R14D;<br>
> + case X86::R15: return X86::R15D;<br>
> + case X86::RIP: return X86::EIP;<br>
> + }<br>
> + }<br>
> +<br>
> + void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {<br>
> + assert(N == 1 && "Invalid number of operands!");<br>
> + unsigned RegNo = getReg();<br>
> + if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))<br>
> + RegNo = getGR32FromGR64(RegNo);<br>
> + Inst.addOperand(MCOperand::CreateReg(RegNo));<br>
> + }<br>
> +<br>
> void addImmOperands(MCInst &Inst, unsigned N) const {<br>
> assert(N == 1 && "Invalid number of operands!");<br>
> addExpr(Inst, getImm());<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrInfo.td-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=6mzC1MiuRitYod3pWNMclaY9c8vhzZNBJ6-elBKxv2k&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun Oct 13 23:55:01 2013<br>
> @@ -502,6 +502,14 @@ class ImmZExtAsmOperandClass : AsmOperan<br>
> let RenderMethod = "addImmOperands";<br>
> }<br>
><br>
> +def X86GR32orGR64AsmOperand : AsmOperandClass {<br>
> + let Name = "GR32orGR64";<br>
> +}<br>
> +<br>
> +def GR32orGR64 : RegisterOperand<GR32> {<br>
> + let ParserMatchClass = X86GR32orGR64AsmOperand;<br>
> +}<br>
> +<br>
> // Sign-extended immediate classes. We don't need to define the full lattice<br>
> // here because there is no instruction with an ambiguity between ImmSExti64i32<br>
> // and ImmSExti32i8.<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrMMX.td-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=-BEWJ44cySYs_6Rny-QYzNTe59lvCiQGq0cpzJmYpbY&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Sun Oct 13 23:55:01 2013<br>
> @@ -546,18 +546,18 @@ let Constraints = "$src1 = $dst" in {<br>
><br>
> // Extract / Insert<br>
> def MMX_PEXTRWirri: MMXIi8<0xC5, MRMSrcReg,<br>
> - (outs GR32:$dst), (ins VR64:$src1, i32i8imm:$src2),<br>
> - "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
> - [(set GR32:$dst, (int_x86_mmx_pextr_w VR64:$src1,<br>
> - (iPTR imm:$src2)))],<br>
> - IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;<br>
> + (outs GR32orGR64:$dst), (ins VR64:$src1, i32i8imm:$src2),<br>
> + "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
> + [(set GR32orGR64:$dst, (int_x86_mmx_pextr_w VR64:$src1,<br>
> + (iPTR imm:$src2)))],<br>
> + IIC_MMX_PEXTR>, Sched<[WriteShuffle]>;<br>
> let Constraints = "$src1 = $dst" in {<br>
> def MMX_PINSRWirri : MMXIi8<0xC4, MRMSrcReg,<br>
> (outs VR64:$dst),<br>
> - (ins VR64:$src1, GR32:$src2, i32i8imm:$src3),<br>
> + (ins VR64:$src1, GR32orGR64:$src2, i32i8imm:$src3),<br>
> "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
> [(set VR64:$dst, (int_x86_mmx_pinsr_w VR64:$src1,<br>
> - GR32:$src2, (iPTR imm:$src3)))],<br>
> + GR32orGR64:$src2, (iPTR imm:$src3)))],<br>
> IIC_MMX_PINSRW>, Sched<[WriteShuffle]>;<br>
><br>
> def MMX_PINSRWirmi : MMXIi8<0xC4, MRMSrcMem,<br>
> @@ -571,9 +571,10 @@ let Constraints = "$src1 = $dst" in {<br>
> }<br>
><br>
> // Mask creation<br>
> -def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR64:$src),<br>
> +def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),<br>
> + (ins VR64:$src),<br>
> "pmovmskb\t{$src, $dst|$dst, $src}",<br>
> - [(set GR32:$dst,<br>
> + [(set GR32orGR64:$dst,<br>
> (int_x86_mmx_pmovmskb VR64:$src))]>;<br>
><br>
><br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86InstrSSE.td-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=cln6UnvpNeN_vcmM5fjJLXAPkGJmbKc4WpgMKS9-xlE&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Oct 13 23:55:01 2013<br>
> @@ -2706,14 +2706,10 @@ let Predicates = [UseSSE2] in {<br>
> /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave<br>
> multiclass sse12_extr_sign_mask<RegisterClass RC, Intrinsic Int, string asm,<br>
> Domain d> {<br>
> - def rr32 : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins RC:$src),<br>
> - !strconcat(asm, "\t{$src, $dst|$dst, $src}"),<br>
> - [(set GR32:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,<br>
> - Sched<[WriteVecLogic]>;<br>
> - let isAsmParserOnly = 1, hasSideEffects = 0 in<br>
> - def rr64 : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins RC:$src),<br>
> - !strconcat(asm, "\t{$src, $dst|$dst, $src}"), [],<br>
> - IIC_SSE_MOVMSK, d>, REX_W, Sched<[WriteVecLogic]>;<br>
> + def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),<br>
> + !strconcat(asm, "\t{$src, $dst|$dst, $src}"),<br>
> + [(set GR32orGR64:$dst, (Int RC:$src))], IIC_SSE_MOVMSK, d>,<br>
> + Sched<[WriteVecLogic]>;<br>
> }<br>
><br>
> let Predicates = [HasAVX] in {<br>
> @@ -2730,15 +2726,15 @@ let Predicates = [HasAVX] in {<br>
> OpSize, VEX, VEX_L;<br>
><br>
> def : Pat<(i32 (X86fgetsign FR32:$src)),<br>
> - (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>;<br>
> + (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>;<br>
> def : Pat<(i64 (X86fgetsign FR32:$src)),<br>
> (SUBREG_TO_REG (i64 0),<br>
> - (VMOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;<br>
> + (VMOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>;<br>
> def : Pat<(i32 (X86fgetsign FR64:$src)),<br>
> - (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>;<br>
> + (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>;<br>
> def : Pat<(i64 (X86fgetsign FR64:$src)),<br>
> (SUBREG_TO_REG (i64 0),<br>
> - (VMOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;<br>
> + (VMOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>;<br>
> }<br>
><br>
> defm MOVMSKPS : sse12_extr_sign_mask<VR128, int_x86_sse_movmsk_ps, "movmskps",<br>
> @@ -2747,18 +2743,18 @@ defm MOVMSKPD : sse12_extr_sign_mask<VR1<br>
> SSEPackedDouble>, TB, OpSize;<br>
><br>
> def : Pat<(i32 (X86fgetsign FR32:$src)),<br>
> - (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128))>,<br>
> + (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128))>,<br>
> Requires<[UseSSE1]>;<br>
> def : Pat<(i64 (X86fgetsign FR32:$src)),<br>
> (SUBREG_TO_REG (i64 0),<br>
> - (MOVMSKPSrr32 (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,<br>
> + (MOVMSKPSrr (COPY_TO_REGCLASS FR32:$src, VR128)), sub_32bit)>,<br>
> Requires<[UseSSE1]>;<br>
> def : Pat<(i32 (X86fgetsign FR64:$src)),<br>
> - (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128))>,<br>
> + (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128))>,<br>
> Requires<[UseSSE2]>;<br>
> def : Pat<(i64 (X86fgetsign FR64:$src)),<br>
> (SUBREG_TO_REG (i64 0),<br>
> - (MOVMSKPDrr32 (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,<br>
> + (MOVMSKPDrr (COPY_TO_REGCLASS FR64:$src, VR128)), sub_32bit)>,<br>
> Requires<[UseSSE2]>;<br>
><br>
> //===---------------------------------------------------------------------===//<br>
> @@ -4248,13 +4244,13 @@ let ExeDomain = SSEPackedInt in {<br>
> multiclass sse2_pinsrw<bit Is2Addr = 1> {<br>
> def rri : Ii8<0xC4, MRMSrcReg,<br>
> (outs VR128:$dst), (ins VR128:$src1,<br>
> - GR32:$src2, i32i8imm:$src3),<br>
> + GR32orGR64:$src2, i32i8imm:$src3),<br>
> !if(Is2Addr,<br>
> "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
> "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),<br>
> [(set VR128:$dst,<br>
> - (X86pinsrw VR128:$src1, GR32:$src2, imm:$src3))], IIC_SSE_PINSRW>,<br>
> - Sched<[WriteShuffle]>;<br>
> + (X86pinsrw VR128:$src1, GR32orGR64:$src2, imm:$src3))],<br>
> + IIC_SSE_PINSRW>, Sched<[WriteShuffle]>;<br>
> def rmi : Ii8<0xC4, MRMSrcMem,<br>
> (outs VR128:$dst), (ins VR128:$src1,<br>
> i16mem:$src2, i32i8imm:$src3),<br>
> @@ -4270,36 +4266,24 @@ multiclass sse2_pinsrw<bit Is2Addr = 1><br>
> // Extract<br>
> let Predicates = [HasAVX] in<br>
> def VPEXTRWri : Ii8<0xC5, MRMSrcReg,<br>
> - (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),<br>
> + (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),<br>
> "vpextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
> - [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),<br>
> - imm:$src2))]>, TB, OpSize, VEX,<br>
> + [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),<br>
> + imm:$src2))]>, TB, OpSize, VEX,<br>
> Sched<[WriteShuffle]>;<br>
> def PEXTRWri : PDIi8<0xC5, MRMSrcReg,<br>
> - (outs GR32:$dst), (ins VR128:$src1, i32i8imm:$src2),<br>
> + (outs GR32orGR64:$dst), (ins VR128:$src1, i32i8imm:$src2),<br>
> "pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
> - [(set GR32:$dst, (X86pextrw (v8i16 VR128:$src1),<br>
> - imm:$src2))], IIC_SSE_PEXTRW>,<br>
> + [(set GR32orGR64:$dst, (X86pextrw (v8i16 VR128:$src1),<br>
> + imm:$src2))], IIC_SSE_PEXTRW>,<br>
> Sched<[WriteShuffleLd, ReadAfterLd]>;<br>
><br>
> // Insert<br>
> -let Predicates = [HasAVX] in {<br>
> - defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;<br>
> - let isAsmParserOnly = 1, hasSideEffects = 0 in<br>
> - def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),<br>
> - (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),<br>
> - "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",<br>
> - []>, TB, OpSize, VEX_4V, Sched<[WriteShuffle]>;<br>
> -}<br>
> -<br>
> -let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in {<br>
> - defm PINSRW : sse2_pinsrw, TB, OpSize;<br>
> - let isAsmParserOnly = 1, hasSideEffects = 0 in<br>
> - def PINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst),<br>
> - (ins VR128:$src1, GR64:$src2, i32i8imm:$src3),<br>
> - "pinsrw\t{$src3, $src2, $dst|$dst, $src2, $src3}",<br>
> - []>, TB, OpSize, Sched<[WriteShuffle]>;<br>
> -} // Predicates = [UseSSE2], Constraints = "$src1 = $dst"<br>
> +let Predicates = [HasAVX] in<br>
> +defm VPINSRW : sse2_pinsrw<0>, TB, OpSize, VEX_4V;<br>
> +<br>
> +let Predicates = [UseSSE2], Constraints = "$src1 = $dst" in<br>
> +defm PINSRW : sse2_pinsrw, TB, OpSize;<br>
><br>
> } // ExeDomain = SSEPackedInt<br>
><br>
> @@ -4309,27 +4293,24 @@ let Predicates = [UseSSE2], Constraints<br>
><br>
> let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {<br>
><br>
> -def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),<br>
> +def VPMOVMSKBrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),<br>
> + (ins VR128:$src),<br>
> "pmovmskb\t{$src, $dst|$dst, $src}",<br>
> - [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],<br>
> + [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],<br>
> IIC_SSE_MOVMSK>, VEX;<br>
> -def VPMOVMSKBr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),<br>
> - "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>, VEX;<br>
><br>
> let Predicates = [HasAVX2] in {<br>
> -def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR256:$src),<br>
> +def VPMOVMSKBYrr : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),<br>
> + (ins VR256:$src),<br>
> "pmovmskb\t{$src, $dst|$dst, $src}",<br>
> - [(set GR32:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>, VEX, VEX_L;<br>
> -def VPMOVMSKBYr64r : VPDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR256:$src),<br>
> - "pmovmskb\t{$src, $dst|$dst, $src}", []>, VEX, VEX_L;<br>
> + [(set GR32orGR64:$dst, (int_x86_avx2_pmovmskb VR256:$src))]>,<br>
> + VEX, VEX_L;<br>
> }<br>
><br>
> -def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),<br>
> +def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),<br>
> "pmovmskb\t{$src, $dst|$dst, $src}",<br>
> - [(set GR32:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],<br>
> + [(set GR32orGR64:$dst, (int_x86_sse2_pmovmskb_128 VR128:$src))],<br>
> IIC_SSE_MOVMSK>;<br>
> -def PMOVMSKBr64r : PDI<0xD7, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src),<br>
> - "pmovmskb\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVMSK>;<br>
><br>
> } // ExeDomain = SSEPackedInt<br>
><br>
> @@ -6024,29 +6005,26 @@ let Predicates = [UseSSE41] in {<br>
><br>
> /// SS41I_binop_ext8 - SSE 4.1 extract 8 bits to 32 bit reg or 8 bit mem<br>
> multiclass SS41I_extract8<bits<8> opc, string OpcodeStr> {<br>
> - def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),<br>
> + def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),<br>
> (ins VR128:$src1, i32i8imm:$src2),<br>
> !strconcat(OpcodeStr,<br>
> - "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> - [(set GR32:$dst, (X86pextrb (v16i8 VR128:$src1), imm:$src2))]>,<br>
> + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + [(set GR32orGR64:$dst, (X86pextrb (v16i8 VR128:$src1),<br>
> + imm:$src2))]>,<br>
> OpSize;<br>
> let neverHasSideEffects = 1, mayStore = 1 in<br>
> def mr : SS4AIi8<opc, MRMDestMem, (outs),<br>
> (ins i8mem:$dst, VR128:$src1, i32i8imm:$src2),<br>
> !strconcat(OpcodeStr,<br>
> - "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> []>, OpSize;<br>
> // FIXME:<br>
> // There's an AssertZext in the way of writing the store pattern<br>
> // (store (i8 (trunc (X86pextrb (v16i8 VR128:$src1), imm:$src2))), addr:$dst)<br>
> }<br>
><br>
> -let Predicates = [HasAVX] in {<br>
> +let Predicates = [HasAVX] in<br>
> defm VPEXTRB : SS41I_extract8<0x14, "vpextrb">, VEX;<br>
> - def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),<br>
> - (ins VR128:$src1, i32i8imm:$src2),<br>
> - "vpextrb\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, OpSize, VEX;<br>
> -}<br>
><br>
> defm PEXTRB : SS41I_extract8<0x14, "pextrb">;<br>
><br>
> @@ -6054,7 +6032,7 @@ defm PEXTRB : SS41I_extract8<0x14,<br>
> /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination<br>
> multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> {<br>
> let isCodeGenOnly = 1, hasSideEffects = 0 in<br>
> - def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),<br>
> + def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),<br>
> (ins VR128:$src1, i32i8imm:$src2),<br>
> !strconcat(OpcodeStr,<br>
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> @@ -6123,11 +6101,11 @@ defm PEXTRQ : SS41I_extract64<0x16,<br>
> /// destination<br>
> multiclass SS41I_extractf32<bits<8> opc, string OpcodeStr,<br>
> OpndItins itins = DEFAULT_ITINS> {<br>
> - def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),<br>
> + def rr : SS4AIi8<opc, MRMDestReg, (outs GR32orGR64:$dst),<br>
> (ins VR128:$src1, i32i8imm:$src2),<br>
> !strconcat(OpcodeStr,<br>
> "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
> - [(set GR32:$dst,<br>
> + [(set GR32orGR64:$dst,<br>
> (extractelt (bc_v4i32 (v4f32 VR128:$src1)), imm:$src2))],<br>
> itins.rr>,<br>
> OpSize;<br>
> @@ -6140,13 +6118,8 @@ multiclass SS41I_extractf32<bits<8> opc,<br>
> }<br>
><br>
> let ExeDomain = SSEPackedSingle in {<br>
> - let Predicates = [UseAVX] in {<br>
> + let Predicates = [UseAVX] in<br>
> defm VEXTRACTPS : SS41I_extractf32<0x17, "vextractps">, VEX;<br>
> - def VEXTRACTPSrr64 : SS4AIi8<0x17, MRMDestReg, (outs GR64:$dst),<br>
> - (ins VR128:$src1, i32i8imm:$src2),<br>
> - "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",<br>
> - []>, OpSize, VEX;<br>
> - }<br>
> defm EXTRACTPS : SS41I_extractf32<0x17, "extractps", SSE_EXTRACT_ITINS>;<br>
> }<br>
><br>
> @@ -6168,13 +6141,13 @@ def : Pat<(store (f32 (bitconvert (extra<br>
><br>
> multiclass SS41I_insert8<bits<8> opc, string asm, bit Is2Addr = 1> {<br>
> def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),<br>
> - (ins VR128:$src1, GR32:$src2, i32i8imm:$src3),<br>
> + (ins VR128:$src1, GR32orGR64:$src2, i32i8imm:$src3),<br>
> !if(Is2Addr,<br>
> !strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),<br>
> !strconcat(asm,<br>
> "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),<br>
> [(set VR128:$dst,<br>
> - (X86pinsrb VR128:$src1, GR32:$src2, imm:$src3))]>, OpSize;<br>
> + (X86pinsrb VR128:$src1, GR32orGR64:$src2, imm:$src3))]>, OpSize;<br>
> def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),<br>
> (ins VR128:$src1, i8mem:$src2, i32i8imm:$src3),<br>
> !if(Is2Addr,<br>
><br>
> Modified: llvm/trunk/test/MC/X86/x86-64.s<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_MC_X86_x86-2D64.s-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=SltdEYlesPnihKpOor_HcSW1tM7IQnCLSUOsgBWwnwM&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/X86/x86-64.s (original)<br>
> +++ llvm/trunk/test/MC/X86/x86-64.s Sun Oct 13 23:55:01 2013<br>
> @@ -549,8 +549,8 @@ cvttpd2dq 0xdeadbeef(%ebx,%ecx,8),%xmm5<br>
><br>
> // rdar://8490728 - llvm-mc rejects 'movmskpd'<br>
> movmskpd %xmm6, %rax<br>
> -// CHECK: movmskpd %xmm6, %rax<br>
> -// CHECK: encoding: [0x66,0x48,0x0f,0x50,0xc6]<br>
> +// CHECK: movmskpd %xmm6, %eax<br>
> +// CHECK: encoding: [0x66,0x0f,0x50,0xc6]<br>
> movmskpd %xmm6, %eax<br>
> // CHECK: movmskpd %xmm6, %eax<br>
> // CHECK: encoding: [0x66,0x0f,0x50,0xc6]<br>
><br>
> Modified: llvm/trunk/test/MC/X86/x86_64-avx-encoding.s<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_MC_X86_x86-5F64-2Davx-2Dencoding.s-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=IAvczJZUcO4s6rKHQ388E28reqGiTksqhfRbrD-gnyw&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-avx-encoding.s?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/X86/x86_64-avx-encoding.s (original)<br>
> +++ llvm/trunk/test/MC/X86/x86_64-avx-encoding.s Sun Oct 13 23:55:01 2013<br>
> @@ -4044,7 +4044,7 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11<br>
> // CHECK: encoding: [0xc4,0x43,0x79,0x17,0xc0,0x0a]<br>
> vextractps $10, %xmm8, %r8<br>
><br>
> -// CHECK: vextractps $7, %xmm4, %rcx<br>
> +// CHECK: vextractps $7, %xmm4, %ecx<br>
> // CHECK: encoding: [0xc4,0xe3,0x79,0x17,0xe1,0x07]<br>
> vextractps $7, %xmm4, %rcx<br>
><br>
> @@ -4052,35 +4052,35 @@ vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11<br>
> // CHECK: encoding: [0xc4,0xe1,0xf9,0x7e,0xe1]<br>
> vmovd %xmm4, %rcx<br>
><br>
> -// CHECK: vmovmskpd %xmm4, %rcx<br>
> +// CHECK: vmovmskpd %xmm4, %ecx<br>
> // CHECK: encoding: [0xc5,0xf9,0x50,0xcc]<br>
> vmovmskpd %xmm4, %rcx<br>
><br>
> -// CHECK: vmovmskpd %ymm4, %rcx<br>
> +// CHECK: vmovmskpd %ymm4, %ecx<br>
> // CHECK: encoding: [0xc5,0xfd,0x50,0xcc]<br>
> vmovmskpd %ymm4, %rcx<br>
><br>
> -// CHECK: vmovmskps %xmm4, %rcx<br>
> +// CHECK: vmovmskps %xmm4, %ecx<br>
> // CHECK: encoding: [0xc5,0xf8,0x50,0xcc]<br>
> vmovmskps %xmm4, %rcx<br>
><br>
> -// CHECK: vmovmskps %ymm4, %rcx<br>
> +// CHECK: vmovmskps %ymm4, %ecx<br>
> // CHECK: encoding: [0xc5,0xfc,0x50,0xcc]<br>
> vmovmskps %ymm4, %rcx<br>
><br>
> -// CHECK: vpextrb $7, %xmm4, %rcx<br>
> +// CHECK: vpextrb $7, %xmm4, %ecx<br>
> // CHECK: encoding: [0xc4,0xe3,0x79,0x14,0xe1,0x07]<br>
> vpextrb $7, %xmm4, %rcx<br>
><br>
> -// CHECK: vpinsrw $7, %r8, %xmm15, %xmm8<br>
> +// CHECK: vpinsrw $7, %r8d, %xmm15, %xmm8<br>
> // CHECK: encoding: [0xc4,0x41,0x01,0xc4,0xc0,0x07]<br>
> vpinsrw $7, %r8, %xmm15, %xmm8<br>
><br>
> -// CHECK: vpinsrw $7, %rcx, %xmm4, %xmm6<br>
> +// CHECK: vpinsrw $7, %ecx, %xmm4, %xmm6<br>
> // CHECK: encoding: [0xc5,0xd9,0xc4,0xf1,0x07]<br>
> vpinsrw $7, %rcx, %xmm4, %xmm6<br>
><br>
> -// CHECK: vpmovmskb %xmm4, %rcx<br>
> +// CHECK: vpmovmskb %xmm4, %ecx<br>
> // CHECK: encoding: [0xc5,0xf9,0xd7,0xcc]<br>
> vpmovmskb %xmm4, %rcx<br>
><br>
><br>
> Modified: llvm/trunk/test/MC/X86/x86_64-encoding.s<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_MC_X86_x86-5F64-2Dencoding.s-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=6n2R8nR-hjHhyQ5b9symzpKq3pGx4RGaXaxQ6-jAjck&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-encoding.s?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/X86/x86_64-encoding.s (original)<br>
> +++ llvm/trunk/test/MC/X86/x86_64-encoding.s Sun Oct 13 23:55:01 2013<br>
> @@ -232,7 +232,7 @@ sha256msg2 (%rax), %xmm2<br>
> // CHECK: encoding: [0xdf,0x07]<br>
> filds (%rdi)<br>
><br>
> -// CHECK: pmovmskb %xmm5, %rcx<br>
> +// CHECK: pmovmskb %xmm5, %ecx<br>
> // CHECK: encoding: [0x66,0x0f,0xd7,0xcd]<br>
> pmovmskb %xmm5,%rcx<br>
><br>
> @@ -240,6 +240,6 @@ sha256msg2 (%rax), %xmm2<br>
> // CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]<br>
> pinsrw $3, %ecx, %xmm5<br>
><br>
> -// CHECK: pinsrw $3, %rcx, %xmm5<br>
> +// CHECK: pinsrw $3, %ecx, %xmm5<br>
> // CHECK: encoding: [0x66,0x0f,0xc4,0xe9,0x03]<br>
> pinsrw $3, %rcx, %xmm5<br>
><br>
> Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp<br>
> URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_utils_TableGen_X86RecognizableInstr.cpp-3Frev-3D192567-26r1-3D192566-26r2-3D192567-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=pCMunp4jAnepBG-ftdhlRyMQ5IF5x4H3v67nSMoTlHk&s=j4vPIeLDssO9fe3NYmvfpGooDSZOdmJzPVtZPw06sOk&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=192567&r1=192566&r2=192567&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)<br>
> +++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Sun Oct 13 23:55:01 2013<br>
> @@ -1213,6 +1213,7 @@ OperandType RecognizableInstr::typeFromS<br>
> TYPE("i32i8imm", TYPE_IMM32)<br>
> TYPE("u32u8imm", TYPE_IMM32)<br>
> TYPE("GR32", TYPE_Rv)<br>
> + TYPE("GR32orGR64", TYPE_R32)<br>
> TYPE("i64mem", TYPE_Mv)<br>
> TYPE("i64i32imm", TYPE_IMM64)<br>
> TYPE("i64i8imm", TYPE_IMM64)<br>
> @@ -1323,6 +1324,7 @@ OperandEncoding RecognizableInstr::rmReg<br>
> bool hasOpSizePrefix) {<br>
> ENCODING("GR16", ENCODING_RM)<br>
> ENCODING("GR32", ENCODING_RM)<br>
> + ENCODING("GR32orGR64", ENCODING_RM)<br>
> ENCODING("GR64", ENCODING_RM)<br>
> ENCODING("GR8", ENCODING_RM)<br>
> ENCODING("VR128", ENCODING_RM)<br>
> @@ -1346,6 +1348,7 @@ OperandEncoding RecognizableInstr::roReg<br>
> bool hasOpSizePrefix) {<br>
> ENCODING("GR16", ENCODING_REG)<br>
> ENCODING("GR32", ENCODING_REG)<br>
> + ENCODING("GR32orGR64", ENCODING_REG)<br>
> ENCODING("GR64", ENCODING_REG)<br>
> ENCODING("GR8", ENCODING_REG)<br>
> ENCODING("VR128", ENCODING_REG)<br>
><br>
><br>
> _______________________________________________<br>
> llvm-commits mailing list<br>
> <a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
> <a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>