<div dir="ltr">Oh hey, thanks!<div><br></div><div>Also thanks for all of the cleanups, the code looks much nicer.</div><div><br></div><div>-eric</div></div><br><div class="gmail_quote"><div dir="ltr">On Thu, Jun 18, 2015 at 1:38 PM Reid Kleckner <<a href="mailto:reid@kleckner.net">reid@kleckner.net</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rnk<br>
Date: Thu Jun 18 15:32:02 2015<br>
New Revision: 240047<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D240047-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=x5JabzHKiDFs3t-o5pPsfSmlgFW-jSpC5_1BiyJP_aU&s=hvzTx9nU_vC97crUHNJLvXGilNhoaBerrC4rSmyvgGI&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project?rev=240047&view=rev</a><br>
Log:<br>
[X86] Rename RegInfo to TRI as suggested by Eric<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86FrameLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86FrameLowering.h<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86FrameLowering.cpp-3Frev-3D240047-26r1-3D240046-26r2-3D240047-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=x5JabzHKiDFs3t-o5pPsfSmlgFW-jSpC5_1BiyJP_aU&s=BVBW4C5jgcoN_GlEW9VcdEQ4RqsrE3Tx7An3XzmMcC8&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=240047&r1=240046&r2=240047&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Thu Jun 18 15:32:02 2015<br>
@@ -41,14 +41,14 @@ X86FrameLowering::X86FrameLowering(const<br>
unsigned StackAlignOverride)<br>
: TargetFrameLowering(StackGrowsDown, StackAlignOverride,<br>
STI.is64Bit() ? -8 : -4),<br>
- STI(STI), TII(*STI.getInstrInfo()), RegInfo(STI.getRegisterInfo()) {<br>
+ STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {<br>
// Cache a bunch of frame-related predicates for this subtarget.<br>
- SlotSize = RegInfo->getSlotSize();<br>
+ SlotSize = TRI->getSlotSize();<br>
Is64Bit = STI.is64Bit();<br>
IsLP64 = STI.isTarget64BitLP64();<br>
// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.<br>
Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64();<br>
- StackPtr = RegInfo->getStackRegister();<br>
+ StackPtr = TRI->getStackRegister();<br>
}<br>
<br>
bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const {<br>
@@ -63,8 +63,8 @@ bool X86FrameLowering::hasReservedCallFr<br>
bool<br>
X86FrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const {<br>
return hasReservedCallFrame(MF) ||<br>
- (hasFP(MF) && !RegInfo->needsStackRealignment(MF)) ||<br>
- RegInfo->hasBasePointer(MF);<br>
+ (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||<br>
+ TRI->hasBasePointer(MF);<br>
}<br>
<br>
// needsFrameIndexResolution - Do we need to perform FI resolution for<br>
@@ -88,7 +88,7 @@ bool X86FrameLowering::hasFP(const Machi<br>
const MachineModuleInfo &MMI = MF.getMMI();<br>
<br>
return (MF.getTarget().Options.DisableFramePointerElim(MF) ||<br>
- RegInfo->needsStackRealignment(MF) ||<br>
+ TRI->needsStackRealignment(MF) ||<br>
MFI->hasVarSizedObjects() ||<br>
MFI->isFrameAddressTaken() || MFI->hasInlineAsmWithSPAdjust() ||<br>
MF.getInfo<X86MachineFunctionInfo>()->getForceFramePointer() ||<br>
@@ -148,7 +148,7 @@ static unsigned getLEArOpcode(unsigned I<br>
/// to this register without worry about clobbering it.<br>
static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB,<br>
MachineBasicBlock::iterator &MBBI,<br>
- const TargetRegisterInfo *RegInfo,<br>
+ const TargetRegisterInfo *TRI,<br>
bool Is64Bit) {<br>
const MachineFunction *MF = MBB.getParent();<br>
const Function *F = MF->getFunction();<br>
@@ -187,7 +187,7 @@ static unsigned findDeadCallerSavedReg(M<br>
unsigned Reg = MO.getReg();<br>
if (!Reg)<br>
continue;<br>
- for (MCRegAliasIterator AI(Reg, RegInfo, true); AI.isValid(); ++AI)<br>
+ for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)<br>
Uses.insert(*AI);<br>
}<br>
<br>
@@ -257,7 +257,7 @@ void X86FrameLowering::emitSPUpdate(Mach<br>
if (isSub && !isEAXLiveIn(*MBB.getParent()))<br>
Reg = (unsigned)(Is64Bit ? X86::RAX : X86::EAX);<br>
else<br>
- Reg = findDeadCallerSavedReg(MBB, MBBI, RegInfo, Is64Bit);<br>
+ Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);<br>
<br>
if (Reg) {<br>
unsigned Opc = Is64Bit ? X86::MOV64ri : X86::MOV32ri;<br>
@@ -280,7 +280,7 @@ void X86FrameLowering::emitSPUpdate(Mach<br>
// Use push / pop instead.<br>
unsigned Reg = isSub<br>
? (unsigned)(Is64Bit ? X86::RAX : X86::EAX)<br>
- : findDeadCallerSavedReg(MBB, MBBI, RegInfo, Is64Bit);<br>
+ : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit);<br>
if (Reg) {<br>
unsigned Opc = isSub<br>
? (Is64Bit ? X86::PUSH64r : X86::PUSH32r)<br>
@@ -652,12 +652,12 @@ void X86FrameLowering::emitPrologue(Mach<br>
bool NeedsWinCFI = IsWin64Prologue && Fn->needsUnwindTableEntry();<br>
bool NeedsDwarfCFI =<br>
!IsWin64Prologue && (MMI.hasDebugInfo() || Fn->needsUnwindTableEntry());<br>
- unsigned FramePtr = RegInfo->getFrameRegister(MF);<br>
+ unsigned FramePtr = TRI->getFrameRegister(MF);<br>
const unsigned MachineFramePtr =<br>
STI.isTarget64BitILP32()<br>
? getX86SubSuperRegister(FramePtr, MVT::i64, false)<br>
: FramePtr;<br>
- unsigned BasePtr = RegInfo->getBaseRegister();<br>
+ unsigned BasePtr = TRI->getBaseRegister();<br>
DebugLoc DL;<br>
<br>
// Add RETADDR move area to callee saved frame size.<br>
@@ -685,7 +685,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
// stack pointer (we fit in the Red Zone). We also check that we don't<br>
// push and pop from the stack.<br>
if (Is64Bit && !Fn->hasFnAttribute(Attribute::NoRedZone) &&<br>
- !RegInfo->needsStackRealignment(MF) &&<br>
+ !TRI->needsStackRealignment(MF) &&<br>
!MFI->hasVarSizedObjects() && // No dynamic alloca.<br>
!MFI->adjustsStack() && // No calls.<br>
!IsWin64CC && // Win64 has no Red Zone<br>
@@ -733,7 +733,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize();<br>
<br>
// Callee-saved registers are pushed on stack before the stack is realigned.<br>
- if (RegInfo->needsStackRealignment(MF) && !IsWin64Prologue)<br>
+ if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)<br>
NumBytes = RoundUpToAlignment(NumBytes, MaxAlign);<br>
<br>
// Get the offset of the stack slot for the EBP register, which is<br>
@@ -754,7 +754,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
MCCFIInstruction::createDefCfaOffset(nullptr, 2 * stackGrowth));<br>
<br>
// Change the rule for the FramePtr to be an "offset" rule.<br>
- unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);<br>
+ unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);<br>
BuildCFI(MBB, MBBI, DL, MCCFIInstruction::createOffset(<br>
nullptr, DwarfFramePtr, 2 * stackGrowth));<br>
}<br>
@@ -777,7 +777,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
if (NeedsDwarfCFI) {<br>
// Mark effective beginning of when frame pointer becomes valid.<br>
// Define the current CFA to use the EBP/RBP register.<br>
- unsigned DwarfFramePtr = RegInfo->getDwarfRegNum(MachineFramePtr, true);<br>
+ unsigned DwarfFramePtr = TRI->getDwarfRegNum(MachineFramePtr, true);<br>
BuildCFI(MBB, MBBI, DL,<br>
MCCFIInstruction::createDefCfaRegister(nullptr, DwarfFramePtr));<br>
}<br>
@@ -818,7 +818,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
// Realign stack after we pushed callee-saved registers (so that we'll be<br>
// able to calculate their offsets from the frame pointer).<br>
// Don't do this for Win64, it needs to realign the stack after the prologue.<br>
- if (!IsWin64Prologue && RegInfo->needsStackRealignment(MF)) {<br>
+ if (!IsWin64Prologue && TRI->needsStackRealignment(MF)) {<br>
assert(HasFP && "There should be a frame pointer if stack is realigned.");<br>
BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);<br>
}<br>
@@ -839,7 +839,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
// increments is necessary to ensure that the guard pages used by the OS<br>
// virtual memory manager are allocated in correct sequence.<br>
uint64_t AlignedNumBytes = NumBytes;<br>
- if (IsWin64Prologue && RegInfo->needsStackRealignment(MF))<br>
+ if (IsWin64Prologue && TRI->needsStackRealignment(MF))<br>
AlignedNumBytes = RoundUpToAlignment(AlignedNumBytes, MaxAlign);<br>
if (AlignedNumBytes >= StackProbeSize && UseStackProbe) {<br>
// Check whether EAX is livein for this function.<br>
@@ -951,7 +951,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
// Realign stack after we spilled callee-saved registers (so that we'll be<br>
// able to calculate their offsets from the frame pointer).<br>
// Win64 requires aligning the stack after the prologue.<br>
- if (IsWin64Prologue && RegInfo->needsStackRealignment(MF)) {<br>
+ if (IsWin64Prologue && TRI->needsStackRealignment(MF)) {<br>
assert(HasFP && "There should be a frame pointer if stack is realigned.");<br>
BuildStackAlignAND(MBB, MBBI, DL, MaxAlign);<br>
}<br>
@@ -960,7 +960,7 @@ void X86FrameLowering::emitPrologue(Mach<br>
// of the stack pointer is at this point. Any variable size objects<br>
// will be allocated after this, so we can still use the base pointer<br>
// to reference locals.<br>
- if (RegInfo->hasBasePointer(MF)) {<br>
+ if (TRI->hasBasePointer(MF)) {<br>
// Update the base pointer with the current stack pointer.<br>
unsigned Opc = Uses64BitFramePtr ? X86::MOV64rr : X86::MOV32rr;<br>
BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)<br>
@@ -1012,7 +1012,7 @@ void X86FrameLowering::emitEpilogue(Mach<br>
DL = MBBI->getDebugLoc();<br>
// standard x86_64 and NaCl use 64-bit frame/stack pointers, x32 - 32-bit.<br>
const bool Is64BitILP32 = STI.isTarget64BitILP32();<br>
- unsigned FramePtr = RegInfo->getFrameRegister(MF);<br>
+ unsigned FramePtr = TRI->getFrameRegister(MF);<br>
unsigned MachineFramePtr =<br>
Is64BitILP32 ? getX86SubSuperRegister(FramePtr, MVT::i64, false)<br>
: FramePtr;<br>
@@ -1034,7 +1034,7 @@ void X86FrameLowering::emitEpilogue(Mach<br>
<br>
// Callee-saved registers were pushed on stack before the stack was<br>
// realigned.<br>
- if (RegInfo->needsStackRealignment(MF) && !IsWin64Prologue)<br>
+ if (TRI->needsStackRealignment(MF) && !IsWin64Prologue)<br>
NumBytes = RoundUpToAlignment(FrameSize, MaxAlign);<br>
<br>
// Pop EBP.<br>
@@ -1069,8 +1069,8 @@ void X86FrameLowering::emitEpilogue(Mach<br>
// If dynamic alloca is used, then reset esp to point to the last callee-saved<br>
// slot before popping them off! Same applies for the case, when stack was<br>
// realigned.<br>
- if (RegInfo->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {<br>
- if (RegInfo->needsStackRealignment(MF))<br>
+ if (TRI->needsStackRealignment(MF) || MFI->hasVarSizedObjects()) {<br>
+ if (TRI->needsStackRealignment(MF))<br>
MBBI = FirstCSPop;<br>
unsigned SEHFrameOffset = calculateSetFPREG(SEHStackAllocAmt);<br>
uint64_t LEAAmount =<br>
@@ -1160,7 +1160,7 @@ int X86FrameLowering::getFrameIndexOffse<br>
}<br>
<br>
<br>
- if (RegInfo->hasBasePointer(MF)) {<br>
+ if (TRI->hasBasePointer(MF)) {<br>
assert(HasFP && "VLAs and dynamic stack realign, but no FP?!");<br>
if (FI < 0) {<br>
// Skip the saved EBP.<br>
@@ -1169,7 +1169,7 @@ int X86FrameLowering::getFrameIndexOffse<br>
assert((-(Offset + StackSize)) % MFI->getObjectAlignment(FI) == 0);<br>
return Offset + StackSize;<br>
}<br>
- } else if (RegInfo->needsStackRealignment(MF)) {<br>
+ } else if (TRI->needsStackRealignment(MF)) {<br>
if (FI < 0) {<br>
// Skip the saved EBP.<br>
return Offset + SlotSize + FPDelta;<br>
@@ -1199,12 +1199,12 @@ int X86FrameLowering::getFrameIndexRefer<br>
// We can't calculate offset from frame pointer if the stack is realigned,<br>
// so enforce usage of stack/base pointer. The base pointer is used when we<br>
// have dynamic allocas in addition to dynamic realignment.<br>
- if (RegInfo->hasBasePointer(MF))<br>
- FrameReg = RegInfo->getBaseRegister();<br>
- else if (RegInfo->needsStackRealignment(MF))<br>
- FrameReg = RegInfo->getStackRegister();<br>
+ if (TRI->hasBasePointer(MF))<br>
+ FrameReg = TRI->getBaseRegister();<br>
+ else if (TRI->needsStackRealignment(MF))<br>
+ FrameReg = TRI->getStackRegister();<br>
else<br>
- FrameReg = RegInfo->getFrameRegister(MF);<br>
+ FrameReg = TRI->getFrameRegister(MF);<br>
return getFrameIndexOffset(MF, FI);<br>
}<br>
<br>
@@ -1226,7 +1226,7 @@ int X86FrameLowering::getFrameIndexOffse<br>
// frame). As a result, THE RESULT OF THIS CALL IS MEANINGLESS FOR CSRs<br>
// AND FixedObjects IFF needsStackRealignment or hasVarSizedObject.<br>
<br>
- assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");<br>
+ assert(!TRI->hasBasePointer(MF) && "we don't handle this case");<br>
<br>
// We don't handle tail calls, and shouldn't be seeing them<br>
// either.<br>
@@ -1271,9 +1271,9 @@ int X86FrameLowering::getFrameIndexOffse<br>
int X86FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,<br>
int FI,<br>
unsigned &FrameReg) const {<br>
- assert(!RegInfo->hasBasePointer(MF) && "we don't handle this case");<br>
+ assert(!TRI->hasBasePointer(MF) && "we don't handle this case");<br>
<br>
- FrameReg = RegInfo->getStackRegister();<br>
+ FrameReg = TRI->getStackRegister();<br>
return getFrameIndexOffsetFromSP(MF, FI);<br>
}<br>
<br>
@@ -1294,7 +1294,7 @@ bool X86FrameLowering::assignCalleeSaved<br>
// Since emitPrologue and emitEpilogue will handle spilling and restoring of<br>
// the frame register, we can delete it from CSI list and not have to worry<br>
// about avoiding it later.<br>
- unsigned FPReg = RegInfo->getFrameRegister(MF);<br>
+ unsigned FPReg = TRI->getFrameRegister(MF);<br>
for (unsigned i = 0; i < CSI.size(); ++i) {<br>
if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {<br>
CSI.erase(CSI.begin() + i);<br>
@@ -1325,7 +1325,7 @@ bool X86FrameLowering::assignCalleeSaved<br>
if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))<br>
continue;<br>
<br>
- const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);<br>
+ const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);<br>
// ensure alignment<br>
SpillSlotOffset -= std::abs(SpillSlotOffset) % RC->getAlignment();<br>
// spill into slot<br>
@@ -1435,8 +1435,8 @@ X86FrameLowering::processFunctionBeforeC<br>
}<br>
<br>
// Spill the BasePtr if it's used.<br>
- if (RegInfo->hasBasePointer(MF))<br>
- MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister());<br>
+ if (TRI->hasBasePointer(MF))<br>
+ MF.getRegInfo().setPhysRegUsed(TRI->getBaseRegister());<br>
}<br>
<br>
static bool<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_X86_X86FrameLowering.h-3Frev-3D240047-26r1-3D240046-26r2-3D240047-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=x5JabzHKiDFs3t-o5pPsfSmlgFW-jSpC5_1BiyJP_aU&s=VIUfzGOFNyzakr2dazrgv5ZwZHxCQTTviqSHhoEzt-o&e=" rel="noreferrer" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?rev=240047&r1=240046&r2=240047&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FrameLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Thu Jun 18 15:32:02 2015<br>
@@ -31,7 +31,7 @@ public:<br>
<br>
const X86Subtarget &STI;<br>
const TargetInstrInfo &TII;<br>
- const X86RegisterInfo *RegInfo;<br>
+ const X86RegisterInfo *TRI;<br>
<br>
unsigned SlotSize;<br>
<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" rel="noreferrer" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</blockquote></div>