<div dir="ltr">This broke the Windows self-host:<div><a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__lab.llvm.org-3A8011_builders_clang-2Dx86-2Dwin2008-2Dselfhost_builds_1279&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=U7nVjyEzW7wmTTFVPQsjKjrshwlki-O9K98AjuM4W3E&s=0uthcyGdYTn3AIVVKSNdhoH2mgk9SIU7A-youtgwjao&e=">http://lab.llvm.org:8011/builders/clang-x86-win2008-selfhost/builds/1279</a><br></div><div><br></div><div><span style="font-size:12.8000001907349px">+ // Some places use this if the address space can't be determined.</span><br style="font-size:12.8000001907349px"><span style="font-size:12.8000001907349px">+ UNKNOWN_ADDRESS_SPACE = ~0u</span><br></div><div><span style="font-size:12.8000001907349px"><br></span></div><div><span style="font-size:12.8000001907349px">On Windows, enums are always ints unless you say otherwise, so clang-cl gave us this:</span></div><div><span style="font-size:12.8000001907349px"><br></span></div><div><div style><span style="font-size:12.8000001907349px">..\lib\Target\R600/AMDGPU.h(143,3) : warning: enumerator value is not representable in the underlying type 'int' [-Wmicrosoft]</span></div><div style><span style="font-size:12.8000001907349px"> UNKNOWN_ADDRESS_SPACE = ~0u</span></div><div style><span style="font-size:12.8000001907349px"> ^</span></div><div style><span style="font-size:12.8000001907349px">..\lib\Target\R600\SIISelLowering.cpp(263,8) : error: case value evaluates to -1, which cannot be narrowed to type 'unsigned int' [-Wc++11-narrowing]</span></div><div style><span style="font-size:12.8000001907349px"> case AMDGPUAS::UNKNOWN_ADDRESS_SPACE: {</span></div><div style><span style="font-size:12.8000001907349px"> ^</span></div></div><div><br></div><div>I think MSVC doesn't implement C++11 narrowing checks. I'll have a fix soon.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Jun 4, 2015 at 9:17 AM, Matt Arsenault <span dir="ltr"><<a href="mailto:Matthew.Arsenault@amd.com" target="_blank">Matthew.Arsenault@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: arsenm<br>
Date: Thu Jun 4 11:17:42 2015<br>
New Revision: 239053<br>
<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject-3Frev-3D239053-26view-3Drev&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=U7nVjyEzW7wmTTFVPQsjKjrshwlki-O9K98AjuM4W3E&s=s1EpAhUEHDpOO9kfuLBZECZ2Q_bPVWIvIawl6j8wQYI&e=" target="_blank">http://llvm.org/viewvc/llvm-project?rev=239053&view=rev</a><br>
Log:<br>
R600/SI: Reimplement isLegalAddressingMode<br>
<br>
Now that we sometimes know the address space, this can<br>
theoretically do a better job.<br>
<br>
This needs better test coverage, but this mostly depends on<br>
first updating the loop optimizatiosn to provide the address<br>
space.<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll<br>
Modified:<br>
llvm/trunk/lib/Target/R600/AMDGPU.h<br>
llvm/trunk/lib/Target/R600/SIISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/R600/AMDGPU.h<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_R600_AMDGPU.h-3Frev-3D239053-26r1-3D239052-26r2-3D239053-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=U7nVjyEzW7wmTTFVPQsjKjrshwlki-O9K98AjuM4W3E&s=Iej0hUCBrcUn3pxJEO_74hA9MXoabYoJTrE5dieIvC4&e=" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.h?rev=239053&r1=239052&r2=239053&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/AMDGPU.h (original)<br>
+++ llvm/trunk/lib/Target/R600/AMDGPU.h Thu Jun 4 11:17:42 2015<br>
@@ -137,7 +137,10 @@ enum AddressSpaces {<br>
CONSTANT_BUFFER_14 = 22,<br>
CONSTANT_BUFFER_15 = 23,<br>
ADDRESS_NONE = 24, ///< Address space for unknown memory.<br>
- LAST_ADDRESS = ADDRESS_NONE<br>
+ LAST_ADDRESS = ADDRESS_NONE,<br>
+<br>
+ // Some places use this if the address space can't be determined.<br>
+ UNKNOWN_ADDRESS_SPACE = ~0u<br>
};<br>
<br>
} // namespace AMDGPUAS<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_lib_Target_R600_SIISelLowering.cpp-3Frev-3D239053-26r1-3D239052-26r2-3D239053-26view-3Ddiff&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=U7nVjyEzW7wmTTFVPQsjKjrshwlki-O9K98AjuM4W3E&s=6IqmqKomVm4BR2CLtjKvk4H1UAuNtQdzU4itocstSYc&e=" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=239053&r1=239052&r2=239053&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Thu Jun 4 11:17:42 2015<br>
@@ -250,47 +250,83 @@ bool SITargetLowering::isShuffleMaskLega<br>
return false;<br>
}<br>
<br>
-// FIXME: This really needs an address space argument. The immediate offset<br>
-// size is different for different sets of memory instruction sets.<br>
-<br>
-// The single offset DS instructions have a 16-bit unsigned byte offset.<br>
-//<br>
-// MUBUF / MTBUF have a 12-bit unsigned byte offset, and additionally can do r +<br>
-// r + i with addr64. 32-bit has more addressing mode options. Depending on the<br>
-// resource constant, it can also do (i64 r0) + (i32 r1) * (i14 i).<br>
-//<br>
-// SMRD instructions have an 8-bit, dword offset.<br>
-//<br>
bool SITargetLowering::isLegalAddressingMode(const AddrMode &AM,<br>
Type *Ty, unsigned AS) const {<br>
// No global is ever allowed as a base.<br>
if (AM.BaseGV)<br>
return false;<br>
<br>
- // Allow a 16-bit unsigned immediate field, since this is what DS instructions<br>
- // use.<br>
- if (!isUInt<16>(AM.BaseOffs))<br>
- return false;<br>
+ switch (AS) {<br>
+ case AMDGPUAS::GLOBAL_ADDRESS:<br>
+ case AMDGPUAS::CONSTANT_ADDRESS: // XXX - Should we assume SMRD instructions?<br>
+ case AMDGPUAS::PRIVATE_ADDRESS:<br>
+ case AMDGPUAS::UNKNOWN_ADDRESS_SPACE: {<br>
+ // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and<br>
+ // additionally can do r + r + i with addr64. 32-bit has more addressing<br>
+ // mode options. Depending on the resource constant, it can also do<br>
+ // (i64 r0) + (i32 r1) * (i14 i).<br>
+ //<br>
+ // SMRD instructions have an 8-bit, dword offset.<br>
+ //<br>
+ // Assume nonunifom access, since the address space isn't enough to know<br>
+ // what instruction we will use, and since we don't know if this is a load<br>
+ // or store and scalar stores are only available on VI.<br>
+ //<br>
+ // We also know if we are doing an extload, we can't do a scalar load.<br>
+ //<br>
+ // Private arrays end up using a scratch buffer most of the time, so also<br>
+ // assume those use MUBUF instructions. Scratch loads / stores are currently<br>
+ // implemented as mubuf instructions with offen bit set, so slightly<br>
+ // different than the normal addr64.<br>
+ if (!isUInt<12>(AM.BaseOffs))<br>
+ return false;<br>
<br>
- // Only support r+r,<br>
- switch (AM.Scale) {<br>
- case 0: // "r+i" or just "i", depending on HasBaseReg.<br>
- break;<br>
- case 1:<br>
- if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.<br>
+ // FIXME: Since we can split immediate into soffset and immediate offset,<br>
+ // would it make sense to allow any immediate?<br>
+<br>
+ switch (AM.Scale) {<br>
+ case 0: // r + i or just i, depending on HasBaseReg.<br>
+ return true;<br>
+ case 1:<br>
+ return true; // We have r + r or r + i.<br>
+ case 2:<br>
+ if (AM.HasBaseReg) {<br>
+ // Reject 2 * r + r.<br>
+ return false;<br>
+ }<br>
+<br>
+ // Allow 2 * r as r + r<br>
+ // Or 2 * r + i is allowed as r + r + i.<br>
+ return true;<br>
+ default: // Don't allow n * r<br>
return false;<br>
- // Otherwise we have r+r or r+i.<br>
- break;<br>
- case 2:<br>
- if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.<br>
+ }<br>
+ }<br>
+ case AMDGPUAS::LOCAL_ADDRESS:<br>
+ case AMDGPUAS::REGION_ADDRESS: {<br>
+ // Basic, single offset DS instructions allow a 16-bit unsigned immediate<br>
+ // field.<br>
+ // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have<br>
+ // an 8-bit dword offset but we don't know the alignment here.<br>
+ if (!isUInt<16>(AM.BaseOffs))<br>
return false;<br>
- // Allow 2*r as r+r.<br>
- break;<br>
- default: // Don't allow n * r<br>
+<br>
+ if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.<br>
+ return true;<br>
+<br>
+ if (AM.Scale == 1 && AM.HasBaseReg)<br>
+ return true;<br>
+<br>
return false;<br>
}<br>
-<br>
- return true;<br>
+ case AMDGPUAS::FLAT_ADDRESS: {<br>
+ // Flat instructions do not have offsets, and only have the register<br>
+ // address.<br>
+ return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);<br>
+ }<br>
+ default:<br>
+ llvm_unreachable("unhandled address space");<br>
+ }<br>
}<br>
<br>
bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,<br>
<br>
Added: llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll<br>
URL: <a href="https://urldefense.proofpoint.com/v2/url?u=http-3A__llvm.org_viewvc_llvm-2Dproject_llvm_trunk_test_CodeGen_R600_cgp-2Daddressing-2Dmodes.ll-3Frev-3D239053-26view-3Dauto&d=AwMFaQ&c=8hUWFZcy2Z-Za5rBPlktOQ&r=mQ4LZ2PUj9hpadE3cDHZnIdEwhEBrbAstXeMaFoB9tg&m=U7nVjyEzW7wmTTFVPQsjKjrshwlki-O9K98AjuM4W3E&s=cIm2IhmLD-TH9z56YUbYgS8y6T6v4XMbHUDpvt8OHTQ&e=" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll?rev=239053&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll (added)<br>
+++ llvm/trunk/test/CodeGen/R600/cgp-addressing-modes.ll Thu Jun 4 11:17:42 2015<br>
@@ -0,0 +1,242 @@<br>
+; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown < %s | FileCheck -check-prefix=OPT %s<br>
+; RUN: llc -march=amdgcn -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN %s<br>
+<br>
+declare i32 @llvm.r600.read.tidig.x() #0<br>
+<br>
+; OPT-LABEL: @test_sink_global_small_offset_i32(<br>
+; OPT-NOT: getelementptr i32, i32 addrspace(1)* %in<br>
+; OPT: br i1<br>
+; OPT: ptrtoint<br>
+<br>
+; GCN-LABEL: {{^}}test_sink_global_small_offset_i32:<br>
+; GCN: {{^}}BB0_2:<br>
+define void @test_sink_global_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond) {<br>
+entry:<br>
+ %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999<br>
+ %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 7<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ %tmp1 = load i32, i32 addrspace(1)* %in.gep<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; OPT-LABEL: @test_sink_global_small_max_i32_ds_offset(<br>
+; OPT: %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535<br>
+; OPT: br i1<br>
+<br>
+; GCN-LABEL: {{^}}test_sink_global_small_max_i32_ds_offset:<br>
+; GCN: s_and_saveexec_b64<br>
+; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}<br>
+; GCN: {{^}}BB1_2:<br>
+; GCN: s_or_b64 exec<br>
+define void @test_sink_global_small_max_i32_ds_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {<br>
+entry:<br>
+ %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999<br>
+ %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 65535<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ %tmp1 = load i8, i8 addrspace(1)* %in.gep<br>
+ %tmp2 = sext i8 %tmp1 to i32<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}test_sink_global_small_max_mubuf_offset:<br>
+; GCN: s_and_saveexec_b64<br>
+; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4095{{$}}<br>
+; GCN: {{^}}BB2_2:<br>
+; GCN: s_or_b64 exec<br>
+define void @test_sink_global_small_max_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {<br>
+entry:<br>
+ %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024<br>
+ %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4095<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ %tmp1 = load i8, i8 addrspace(1)* %in.gep<br>
+ %tmp2 = sext i8 %tmp1 to i32<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}test_sink_global_small_max_plus_1_mubuf_offset:<br>
+; GCN: s_and_saveexec_b64<br>
+; GCN: buffer_load_sbyte {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}<br>
+; GCN: {{^}}BB3_2:<br>
+; GCN: s_or_b64 exec<br>
+define void @test_sink_global_small_max_plus_1_mubuf_offset(i32 addrspace(1)* %out, i8 addrspace(1)* %in, i32 %cond) {<br>
+entry:<br>
+ %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 99999<br>
+ %in.gep = getelementptr i8, i8 addrspace(1)* %in, i64 4096<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ %tmp1 = load i8, i8 addrspace(1)* %in.gep<br>
+ %tmp2 = sext i8 %tmp1 to i32<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; OPT-LABEL: @test_no_sink_flat_small_offset_i32(<br>
+; OPT: getelementptr i32, i32 addrspace(4)* %in<br>
+; OPT: br i1<br>
+; OPT-NOT: ptrtoint<br>
+<br>
+; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32:<br>
+; GCN: flat_load_dword<br>
+; GCN: {{^}}BB4_2:<br>
+<br>
+define void @test_no_sink_flat_small_offset_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) {<br>
+entry:<br>
+ %out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999<br>
+ %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ %tmp1 = load i32, i32 addrspace(4)* %in.gep<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(4)* %out.gep<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; OPT-LABEL: @test_sink_scratch_small_offset_i32(<br>
+; OPT-NOT: getelementptr [512 x i32]<br>
+; OPT: br i1<br>
+; OPT: ptrtoint<br>
+<br>
+; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32:<br>
+; GCN: s_and_saveexec_b64<br>
+; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}<br>
+; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}<br>
+; GCN: {{^}}BB5_2:<br>
+define void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) {<br>
+entry:<br>
+ %alloca = alloca [512 x i32], align 4<br>
+ %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998<br>
+ %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999<br>
+ %add.arg = add i32 %arg, 8<br>
+ %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1023<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ store volatile i32 123, i32* %alloca.gep<br>
+ %tmp1 = load volatile i32, i32* %alloca.gep<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep.0<br>
+ %load = load volatile i32, i32* %alloca.gep<br>
+ store i32 %load, i32 addrspace(1)* %out.gep.1<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; OPT-LABEL: @test_no_sink_scratch_large_offset_i32(<br>
+; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024<br>
+; OPT: br i1<br>
+; OPT-NOT: ptrtoint<br>
+<br>
+; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32:<br>
+; GCN: s_and_saveexec_b64<br>
+; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}<br>
+; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}<br>
+; GCN: {{^}}BB6_2:<br>
+define void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %cond, i32 %arg) {<br>
+entry:<br>
+ %alloca = alloca [512 x i32], align 4<br>
+ %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998<br>
+ %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999<br>
+ %add.arg = add i32 %arg, 8<br>
+ %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ store volatile i32 123, i32* %alloca.gep<br>
+ %tmp1 = load volatile i32, i32* %alloca.gep<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep.0<br>
+ %load = load volatile i32, i32* %alloca.gep<br>
+ store i32 %load, i32 addrspace(1)* %out.gep.1<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32:<br>
+; GCN: s_and_saveexec_b64<br>
+; GCN: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}<br>
+; GCN: {{^}}BB7_2:<br>
+define void @test_sink_global_vreg_sreg_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %offset, i32 %cond) {<br>
+entry:<br>
+ %offset.ext = zext i32 %offset to i64<br>
+ %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999<br>
+ %in.gep = getelementptr i32, i32 addrspace(1)* %in, i64 %offset.ext<br>
+ %tmp0 = icmp eq i32 %cond, 0<br>
+ br i1 %tmp0, label %endif, label %if<br>
+<br>
+if:<br>
+ %tmp1 = load i32, i32 addrspace(1)* %in.gep<br>
+ br label %endif<br>
+<br>
+endif:<br>
+ %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]<br>
+ store i32 %x, i32 addrspace(1)* %out.gep<br>
+ br label %done<br>
+<br>
+done:<br>
+ ret void<br>
+}<br>
+<br>
+attributes #0 = { nounwind readnone }<br>
+attributes #1 = { nounwind }<br>
<br>
<br>
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</blockquote></div><br></div>