<div dir="ltr">Not really. There's no way to autoupgrade depending on target and since we _always_ emitted the use-soft-float attribute, even on targets that don't support it, we'd need to have a) every target support +soft-float or b) turn off the warning for unsupported subtarget features if that one happened to be +soft-float. <div><br></div><div>-eric<br><br><div class="gmail_quote">On Wed, May 13, 2015 at 4:34 PM Akira Hatanaka <<a href="mailto:ahatanak@gmail.com">ahatanak@gmail.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><div class="gmail_extra">I wonder if adding a function which upgrades an old IR would simplify the backend a little. Currently, getSubtargetImp adds "+soft-float" to target-features if there is function attribute "use-soft-float"="true", but that piece of code can be removed if it's done in autoupgrade.</div></div><div dir="ltr"><div class="gmail_extra"><br></div><div class="gmail_extra"><div class="gmail_quote">On Wed, May 13, 2015 at 1:59 PM, Eric Christopher <span dir="ltr"><<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div dir="ltr">Yep, next on my list. I hadn't just because I wanted to get the existing format down in a way that we can deal with and see if there's a need for additional command line options etc. The backends can adapt to the changed and existing codegen, etc right now and I don't think there's any additional need for command line options, or upgrading the IR to a new format.<span><font color="#888888"><br><br>-eric</font></span><div><div><br><br><div class="gmail_quote">On Tue, May 12, 2015 at 11:04 AM Akira Hatanaka <<a href="mailto:ahatanak@gmail.com" target="_blank">ahatanak@gmail.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div dir="ltr">Is clang going to stop emitting attribute "use-soft-float" now that "+soft-float" is embedded in the feature string?</div><div dir="ltr"><div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, May 11, 2015 at 6:26 PM, Eric Christopher <span dir="ltr"><<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: echristo<br>
Date: Mon May 11 20:26:05 2015<br>
New Revision: 237079<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=237079&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=237079&view=rev</a><br>
Log:<br>
Migrate existing backends that care about software floating point<br>
to use the information in the module rather than TargetOptions.<br>
<br>
We've had and clang has used the use-soft-float attribute for some<br>
time now so have the backends set a subtarget feature based on<br>
a particular function now that subtargets are created based on<br>
functions and function attributes.<br>
<br>
For the one middle end soft float check go ahead and create<br>
an overloadable TargetLowering::useSoftFloat function that<br>
just checks the TargetSubtargetInfo in all cases.<br>
<br>
Also remove the command line option that hard codes whether or<br>
not soft-float is set by using the attribute for all of the<br>
target specific test cases - for the generic just go ahead and<br>
add the attribute in the one case that showed up.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/CodeGen/CommandFlags.h<br>
llvm/trunk/include/llvm/Target/TargetLowering.h<br>
llvm/trunk/include/llvm/Target/TargetOptions.h<br>
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
llvm/trunk/lib/Target/ARM/ARM.td<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
llvm/trunk/lib/Target/ARM/ARMSubtarget.h<br>
llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp<br>
llvm/trunk/lib/Target/TargetMachine.cpp<br>
llvm/trunk/lib/Target/X86/X86.td<br>
llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
llvm/trunk/test/CodeGen/ARM/vfp-libcalls.ll<br>
llvm/trunk/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll<br>
llvm/trunk/test/CodeGen/X86/cvt16.ll<br>
llvm/trunk/test/CodeGen/X86/floor-soft-float.ll<br>
llvm/trunk/test/CodeGen/X86/soft-fp.ll<br>
llvm/trunk/tools/llc/llc.cpp<br>
llvm/trunk/tools/lli/lli.cpp<br>
<br>
Modified: llvm/trunk/include/llvm/CodeGen/CommandFlags.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CommandFlags.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/CommandFlags.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/CodeGen/CommandFlags.h (original)<br>
+++ llvm/trunk/include/llvm/CodeGen/CommandFlags.h Mon May 11 20:26:05 2015<br>
@@ -126,11 +126,6 @@ EnableHonorSignDependentRoundingFPMath("<br>
cl::desc("Force codegen to assume rounding mode can change dynamically"),<br>
cl::init(false));<br>
<br>
-cl::opt<bool><br>
-GenerateSoftFloatCalls("soft-float",<br>
- cl::desc("Generate software floating point library calls"),<br>
- cl::init(false));<br>
-<br>
cl::opt<llvm::FloatABI::ABIType><br>
FloatABIForCalls("float-abi",<br>
cl::desc("Choose float ABI type"),<br>
@@ -241,7 +236,6 @@ static inline TargetOptions InitTargetOp<br>
Options.NoNaNsFPMath = EnableNoNaNsFPMath;<br>
Options.HonorSignDependentRoundingFPMathOption =<br>
EnableHonorSignDependentRoundingFPMath;<br>
- Options.UseSoftFloat = GenerateSoftFloatCalls;<br>
if (FloatABIForCalls != FloatABI::Default)<br>
Options.FloatABIType = FloatABIForCalls;<br>
Options.NoZerosInBSS = DontPlaceZerosInBSS;<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon May 11 20:26:05 2015<br>
@@ -165,6 +165,7 @@ public:<br>
<br>
bool isBigEndian() const { return !IsLittleEndian; }<br>
bool isLittleEndian() const { return IsLittleEndian; }<br>
+ virtual bool useSoftFloat() const { return false; }<br>
<br>
/// Return the pointer type for the given address space, defaults to<br>
/// the pointer type from the data layout.<br>
<br>
Modified: llvm/trunk/include/llvm/Target/TargetOptions.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)<br>
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Mon May 11 20:26:05 2015<br>
@@ -63,7 +63,7 @@ namespace llvm {<br>
: PrintMachineCode(false), NoFramePointerElim(false),<br>
LessPreciseFPMADOption(false), UnsafeFPMath(false),<br>
NoInfsFPMath(false), NoNaNsFPMath(false),<br>
- HonorSignDependentRoundingFPMathOption(false), UseSoftFloat(false),<br>
+ HonorSignDependentRoundingFPMathOption(false),<br>
NoZerosInBSS(false),<br>
GuaranteedTailCallOpt(false),<br>
DisableTailCalls(false), StackAlignmentOverride(0),<br>
@@ -127,12 +127,6 @@ namespace llvm {<br>
unsigned HonorSignDependentRoundingFPMathOption : 1;<br>
bool HonorSignDependentRoundingFPMath() const;<br>
<br>
- /// UseSoftFloat - This flag is enabled when the -soft-float flag is<br>
- /// specified on the command line. When this flag is on, the code generator<br>
- /// will generate libcalls to the software floating point library instead of<br>
- /// target FP instructions.<br>
- unsigned UseSoftFloat : 1;<br>
-<br>
/// NoZerosInBSS - By default some codegens place zero-initialized data to<br>
/// .bss section. This flag disables such behaviour (necessary, e.g. for<br>
/// crt*.o compiling).<br>
@@ -240,7 +234,6 @@ inline bool operator==(const TargetOptio<br>
ARE_EQUAL(NoInfsFPMath) &&<br>
ARE_EQUAL(NoNaNsFPMath) &&<br>
ARE_EQUAL(HonorSignDependentRoundingFPMathOption) &&<br>
- ARE_EQUAL(UseSoftFloat) &&<br>
ARE_EQUAL(NoZerosInBSS) &&<br>
ARE_EQUAL(GuaranteedTailCallOpt) &&<br>
ARE_EQUAL(DisableTailCalls) &&<br>
<br>
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)<br>
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon May 11 20:26:05 2015<br>
@@ -3456,7 +3456,7 @@ void SelectionDAGLegalize::ExpandNode(SD<br>
break;<br>
}<br>
case ISD::FP_TO_FP16: {<br>
- if (!TM.Options.UseSoftFloat && TM.Options.UnsafeFPMath) {<br>
+ if (!TLI.useSoftFloat() && TM.Options.UnsafeFPMath) {<br>
SDValue Op = Node->getOperand(0);<br>
MVT SVT = Op.getSimpleValueType();<br>
if ((SVT == MVT::f64 || SVT == MVT::f80) &&<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARM.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARM.td (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARM.td Mon May 11 20:26:05 2015<br>
@@ -23,6 +23,9 @@ include "llvm/Target/Target.td"<br>
def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",<br>
"Thumb mode">;<br>
<br>
+def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",<br>
+ "Use software floating point features.">;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// ARM Subtarget features.<br>
//<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon May 11 20:26:05 2015<br>
@@ -170,7 +170,7 @@ ARMTargetLowering::ARMTargetLowering(con<br>
if (Subtarget->isTargetMachO()) {<br>
// Uses VFP for Thumb libfuncs if available.<br>
if (Subtarget->isThumb() && Subtarget->hasVFP2() &&<br>
- Subtarget->hasARMOps() && !TM.Options.UseSoftFloat) {<br>
+ Subtarget->hasARMOps() && !Subtarget->useSoftFloat()) {<br>
// Single-precision floating-point arithmetic.<br>
setLibcallName(RTLIB::ADD_F32, "__addsf3vfp");<br>
setLibcallName(RTLIB::SUB_F32, "__subsf3vfp");<br>
@@ -401,7 +401,7 @@ ARMTargetLowering::ARMTargetLowering(con<br>
addRegisterClass(MVT::i32, &ARM::tGPRRegClass);<br>
else<br>
addRegisterClass(MVT::i32, &ARM::GPRRegClass);<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&<br>
!Subtarget->isThumb1Only()) {<br>
addRegisterClass(MVT::f32, &ARM::SPRRegClass);<br>
addRegisterClass(MVT::f64, &ARM::DPRRegClass);<br>
@@ -820,7 +820,7 @@ ARMTargetLowering::ARMTargetLowering(con<br>
}<br>
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&<br>
!Subtarget->isThumb1Only()) {<br>
// Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR<br>
// iff target supports vfp2.<br>
@@ -861,7 +861,7 @@ ARMTargetLowering::ARMTargetLowering(con<br>
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);<br>
setOperationAction(ISD::FREM, MVT::f64, Expand);<br>
setOperationAction(ISD::FREM, MVT::f32, Expand);<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasVFP2() &&<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasVFP2() &&<br>
!Subtarget->isThumb1Only()) {<br>
setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom);<br>
setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom);<br>
@@ -875,7 +875,7 @@ ARMTargetLowering::ARMTargetLowering(con<br>
}<br>
<br>
// Various VFP goodness<br>
- if (!TM.Options.UseSoftFloat && !Subtarget->isThumb1Only()) {<br>
+ if (!Subtarget->useSoftFloat() && !Subtarget->isThumb1Only()) {<br>
// FP-ARMv8 adds f64 <-> f16 conversion. Before that it should be expanded.<br>
if (!Subtarget->hasFPARMv8() || Subtarget->isFPOnlySP()) {<br>
setOperationAction(ISD::FP16_TO_FP, MVT::f64, Expand);<br>
@@ -932,7 +932,7 @@ ARMTargetLowering::ARMTargetLowering(con<br>
<br>
setStackPointerRegisterToSaveRestore(ARM::SP);<br>
<br>
- if (TM.Options.UseSoftFloat || Subtarget->isThumb1Only() ||<br>
+ if (Subtarget->useSoftFloat() || Subtarget->isThumb1Only() ||<br>
!Subtarget->hasVFP2())<br>
setSchedulingPreference(Sched::RegPressure);<br>
else<br>
@@ -956,6 +956,10 @@ ARMTargetLowering::ARMTargetLowering(con<br>
setMinFunctionAlignment(Subtarget->isThumb() ? 1 : 2);<br>
}<br>
<br>
+bool ARMTargetLowering::useSoftFloat() const {<br>
+ return Subtarget->useSoftFloat();<br>
+}<br>
+<br>
// FIXME: It might make sense to define the representative register class as the<br>
// nearest super-register that has a non-null superset. For example, DPR_VFP2 is<br>
// a super-register of SPR, and DPR is a superset if DPR_VFP2. Consequently,<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon May 11 20:26:05 2015<br>
@@ -231,6 +231,7 @@ namespace llvm {<br>
const ARMSubtarget &STI);<br>
<br>
unsigned getJumpTableEncoding() const override;<br>
+ bool useSoftFloat() const override;<br>
<br>
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Mon May 11 20:26:05 2015<br>
@@ -145,6 +145,7 @@ void ARMSubtarget::initializeEnvironment<br>
HasVMLxForwarding = false;<br>
SlowFPBrcc = false;<br>
InThumbMode = false;<br>
+ UseSoftFloat = false;<br>
HasThumb2 = false;<br>
NoARM = false;<br>
IsR9Reserved = ReserveR9;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Mon May 11 20:26:05 2015<br>
@@ -100,6 +100,9 @@ protected:<br>
/// InThumbMode - True if compiling for Thumb, false for ARM.<br>
bool InThumbMode;<br>
<br>
+ /// UseSoftFloat - True if we're using software floating point features.<br>
+ bool UseSoftFloat;<br>
+<br>
/// HasThumb2 - True if Thumb2 instructions are supported.<br>
bool HasThumb2;<br>
<br>
@@ -393,6 +396,7 @@ public:<br>
bool isAPCS_ABI() const;<br>
bool isAAPCS_ABI() const;<br>
<br>
+ bool useSoftFloat() const { return UseSoftFloat; }<br>
bool isThumb() const { return InThumbMode; }<br>
bool isThumb1Only() const { return InThumbMode && !HasThumb2; }<br>
bool isThumb2() const { return InThumbMode && HasThumb2; }<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon May 11 20:26:05 2015<br>
@@ -207,13 +207,15 @@ ARMBaseTargetMachine::getSubtargetImpl(c<br>
// function before we can generate a subtarget. We also need to use<br>
// it as a key for the subtarget since that can be the only difference<br>
// between two functions.<br>
- Attribute SFAttr = F.getFnAttribute("use-soft-float");<br>
- bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)<br>
- ? SFAttr.getValueAsString() == "true"<br>
- : Options.UseSoftFloat;<br>
+ bool SoftFloat =<br>
+ F.hasFnAttribute("use-soft-float") &&<br>
+ F.getFnAttribute("use-soft-float").getValueAsString() == "true";<br>
+ // If the soft float attribute is set on the function turn on the soft float<br>
+ // subtarget feature.<br>
+ if (SoftFloat)<br>
+ FS += FS.empty() ? "+soft-float" : ",+soft-float";<br>
<br>
- auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"<br>
- : "use-soft-float=false")];<br>
+ auto &I = SubtargetMap[CPU + FS];<br>
if (!I) {<br>
// This needs to be done before we create a new subtarget since any<br>
// creation will depend on the TM and the code generation flags on the<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon May 11 20:26:05 2015<br>
@@ -3598,6 +3598,10 @@ unsigned MipsTargetLowering::getJumpTabl<br>
return TargetLowering::getJumpTableEncoding();<br>
}<br>
<br>
+bool MipsTargetLowering::useSoftFloat() const {<br>
+ return Subtarget.useSoftFloat();<br>
+}<br>
+<br>
void MipsTargetLowering::copyByValRegs(<br>
SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains, SelectionDAG &DAG,<br>
const ISD::ArgFlagsTy &Flags, SmallVectorImpl<SDValue> &InVals,<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon May 11 20:26:05 2015<br>
@@ -530,6 +530,7 @@ namespace llvm {<br>
bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;<br>
<br>
unsigned getJumpTableEncoding() const override;<br>
+ bool useSoftFloat() const override;<br>
<br>
/// Emit a sign-extension using sll/sra, seb, or seh appropriately.<br>
MachineBasicBlock *emitSignExtendToI32InReg(MachineInstr *MI,<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon May 11 20:26:05 2015<br>
@@ -140,10 +140,9 @@ MipsTargetMachine::getSubtargetImpl(cons<br>
// FIXME: This is related to the code below to reset the target options,<br>
// we need to know whether or not the soft float flag is set on the<br>
// function, so we can enable it as a subtarget feature.<br>
- Attribute SFAttr = F.getFnAttribute("use-soft-float");<br>
- bool softFloat = !SFAttr.hasAttribute(Attribute::None)<br>
- ? SFAttr.getValueAsString() == "true"<br>
- : Options.UseSoftFloat;<br>
+ bool softFloat =<br>
+ F.hasFnAttribute("use-soft-float") &&<br>
+ F.getFnAttribute("use-soft-float").getValueAsString() == "true";<br>
<br>
if (hasMips16Attr)<br>
FS += FS.empty() ? "+mips16" : ",+mips16";<br>
<br>
Modified: llvm/trunk/lib/Target/TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/TargetMachine.cpp Mon May 11 20:26:05 2015<br>
@@ -71,7 +71,6 @@ void TargetMachine::resetTargetOptions(c<br>
RESET_OPTION(UnsafeFPMath, "unsafe-fp-math");<br>
RESET_OPTION(NoInfsFPMath, "no-infs-fp-math");<br>
RESET_OPTION(NoNaNsFPMath, "no-nans-fp-math");<br>
- RESET_OPTION(UseSoftFloat, "use-soft-float");<br>
RESET_OPTION(DisableTailCalls, "disable-tail-calls");<br>
<br>
Options.MCOptions.SanitizeAddress = F.hasFnAttribute(Attribute::SanitizeAddress);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86.td Mon May 11 20:26:05 2015<br>
@@ -192,6 +192,9 @@ def FeatureUseSqrtEst : SubtargetFeature<br>
"Use RSQRT* to optimize square root calculations">;<br>
def FeatureUseRecipEst : SubtargetFeature<"use-recip-est", "UseReciprocalEst",<br>
"true", "Use RCP* to optimize division calculations">;<br>
+def FeatureSoftFloat<br>
+ : SubtargetFeature<"soft-float", "UseSoftFloat", "true",<br>
+ "Use software floating point features.">;<br>
<br>
//===----------------------------------------------------------------------===//<br>
// X86 processors supported.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon May 11 20:26:05 2015<br>
@@ -2254,7 +2254,7 @@ bool X86FastISel::fastLowerIntrinsicCall<br>
default: return false;<br>
case Intrinsic::convert_from_fp16:<br>
case Intrinsic::convert_to_fp16: {<br>
- if (TM.Options.UseSoftFloat || !Subtarget->hasF16C())<br>
+ if (Subtarget->useSoftFloat() || !Subtarget->hasF16C())<br>
return false;<br>
<br>
const Value *Op = II->getArgOperand(0);<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 11 20:26:05 2015<br>
@@ -183,7 +183,7 @@ X86TargetLowering::X86TargetLowering(con<br>
if (Subtarget->is64Bit()) {<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);<br>
- } else if (!TM.Options.UseSoftFloat) {<br>
+ } else if (!Subtarget->useSoftFloat()) {<br>
// We have an algorithm for SSE2->double, and we turn this into a<br>
// 64-bit FILD followed by conditional FADD for other targets.<br>
setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom);<br>
@@ -197,7 +197,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);<br>
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);<br>
<br>
- if (!TM.Options.UseSoftFloat) {<br>
+ if (!Subtarget->useSoftFloat()) {<br>
// SSE has no i16 to fp conversion, only i32<br>
if (X86ScalarSSEf32) {<br>
setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote);<br>
@@ -240,7 +240,7 @@ X86TargetLowering::X86TargetLowering(con<br>
if (Subtarget->is64Bit()) {<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);<br>
setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);<br>
- } else if (!TM.Options.UseSoftFloat) {<br>
+ } else if (!Subtarget->useSoftFloat()) {<br>
// Since AVX is a superset of SSE3, only check for SSE here.<br>
if (Subtarget->hasSSE1() && !Subtarget->hasSSE3())<br>
// Expand FP_TO_UINT into a select.<br>
@@ -368,7 +368,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// Special handling for half-precision floating point conversions.<br>
// If we don't have F16C support, then lower half float conversions<br>
// into library calls.<br>
- if (TM.Options.UseSoftFloat || !Subtarget->hasF16C()) {<br>
+ if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) {<br>
setOperationAction(ISD::FP16_TO_FP, MVT::f32, Expand);<br>
setOperationAction(ISD::FP_TO_FP16, MVT::f32, Expand);<br>
}<br>
@@ -517,7 +517,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::GC_TRANSITION_START, MVT::Other, Custom);<br>
setOperationAction(ISD::GC_TRANSITION_END, MVT::Other, Custom);<br>
<br>
- if (!TM.Options.UseSoftFloat && X86ScalarSSEf64) {<br>
+ if (!Subtarget->useSoftFloat() && X86ScalarSSEf64) {<br>
// f32 and f64 use SSE.<br>
// Set up the FP register classes.<br>
addRegisterClass(MVT::f32, &X86::FR32RegClass);<br>
@@ -551,7 +551,7 @@ X86TargetLowering::X86TargetLowering(con<br>
// cases we handle.<br>
addLegalFPImmediate(APFloat(+0.0)); // xorpd<br>
addLegalFPImmediate(APFloat(+0.0f)); // xorps<br>
- } else if (!TM.Options.UseSoftFloat && X86ScalarSSEf32) {<br>
+ } else if (!Subtarget->useSoftFloat() && X86ScalarSSEf32) {<br>
// Use SSE for f32, x87 for f64.<br>
// Set up the FP register classes.<br>
addRegisterClass(MVT::f32, &X86::FR32RegClass);<br>
@@ -586,7 +586,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FCOS , MVT::f64, Expand);<br>
setOperationAction(ISD::FSINCOS, MVT::f64, Expand);<br>
}<br>
- } else if (!TM.Options.UseSoftFloat) {<br>
+ } else if (!Subtarget->useSoftFloat()) {<br>
// f32 and f64 in x87.<br>
// Set up the FP register classes.<br>
addRegisterClass(MVT::f64, &X86::RFP64RegClass);<br>
@@ -620,7 +620,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::FMA, MVT::f32, Expand);<br>
<br>
// Long double always uses X87.<br>
- if (!TM.Options.UseSoftFloat) {<br>
+ if (!Subtarget->useSoftFloat()) {<br>
addRegisterClass(MVT::f80, &X86::RFP80RegClass);<br>
setOperationAction(ISD::UNDEF, MVT::f80, Expand);<br>
setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand);<br>
@@ -760,7 +760,7 @@ X86TargetLowering::X86TargetLowering(con<br>
<br>
// FIXME: In order to prevent SSE instructions being expanded to MMX ones<br>
// with -msoft-float, disable use of MMX as well.<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasMMX()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasMMX()) {<br>
addRegisterClass(MVT::x86mmx, &X86::VR64RegClass);<br>
// No operations on x86mmx supported, everything uses intrinsics.<br>
}<br>
@@ -778,7 +778,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand);<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasSSE1()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasSSE1()) {<br>
addRegisterClass(MVT::v4f32, &X86::VR128RegClass);<br>
<br>
setOperationAction(ISD::FADD, MVT::v4f32, Legal);<br>
@@ -797,7 +797,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Custom);<br>
}<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasSSE2()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasSSE2()) {<br>
addRegisterClass(MVT::v2f64, &X86::VR128RegClass);<br>
<br>
// FIXME: Unfortunately, -soft-float and -no-implicit-float mean XMM<br>
@@ -942,7 +942,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::BITCAST, MVT::v8i8, Custom);<br>
}<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasSSE41()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasSSE41()) {<br>
for (MVT RoundedTy : {MVT::f32, MVT::f64, MVT::v4f32, MVT::v2f64}) {<br>
setOperationAction(ISD::FFLOOR, RoundedTy, Legal);<br>
setOperationAction(ISD::FCEIL, RoundedTy, Legal);<br>
@@ -1024,7 +1024,7 @@ X86TargetLowering::X86TargetLowering(con<br>
setOperationAction(ISD::SRA, MVT::v4i32, Custom);<br>
}<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasFp256()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasFp256()) {<br>
addRegisterClass(MVT::v32i8, &X86::VR256RegClass);<br>
addRegisterClass(MVT::v16i16, &X86::VR256RegClass);<br>
addRegisterClass(MVT::v8i32, &X86::VR256RegClass);<br>
@@ -1244,7 +1244,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasAVX512()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasAVX512()) {<br>
addRegisterClass(MVT::v16i32, &X86::VR512RegClass);<br>
addRegisterClass(MVT::v16f32, &X86::VR512RegClass);<br>
addRegisterClass(MVT::v8i64, &X86::VR512RegClass);<br>
@@ -1447,7 +1447,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}// has AVX-512<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasBWI()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasBWI()) {<br>
addRegisterClass(MVT::v32i16, &X86::VR512RegClass);<br>
addRegisterClass(MVT::v64i8, &X86::VR512RegClass);<br>
<br>
@@ -1484,7 +1484,7 @@ X86TargetLowering::X86TargetLowering(con<br>
}<br>
}<br>
<br>
- if (!TM.Options.UseSoftFloat && Subtarget->hasVLX()) {<br>
+ if (!Subtarget->useSoftFloat() && Subtarget->hasVLX()) {<br>
addRegisterClass(MVT::v4i1, &X86::VK4RegClass);<br>
addRegisterClass(MVT::v2i1, &X86::VK2RegClass);<br>
<br>
@@ -1789,6 +1789,10 @@ unsigned X86TargetLowering::getJumpTable<br>
return TargetLowering::getJumpTableEncoding();<br>
}<br>
<br>
+bool X86TargetLowering::useSoftFloat() const {<br>
+ return Subtarget->useSoftFloat();<br>
+}<br>
+<br>
const MCExpr *<br>
X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,<br>
const MachineBasicBlock *MBB,<br>
@@ -2294,7 +2298,7 @@ static ArrayRef<MCPhysReg> get64BitArgum<br>
<br>
const Function *Fn = MF.getFunction();<br>
bool NoImplicitFloatOps = Fn->hasFnAttribute(Attribute::NoImplicitFloat);<br>
- bool isSoftFloat = MF.getTarget().Options.UseSoftFloat;<br>
+ bool isSoftFloat = Subtarget->useSoftFloat();<br>
assert(!(isSoftFloat && NoImplicitFloatOps) &&<br>
"SSE register cannot be used when SSE is disabled!");<br>
if (isSoftFloat || NoImplicitFloatOps || !Subtarget->hasSSE1())<br>
@@ -2468,7 +2472,7 @@ X86TargetLowering::LowerFormalArguments(<br>
bool IsWinEHParent = WinEHParent && WinEHParent == Fn;<br>
<br>
// Figure out if XMM registers are in use.<br>
- assert(!(MF.getTarget().Options.UseSoftFloat &&<br>
+ assert(!(Subtarget->useSoftFloat() &&<br>
Fn->hasFnAttribute(Attribute::NoImplicitFloat)) &&<br>
"SSE register cannot be used when SSE is disabled!");<br>
<br>
@@ -14600,7 +14604,7 @@ SDValue X86TargetLowering::LowerVAARG(SD<br>
<br>
if (ArgMode == 2) {<br>
// Sanity Check: Make sure using fp_offset makes sense.<br>
- assert(!DAG.getTarget().Options.UseSoftFloat &&<br>
+ assert(!Subtarget->useSoftFloat() &&<br>
!(DAG.getMachineFunction().getFunction()->hasFnAttribute(<br>
Attribute::NoImplicitFloat)) &&<br>
Subtarget->hasSSE1());<br>
@@ -23203,8 +23207,8 @@ static SDValue PerformSTORECombine(SDNod<br>
<br>
const Function *F = DAG.getMachineFunction().getFunction();<br>
bool NoImplicitFloatOps = F->hasFnAttribute(Attribute::NoImplicitFloat);<br>
- bool F64IsLegal = !DAG.getTarget().Options.UseSoftFloat && !NoImplicitFloatOps<br>
- && Subtarget->hasSSE2();<br>
+ bool F64IsLegal =<br>
+ !Subtarget->useSoftFloat() && !NoImplicitFloatOps && Subtarget->hasSSE2();<br>
if ((VT.isVector() ||<br>
(VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) &&<br>
isa<LoadSDNode>(St->getValue()) &&<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon May 11 20:26:05 2015<br>
@@ -572,6 +572,7 @@ namespace llvm {<br>
const X86Subtarget &STI);<br>
<br>
unsigned getJumpTableEncoding() const override;<br>
+ bool useSoftFloat() const override;<br>
<br>
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Mon May 11 20:26:05 2015<br>
@@ -278,6 +278,7 @@ void X86Subtarget::initializeEnvironment<br>
stackAlignment = 4;<br>
// FIXME: this is a known good value for Yonah. How about others?<br>
MaxInlineSizeThreshold = 128;<br>
+ UseSoftFloat = false;<br>
}<br>
<br>
X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Mon May 11 20:26:05 2015<br>
@@ -218,6 +218,9 @@ protected:<br>
/// Processor has AVX-512 Vector Length eXtenstions<br>
bool HasVLX;<br>
<br>
+ /// Use software floating point for code generation.<br>
+ bool UseSoftFloat;<br>
+<br>
/// The minimum alignment known to hold of the stack frame on<br>
/// entry to the function and which must be maintained by every function.<br>
unsigned stackAlignment;<br>
@@ -385,6 +388,7 @@ public:<br>
<br>
bool isAtom() const { return X86ProcFamily == IntelAtom; }<br>
bool isSLM() const { return X86ProcFamily == IntelSLM; }<br>
+ bool useSoftFloat() const { return UseSoftFloat; }<br>
<br>
const Triple &getTargetTriple() const { return TargetTriple; }<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon May 11 20:26:05 2015<br>
@@ -131,13 +131,15 @@ X86TargetMachine::getSubtargetImpl(const<br>
// function before we can generate a subtarget. We also need to use<br>
// it as a key for the subtarget since that can be the only difference<br>
// between two functions.<br>
- Attribute SFAttr = F.getFnAttribute("use-soft-float");<br>
- bool SoftFloat = !SFAttr.hasAttribute(Attribute::None)<br>
- ? SFAttr.getValueAsString() == "true"<br>
- : Options.UseSoftFloat;<br>
+ bool SoftFloat =<br>
+ F.hasFnAttribute("use-soft-float") &&<br>
+ F.getFnAttribute("use-soft-float").getValueAsString() == "true";<br>
+ // If the soft float attribute is set on the function turn on the soft float<br>
+ // subtarget feature.<br>
+ if (SoftFloat)<br>
+ FS += FS.empty() ? "+soft-float" : ",+soft-float";<br>
<br>
- auto &I = SubtargetMap[CPU + FS + (SoftFloat ? "use-soft-float=true"<br>
- : "use-soft-float=false")];<br>
+ auto &I = SubtargetMap[CPU + FS];<br>
if (!I) {<br>
// This needs to be done before we create a new subtarget since any<br>
// creation will depend on the TM and the code generation flags on the<br>
<br>
Modified: llvm/trunk/test/CodeGen/ARM/vfp-libcalls.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vfp-libcalls.ll?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vfp-libcalls.ll?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/ARM/vfp-libcalls.ll (original)<br>
+++ llvm/trunk/test/CodeGen/ARM/vfp-libcalls.ll Mon May 11 20:26:05 2015<br>
@@ -1,6 +1,6 @@<br>
; RUN: llc -mtriple=armv6-apple-ios -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-HARD<br>
; RUN: llc -mtriple=thumbv6-apple-ios -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFTISH<br>
-; RUN: llc -mtriple=armv7s-apple-ios -soft-float -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFT<br>
+; RUN: llc -mtriple=armv7s-apple-ios -mattr=+soft-float -mcpu=arm1136jf-s -o - %s | FileCheck %s --check-prefix=CHECK-SOFT<br>
<br>
define float @test_call(float %a, float %b) {<br>
; CHECK-HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}<br>
@@ -8,4 +8,4 @@ define float @test_call(float %a, float<br>
; CHECK-SOFT: bl ___addsf3{{$}}<br>
%sum = fadd float %a, %b<br>
ret float %sum<br>
-}<br>
\ No newline at end of file<br>
+}<br>
<br>
Modified: llvm/trunk/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Generic/2009-03-29-SoftFloatVectorExtract.ll Mon May 11 20:26:05 2015<br>
@@ -1,10 +1,14 @@<br>
-; RUN: llc < %s -soft-float<br>
+; RUN: llc < %s<br>
; PR3899<br>
<br>
@m = external global <2 x double><br>
<br>
-define double @vector_ex() nounwind {<br>
+define double @vector_ex() nounwind #0 {<br>
%v = load <2 x double>, <2 x double>* @m<br>
%x = extractelement <2 x double> %v, i32 1<br>
ret double %x<br>
}<br>
+<br>
+; Soft-float attribute so that targets that pay attention to soft float will<br>
+; make floating point types illegal and we'll exercise the legalizer code.<br>
+attributes #0 = { "use-soft-float" = "true" }<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/cvt16.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cvt16.ll?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/cvt16.ll?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/cvt16.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/cvt16.ll Mon May 11 20:26:05 2015<br>
@@ -1,7 +1,7 @@<br>
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c | FileCheck %s -check-prefix=CHECK -check-prefix=LIBCALL<br>
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c | FileCheck %s -check-prefix=CHECK -check-prefix=F16C<br>
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -soft-float=1 -mattr=-f16c | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT<br>
-; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -soft-float=1 -mattr=+f16c | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT<br>
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=-f16c,+soft-float | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT<br>
+; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -mattr=+f16c,+soft-float | FileCheck %s -check-prefix=CHECK -check-prefix=SOFTFLOAT<br>
<br>
; This is a test for float to half float conversions on x86-64.<br>
;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/floor-soft-float.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/floor-soft-float.ll?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/floor-soft-float.ll?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/floor-soft-float.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/floor-soft-float.ll Mon May 11 20:26:05 2015<br>
@@ -1,5 +1,5 @@<br>
-; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx -soft-float=0 | FileCheck %s --check-prefix=CHECK-HARD-FLOAT<br>
-; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx -soft-float=1 | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT<br>
+; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx | FileCheck %s --check-prefix=CHECK-HARD-FLOAT<br>
+; RUN: llc < %s -march=x86-64 -mattr=+sse4.1,-avx,+soft-float | FileCheck %s --check-prefix=CHECK-SOFT-FLOAT<br>
<br>
target triple = "x86_64-unknown-linux-gnu"<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/soft-fp.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/soft-fp.ll?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/soft-fp.ll?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/soft-fp.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/soft-fp.ll Mon May 11 20:26:05 2015<br>
@@ -1,5 +1,5 @@<br>
-; RUN: llc < %s -march=x86 -mattr=+sse2 -soft-float | FileCheck %s<br>
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 -soft-float | FileCheck %s<br>
+; RUN: llc < %s -march=x86 -mattr=+sse2,+soft-float | FileCheck %s<br>
+; RUN: llc < %s -march=x86-64 -mattr=+sse2,+soft-float | FileCheck %s<br>
<br>
; CHECK-NOT: xmm{[0-9]+}<br>
<br>
<br>
Modified: llvm/trunk/tools/llc/llc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/llc/llc.cpp (original)<br>
+++ llvm/trunk/tools/llc/llc.cpp Mon May 11 20:26:05 2015<br>
@@ -281,9 +281,8 @@ static int compileModule(char **argv, LL<br>
return 0;<br>
<br>
assert(M && "Should have exited if we didn't have a module!");<br>
-<br>
- if (GenerateSoftFloatCalls)<br>
- FloatABIForCalls = FloatABI::Soft;<br>
+ if (FloatABIForCalls != FloatABI::Default)<br>
+ Options.FloatABIType = FloatABIForCalls;<br>
<br>
// Figure out where we are going to send the output.<br>
std::unique_ptr<tool_output_file> Out =<br>
<br>
Modified: llvm/trunk/tools/lli/lli.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=237079&r1=237078&r2=237079&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lli/lli.cpp?rev=237079&r1=237078&r2=237079&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/tools/lli/lli.cpp (original)<br>
+++ llvm/trunk/tools/lli/lli.cpp Mon May 11 20:26:05 2015<br>
@@ -465,11 +465,8 @@ int main(int argc, char **argv, char * c<br>
builder.setOptLevel(OLvl);<br>
<br>
TargetOptions Options;<br>
- Options.UseSoftFloat = GenerateSoftFloatCalls;<br>
if (FloatABIForCalls != FloatABI::Default)<br>
Options.FloatABIType = FloatABIForCalls;<br>
- if (GenerateSoftFloatCalls)<br>
- FloatABIForCalls = FloatABI::Soft;<br>
<br>
builder.setTargetOptions(Options);<br>
<br>
<br>
<br>
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