<div dir="ltr">Hi Sam,<br><br>Thanks for working on this! This has been a running sore in ARM vectorization for a long time now.<div><br></div><div>Initial comments:</div><div> * In the future, could you please use Phabricator (<a href="http://reviews.llvm.org">http://reviews.llvm.org</a>) to upload patches to; it makes it much easier to review.</div><div> * There are no regression tests included in this patch - did you forget to git add them?</div><div> * I'm not sure the logic is totally sound. Consider this:</div><div><br></div><div>loop:</div><div> %1 = load i8* %foo</div><div> %2 = zext i8 %1 to i32</div><div> %3 = add i32 %2, 42</div><div> %4 = trunc i32 %3 to i16</div><div> %5 = add i16 %4, 42</div><div> store i16* %5, %bar</div><div> br loop</div><div><br></div><div>getWidestType() will return i16. So the first cast is not free, but neither is it a cast to i32, it's a cast to i16.</div><div><br></div><div>I'm not exactly sure what Elena's query was; it looks like the implementation here should be architecture-agnostic as it's just modelling changes to the IR (truncate nodes disappear) and the rest is the TTI's responsibility.</div><div><br></div><div>Cheers,</div><div><br></div><div>James</div></div><br><div class="gmail_quote">On Mon, 11 May 2015 at 12:17 Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com">elena.demikhovsky@intel.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
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<p class="MsoNormal"><span style="color:#1f497d">+ if (Opcode == Instruction::Trunc) {<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d">+ if (TTI->isTypeLegal(DstVecTy)) {<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d">+ VecCost = 0;<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d">+ }<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d">On AVX-512 the “truncate” is usually one instruction, the VecCost should be 1.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d">On AVX the type may be legal, but “truncate” is more than one instruction.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="color:#1f497d"><u></u> <u></u></span></p>
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<p class="MsoNormal" style="margin-left:36.0pt">
<u></u><span style="font-size:12.0pt;color:#31849b"><span>-<span style="font:7.0pt "Times New Roman"">
</span></span></span><u></u><span dir="LTR"></span><b><i><span style="font-size:12.0pt;font-family:"Times New Roman","serif";color:#31849b"> Elena<u></u><u></u></span></i></b></p>
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<p class="MsoNormal"><span style="color:#1f497d"><u></u> <u></u></span></p>
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<div style="border:none;border-top:solid #b5c4df 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> <a href="mailto:llvm-commits-bounces@cs.uiuc.edu" target="_blank">llvm-commits-bounces@cs.uiuc.edu</a> [mailto:<a href="mailto:llvm-commits-bounces@cs.uiuc.edu" target="_blank">llvm-commits-bounces@cs.uiuc.edu</a>]
<b>On Behalf Of </b>Sam Parker<br>
<b>Sent:</b> Monday, May 11, 2015 13:57<br>
<b>To:</b> <a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
<b>Subject:</b> [PATCH] improve vectorizers by removing cost of unnecessary truncs and exts.<u></u><u></u></span></p>
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<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Hi,<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">I’ve attached a patch to both the loop vectorizer and slp-vectorizer which checks to see whether truncs and extensions would actually be required if the code was vectorized. This is so that the vectorizers understand that the cost of these
instructions is effectively zero if vectorization happens. This is helpful when working on smaller data types, such as i8 and i16, that do not have native support in general purpose registers, but are supported in vector register files.<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal">Regards,<u></u><u></u></p>
<p class="MsoNormal">Sam<u></u><u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
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