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<p class="MsoNormal"><span style="color:#1F497D">+ if (Opcode == Instruction::Trunc) {<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">+ if (TTI->isTypeLegal(DstVecTy)) {<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">+ VecCost = 0;<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">+ }<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">On AVX-512 the “truncate” is usually one instruction, the VecCost should be 1.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D">On AVX the type may be legal, but “truncate” is more than one instruction.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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</span></span></span><![endif]><span dir="LTR"></span><b><i><span style="font-size:12.0pt;font-family:"Times New Roman","serif";color:#31849B"> Elena<o:p></o:p></span></i></b></p>
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<p class="MsoNormal"><span style="color:#1F497D"><o:p> </o:p></span></p>
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<div style="border:none;border-top:solid #B5C4DF 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> llvm-commits-bounces@cs.uiuc.edu [mailto:llvm-commits-bounces@cs.uiuc.edu]
<b>On Behalf Of </b>Sam Parker<br>
<b>Sent:</b> Monday, May 11, 2015 13:57<br>
<b>To:</b> llvm-commits@cs.uiuc.edu<br>
<b>Subject:</b> [PATCH] improve vectorizers by removing cost of unnecessary truncs and exts.<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Hi,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I’ve attached a patch to both the loop vectorizer and slp-vectorizer which checks to see whether truncs and extensions would actually be required if the code was vectorized. This is so that the vectorizers understand that the cost of these
instructions is effectively zero if vectorization happens. This is helpful when working on smaller data types, such as i8 and i16, that do not have native support in general purpose registers, but are supported in vector register files.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Regards,<o:p></o:p></p>
<p class="MsoNormal">Sam<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
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