<div dir="ltr">Reverted in r235987.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Apr 28, 2015 at 3:28 PM, Daniel Jasper <span dir="ltr"><<a href="mailto:djasper@google.com" target="_blank">djasper@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">This breaks test/DebugInfo/constant-sdnodes-have-dbg-location.ll (<a href="http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870" target="_blank">http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870</a>). Do you have a quick fix? Otherwise I'll roll this back.</div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Apr 28, 2015 at 1:56 PM, Sergey Dmitrouk <span dir="ltr"><<a href="mailto:sdmitrouk@accesssoftek.com" target="_blank">sdmitrouk@accesssoftek.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp Tue Apr 28 06:56:37 2015<br>
@@ -131,7 +131,7 @@ class SystemZDAGToDAGISel : public Selec<br>
<br>
// Used by SystemZOperands.td to create integer constants.<br>
inline SDValue getImm(const SDNode *Node, uint64_t Imm) const {<br>
- return CurDAG->getTargetConstant(Imm, Node->getValueType(0));<br>
+ return CurDAG->getTargetConstant(Imm, SDLoc(Node), Node->getValueType(0));<br>
}<br>
<br>
const SystemZTargetMachine &getTargetMachine() const {<br>
@@ -596,7 +596,7 @@ void SystemZDAGToDAGISel::getAddressOper<br>
}<br>
<br>
// Lower the displacement to a TargetConstant.<br>
- Disp = CurDAG->getTargetConstant(AM.Disp, VT);<br>
+ Disp = CurDAG->getTargetConstant(AM.Disp, SDLoc(Base), VT);<br>
}<br>
<br>
void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,<br>
@@ -864,6 +864,7 @@ SDValue SystemZDAGToDAGISel::convertTo(S<br>
}<br>
<br>
SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {<br>
+ SDLoc DL(N);<br>
EVT VT = N->getValueType(0);<br>
RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));<br>
unsigned Count = 0;<br>
@@ -889,7 +890,7 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZer<br>
// Force the new mask into the DAG, since it may include known-one bits.<br>
auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());<br>
if (MaskN->getZExtValue() != RISBG.Mask) {<br>
- SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);<br>
+ SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT);<br>
N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);<br>
return SelectCode(N);<br>
}<br>
@@ -909,14 +910,14 @@ SDNode *SystemZDAGToDAGISel::tryRISBGZer<br>
RISBG.End &= 31;<br>
}<br>
SDValue Ops[5] = {<br>
- getUNDEF(SDLoc(N), OpcodeVT),<br>
- convertTo(SDLoc(N), OpcodeVT, RISBG.Input),<br>
- CurDAG->getTargetConstant(RISBG.Start, MVT::i32),<br>
- CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),<br>
- CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)<br>
+ getUNDEF(DL, OpcodeVT),<br>
+ convertTo(DL, OpcodeVT, RISBG.Input),<br>
+ CurDAG->getTargetConstant(RISBG.Start, DL, MVT::i32),<br>
+ CurDAG->getTargetConstant(RISBG.End | 128, DL, MVT::i32),<br>
+ CurDAG->getTargetConstant(RISBG.Rotate, DL, MVT::i32)<br>
};<br>
- N = CurDAG->getMachineNode(Opcode, SDLoc(N), OpcodeVT, Ops);<br>
- return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();<br>
+ N = CurDAG->getMachineNode(Opcode, DL, OpcodeVT, Ops);<br>
+ return convertTo(DL, VT, SDValue(N, 0)).getNode();<br>
}<br>
<br>
SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {<br>
@@ -955,16 +956,17 @@ SDNode *SystemZDAGToDAGISel::tryRxSBG(SD<br>
Opcode = SystemZ::RISBGN;<br>
}<br>
<br>
+ SDLoc DL(N);<br>
EVT VT = N->getValueType(0);<br>
SDValue Ops[5] = {<br>
- convertTo(SDLoc(N), MVT::i64, Op0),<br>
- convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),<br>
- CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),<br>
- CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),<br>
- CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)<br>
+ convertTo(DL, MVT::i64, Op0),<br>
+ convertTo(DL, MVT::i64, RxSBG[I].Input),<br>
+ CurDAG->getTargetConstant(RxSBG[I].Start, DL, MVT::i32),<br>
+ CurDAG->getTargetConstant(RxSBG[I].End, DL, MVT::i32),<br>
+ CurDAG->getTargetConstant(RxSBG[I].Rotate, DL, MVT::i32)<br>
};<br>
- N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);<br>
- return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();<br>
+ N = CurDAG->getMachineNode(Opcode, DL, MVT::i64, Ops);<br>
+ return convertTo(DL, VT, SDValue(N, 0)).getNode();<br>
}<br>
<br>
SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,<br>
@@ -972,12 +974,12 @@ SDNode *SystemZDAGToDAGISel::splitLargeI<br>
uint64_t LowerVal) {<br>
EVT VT = Node->getValueType(0);<br>
SDLoc DL(Node);<br>
- SDValue Upper = CurDAG->getConstant(UpperVal, VT);<br>
+ SDValue Upper = CurDAG->getConstant(UpperVal, DL, VT);<br>
if (Op0.getNode())<br>
Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);<br>
Upper = SDValue(Select(Upper.getNode()), 0);<br>
<br>
- SDValue Lower = CurDAG->getConstant(LowerVal, VT);<br>
+ SDValue Lower = CurDAG->getConstant(LowerVal, DL, VT);<br>
SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);<br>
return Or.getNode();<br>
}<br>
@@ -1111,7 +1113,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDNo<br>
uint64_t ConstCCMask =<br>
cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();<br>
// Invert the condition.<br>
- CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask,<br>
+ CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, SDLoc(Node),<br>
CCMask.getValueType());<br>
SDValue Op4 = Node->getOperand(4);<br>
Node = CurDAG->UpdateNodeOperands(Node, Op1, Op0, CCValid, CCMask, Op4);<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Tue Apr 28 06:56:37 2015<br>
@@ -591,35 +591,35 @@ LowerAsmOperandForConstraint(SDValue Op,<br>
case 'I': // Unsigned 8-bit constant<br>
if (auto *C = dyn_cast<ConstantSDNode>(Op))<br>
if (isUInt<8>(C->getZExtValue()))<br>
- Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),<br>
+ Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
Op.getValueType()));<br>
return;<br>
<br>
case 'J': // Unsigned 12-bit constant<br>
if (auto *C = dyn_cast<ConstantSDNode>(Op))<br>
if (isUInt<12>(C->getZExtValue()))<br>
- Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),<br>
+ Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
Op.getValueType()));<br>
return;<br>
<br>
case 'K': // Signed 16-bit constant<br>
if (auto *C = dyn_cast<ConstantSDNode>(Op))<br>
if (isInt<16>(C->getSExtValue()))<br>
- Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),<br>
+ Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),<br>
Op.getValueType()));<br>
return;<br>
<br>
case 'L': // Signed 20-bit displacement (on all targets we support)<br>
if (auto *C = dyn_cast<ConstantSDNode>(Op))<br>
if (isInt<20>(C->getSExtValue()))<br>
- Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),<br>
+ Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),<br>
Op.getValueType()));<br>
return;<br>
<br>
case 'M': // 0x7fffffff<br>
if (auto *C = dyn_cast<ConstantSDNode>(Op))<br>
if (C->getZExtValue() == 0x7fffffff)<br>
- Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),<br>
+ Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
Op.getValueType()));<br>
return;<br>
}<br>
@@ -753,7 +753,8 @@ LowerFormalArguments(SDValue Chain, Call<br>
EVT PtrVT = getPointerTy();<br>
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);<br>
if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)<br>
- FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));<br>
+ FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,<br>
+ DAG.getIntPtrConstant(4, DL));<br>
ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,<br>
MachinePointerInfo::getFixedStack(FI),<br>
false, false, false, 0);<br>
@@ -854,7 +855,8 @@ SystemZTargetLowering::LowerCall(CallLow<br>
<br>
// Mark the start of the call.<br>
if (!IsTailCall)<br>
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),<br>
+ Chain = DAG.getCALLSEQ_START(Chain,<br>
+ DAG.getConstant(NumBytes, DL, PtrVT, true),<br>
DL);<br>
<br>
// Copy argument values to their designated locations.<br>
@@ -890,7 +892,7 @@ SystemZTargetLowering::LowerCall(CallLow<br>
if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)<br>
Offset += 4;<br>
SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,<br>
- DAG.getIntPtrConstant(Offset));<br>
+ DAG.getIntPtrConstant(Offset, DL));<br>
<br>
// Emit the store.<br>
MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,<br>
@@ -956,8 +958,8 @@ SystemZTargetLowering::LowerCall(CallLow<br>
<br>
// Mark the end of the call, which is glued to the call itself.<br>
Chain = DAG.getCALLSEQ_END(Chain,<br>
- DAG.getConstant(NumBytes, PtrVT, true),<br>
- DAG.getConstant(0, PtrVT, true),<br>
+ DAG.getConstant(NumBytes, DL, PtrVT, true),<br>
+ DAG.getConstant(0, DL, PtrVT, true),<br>
Glue, DL);<br>
Glue = Chain.getValue(1);<br>
<br>
@@ -1179,7 +1181,7 @@ static IPMConversion getIPMConversion(un<br>
<br>
// If C can be converted to a comparison against zero, adjust the operands<br>
// as necessary.<br>
-static void adjustZeroCmp(SelectionDAG &DAG, Comparison &C) {<br>
+static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {<br>
if (C.ICmpType == SystemZICMP::UnsignedOnly)<br>
return;<br>
<br>
@@ -1193,13 +1195,13 @@ static void adjustZeroCmp(SelectionDAG &<br>
(Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||<br>
(Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {<br>
C.CCMask ^= SystemZ::CCMASK_CMP_EQ;<br>
- C.Op1 = DAG.getConstant(0, C.Op1.getValueType());<br>
+ C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());<br>
}<br>
}<br>
<br>
// If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,<br>
// adjust the operands as necessary.<br>
-static void adjustSubwordCmp(SelectionDAG &DAG, Comparison &C) {<br>
+static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {<br>
// For us to make any changes, it must a comparison between a single-use<br>
// load and a constant.<br>
if (!C.Op0.hasOneUse() ||<br>
@@ -1264,7 +1266,7 @@ static void adjustSubwordCmp(SelectionDA<br>
// Make sure that the second operand is an i32 with the right value.<br>
if (C.Op1.getValueType() != MVT::i32 ||<br>
Value != ConstOp1->getZExtValue())<br>
- C.Op1 = DAG.getConstant(Value, MVT::i32);<br>
+ C.Op1 = DAG.getConstant(Value, DL, MVT::i32);<br>
}<br>
<br>
// Return true if Op is either an unextended load, or a load suitable<br>
@@ -1360,7 +1362,7 @@ static unsigned reverseCCMask(unsigned C<br>
// Check whether C tests for equality between X and Y and whether X - Y<br>
// or Y - X is also computed. In that case it's better to compare the<br>
// result of the subtraction against zero.<br>
-static void adjustForSubtraction(SelectionDAG &DAG, Comparison &C) {<br>
+static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C) {<br>
if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||<br>
C.CCMask == SystemZ::CCMASK_CMP_NE) {<br>
for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {<br>
@@ -1369,7 +1371,7 @@ static void adjustForSubtraction(Selecti<br>
((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||<br>
(N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {<br>
C.Op0 = SDValue(N, 0);<br>
- C.Op1 = DAG.getConstant(0, N->getValueType(0));<br>
+ C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));<br>
return;<br>
}<br>
}<br>
@@ -1425,7 +1427,7 @@ static void adjustForLTGFR(Comparison &C<br>
// If C compares the truncation of an extending load, try to compare<br>
// the untruncated value instead. This exposes more opportunities to<br>
// reuse CC.<br>
-static void adjustICmpTruncate(SelectionDAG &DAG, Comparison &C) {<br>
+static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C) {<br>
if (C.Op0.getOpcode() == ISD::TRUNCATE &&<br>
C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&<br>
C.Op1.getOpcode() == ISD::Constant &&<br>
@@ -1437,7 +1439,7 @@ static void adjustICmpTruncate(Selection<br>
if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||<br>
(Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {<br>
C.Op0 = C.Op0.getOperand(0);<br>
- C.Op1 = DAG.getConstant(0, C.Op0.getValueType());<br>
+ C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());<br>
}<br>
}<br>
}<br>
@@ -1556,7 +1558,7 @@ static unsigned getTestUnderMaskCond(uns<br>
<br>
// See whether C can be implemented as a TEST UNDER MASK instruction.<br>
// Update the arguments with the TM version if so.<br>
-static void adjustForTestUnderMask(SelectionDAG &DAG, Comparison &C) {<br>
+static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C) {<br>
// Check that we have a comparison with a constant.<br>
auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);<br>
if (!ConstOp1)<br>
@@ -1634,7 +1636,7 @@ static void adjustForTestUnderMask(Selec<br>
if (Mask && Mask->getZExtValue() == MaskVal)<br>
C.Op1 = SDValue(Mask, 0);<br>
else<br>
- C.Op1 = DAG.getConstant(MaskVal, C.Op0.getValueType());<br>
+ C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());<br>
C.CCValid = SystemZ::CCMASK_TM;<br>
C.CCMask = NewCCMask;<br>
}<br>
@@ -1677,7 +1679,7 @@ static Comparison getIntrinsicCmp(Select<br>
<br>
// Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.<br>
static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,<br>
- ISD::CondCode Cond) {<br>
+ ISD::CondCode Cond, SDLoc DL) {<br>
if (CmpOp1.getOpcode() == ISD::Constant) {<br>
uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();<br>
unsigned Opcode, CCValid;<br>
@@ -1709,11 +1711,11 @@ static Comparison getCmp(SelectionDAG &D<br>
else<br>
C.ICmpType = SystemZICMP::SignedOnly;<br>
C.CCMask &= ~SystemZ::CCMASK_CMP_UO;<br>
- adjustZeroCmp(DAG, C);<br>
- adjustSubwordCmp(DAG, C);<br>
- adjustForSubtraction(DAG, C);<br>
+ adjustZeroCmp(DAG, DL, C);<br>
+ adjustSubwordCmp(DAG, DL, C);<br>
+ adjustForSubtraction(DAG, DL, C);<br>
adjustForLTGFR(C);<br>
- adjustICmpTruncate(DAG, C);<br>
+ adjustICmpTruncate(DAG, DL, C);<br>
}<br>
<br>
if (shouldSwapCmpOperands(C)) {<br>
@@ -1721,7 +1723,7 @@ static Comparison getCmp(SelectionDAG &D<br>
C.CCMask = reverseCCMask(C.CCMask);<br>
}<br>
<br>
- adjustForTestUnderMask(DAG, C);<br>
+ adjustForTestUnderMask(DAG, DL, C);<br>
return C;<br>
}<br>
<br>
@@ -1740,12 +1742,12 @@ static SDValue emitCmp(SelectionDAG &DAG<br>
}<br>
if (C.Opcode == SystemZISD::ICMP)<br>
return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,<br>
- DAG.getConstant(C.ICmpType, MVT::i32));<br>
+ DAG.getConstant(C.ICmpType, DL, MVT::i32));<br>
if (C.Opcode == SystemZISD::TM) {<br>
bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=<br>
bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));<br>
return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,<br>
- DAG.getConstant(RegisterOnly, MVT::i32));<br>
+ DAG.getConstant(RegisterOnly, DL, MVT::i32));<br>
}<br>
return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);<br>
}<br>
@@ -1759,7 +1761,8 @@ static void lowerMUL_LOHI32(SelectionDAG<br>
Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);<br>
Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);<br>
SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);<br>
- Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));<br>
+ Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,<br>
+ DAG.getConstant(32, DL, MVT::i64));<br>
Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);<br>
Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);<br>
}<br>
@@ -1791,18 +1794,18 @@ static SDValue emitSETCC(SelectionDAG &D<br>
<br>
if (Conversion.XORValue)<br>
Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,<br>
- DAG.getConstant(Conversion.XORValue, MVT::i32));<br>
+ DAG.getConstant(Conversion.XORValue, DL, MVT::i32));<br>
<br>
if (Conversion.AddValue)<br>
Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,<br>
- DAG.getConstant(Conversion.AddValue, MVT::i32));<br>
+ DAG.getConstant(Conversion.AddValue, DL, MVT::i32));<br>
<br>
// The SHR/AND sequence should get optimized to an RISBG.<br>
Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,<br>
- DAG.getConstant(Conversion.Bit, MVT::i32));<br>
+ DAG.getConstant(Conversion.Bit, DL, MVT::i32));<br>
if (Conversion.Bit != 31)<br>
Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,<br>
- DAG.getConstant(1, MVT::i32));<br>
+ DAG.getConstant(1, DL, MVT::i32));<br>
return Result;<br>
}<br>
<br>
@@ -1813,7 +1816,7 @@ SDValue SystemZTargetLowering::lowerSETC<br>
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();<br>
SDLoc DL(Op);<br>
<br>
- Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));<br>
+ Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));<br>
SDValue Glue = emitCmp(DAG, DL, C);<br>
return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);<br>
}<br>
@@ -1825,11 +1828,11 @@ SDValue SystemZTargetLowering::lowerBR_C<br>
SDValue Dest = Op.getOperand(4);<br>
SDLoc DL(Op);<br>
<br>
- Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));<br>
+ Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));<br>
SDValue Glue = emitCmp(DAG, DL, C);<br>
return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),<br>
- Op.getOperand(0), DAG.getConstant(C.CCValid, MVT::i32),<br>
- DAG.getConstant(C.CCMask, MVT::i32), Dest, Glue);<br>
+ Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),<br>
+ DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);<br>
}<br>
<br>
// Return true if Pos is CmpOp and Neg is the negative of CmpOp,<br>
@@ -1850,7 +1853,7 @@ static SDValue getAbsolute(SelectionDAG<br>
Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);<br>
if (IsNegative)<br>
Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),<br>
- DAG.getConstant(0, Op.getValueType()), Op);<br>
+ DAG.getConstant(0, DL, Op.getValueType()), Op);<br>
return Op;<br>
}<br>
<br>
@@ -1863,7 +1866,7 @@ SDValue SystemZTargetLowering::lowerSELE<br>
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();<br>
SDLoc DL(Op);<br>
<br>
- Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC));<br>
+ Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));<br>
<br>
// Check for absolute and negative-absolute selections, including those<br>
// where the comparison value is sign-extended (for LPGFR and LNGFR).<br>
@@ -1898,14 +1901,14 @@ SDValue SystemZTargetLowering::lowerSELE<br>
if (!is32Bit(VT))<br>
Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);<br>
// Sign-extend from the low bit.<br>
- SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);<br>
+ SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32);<br>
SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);<br>
return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);<br>
}<br>
}<br>
<br>
- SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, MVT::i32),<br>
- DAG.getConstant(C.CCMask, MVT::i32), Glue};<br>
+ SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),<br>
+ DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};<br>
<br>
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);<br>
return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);<br>
@@ -1945,7 +1948,7 @@ SDValue SystemZTargetLowering::lowerGlob<br>
// addition for it.<br>
if (Offset != 0)<br>
Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,<br>
- DAG.getConstant(Offset, PtrVT));<br>
+ DAG.getConstant(Offset, DL, PtrVT));<br>
<br>
return Result;<br>
}<br>
@@ -2006,17 +2009,17 @@ SDValue SystemZTargetLowering::lowerGlob<br>
<br>
// The high part of the thread pointer is in access register 0.<br>
SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,<br>
- DAG.getConstant(0, MVT::i32));<br>
+ DAG.getConstant(0, DL, MVT::i32));<br>
TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);<br>
<br>
// The low part of the thread pointer is in access register 1.<br>
SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,<br>
- DAG.getConstant(1, MVT::i32));<br>
+ DAG.getConstant(1, DL, MVT::i32));<br>
TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);<br>
<br>
// Merge them into a single 64-bit address.<br>
SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,<br>
- DAG.getConstant(32, PtrVT));<br>
+ DAG.getConstant(32, DL, PtrVT));<br>
SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);<br>
<br>
// Get the offset of GA from the thread pointer, based on the TLS model.<br>
@@ -2153,7 +2156,7 @@ SDValue SystemZTargetLowering::lowerBITC<br>
} else {<br>
In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);<br>
In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,<br>
- DAG.getConstant(32, MVT::i64));<br>
+ DAG.getConstant(32, DL, MVT::i64));<br>
}<br>
SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);<br>
return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,<br>
@@ -2168,7 +2171,7 @@ SDValue SystemZTargetLowering::lowerBITC<br>
return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,<br>
MVT::i32, Out64);<br>
SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,<br>
- DAG.getConstant(32, MVT::i64));<br>
+ DAG.getConstant(32, DL, MVT::i64));<br>
return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);<br>
}<br>
llvm_unreachable("Unexpected bitcast combination");<br>
@@ -2189,8 +2192,8 @@ SDValue SystemZTargetLowering::lowerVAST<br>
// The initial values of each field.<br>
const unsigned NumFields = 4;<br>
SDValue Fields[NumFields] = {<br>
- DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),<br>
- DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),<br>
+ DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),<br>
+ DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),<br>
DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),<br>
DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)<br>
};<br>
@@ -2202,7 +2205,7 @@ SDValue SystemZTargetLowering::lowerVAST<br>
SDValue FieldAddr = Addr;<br>
if (Offset != 0)<br>
FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,<br>
- DAG.getIntPtrConstant(Offset));<br>
+ DAG.getIntPtrConstant(Offset, DL));<br>
MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,<br>
MachinePointerInfo(SV, Offset),<br>
false, false, 0);<br>
@@ -2220,7 +2223,7 @@ SDValue SystemZTargetLowering::lowerVACO<br>
const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();<br>
SDLoc DL(Op);<br>
<br>
- return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),<br>
+ return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),<br>
/*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,<br>
/*isTailCall*/false,<br>
MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));<br>
@@ -2277,7 +2280,7 @@ SDValue SystemZTargetLowering::lowerSMUL<br>
// multiplication:<br>
//<br>
// (ll * rl) - (((lh & rl) + (ll & rh)) << 64)<br>
- SDValue C63 = DAG.getConstant(63, MVT::i64);<br>
+ SDValue C63 = DAG.getConstant(63, DL, MVT::i64);<br>
SDValue LL = Op.getOperand(0);<br>
SDValue RL = Op.getOperand(1);<br>
SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);<br>
@@ -2427,7 +2430,7 @@ SDValue SystemZTargetLowering::lowerCTPO<br>
DAG.computeKnownBits(Op, KnownZero, KnownOne);<br>
unsigned NumSignificantBits = (~KnownZero).getActiveBits();<br>
if (NumSignificantBits == 0)<br>
- return DAG.getConstant(0, VT);<br>
+ return DAG.getConstant(0, DL, VT);<br>
<br>
// Skip known-zero high parts of the operand.<br>
int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);<br>
@@ -2441,16 +2444,17 @@ SDValue SystemZTargetLowering::lowerCTPO<br>
// Add up per-byte counts in a binary tree. All bits of Op at<br>
// position larger than BitSize remain zero throughout.<br>
for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {<br>
- SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, VT));<br>
+ SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));<br>
if (BitSize != OrigBitSize)<br>
Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,<br>
- DAG.getConstant(((uint64_t)1 << BitSize) - 1, VT));<br>
+ DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));<br>
Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);<br>
}<br>
<br>
// Extract overall result from high byte.<br>
if (BitSize > 8)<br>
- Op = DAG.getNode(ISD::SRL, DL, VT, Op, DAG.getConstant(BitSize - 8, VT));<br>
+ Op = DAG.getNode(ISD::SRL, DL, VT, Op,<br>
+ DAG.getConstant(BitSize - 8, DL, VT));<br>
<br>
return Op;<br>
}<br>
@@ -2501,23 +2505,23 @@ SDValue SystemZTargetLowering::lowerATOM<br>
if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)<br>
if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {<br>
Opcode = SystemZISD::ATOMIC_LOADW_ADD;<br>
- Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());<br>
+ Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());<br>
}<br>
<br>
// Get the address of the containing word.<br>
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,<br>
- DAG.getConstant(-4, PtrVT));<br>
+ DAG.getConstant(-4, DL, PtrVT));<br>
<br>
// Get the number of bits that the word must be rotated left in order<br>
// to bring the field to the top bits of a GR32.<br>
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,<br>
- DAG.getConstant(3, PtrVT));<br>
+ DAG.getConstant(3, DL, PtrVT));<br>
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);<br>
<br>
// Get the complementing shift amount, for rotating a field in the top<br>
// bits back to its proper position.<br>
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,<br>
- DAG.getConstant(0, WideVT), BitShift);<br>
+ DAG.getConstant(0, DL, WideVT), BitShift);<br>
<br>
// Extend the source operand to 32 bits and prepare it for the inner loop.<br>
// ATOMIC_SWAPW uses RISBG to rotate the field left, but all other<br>
@@ -2526,23 +2530,23 @@ SDValue SystemZTargetLowering::lowerATOM<br>
// bits must be set, while for other opcodes they should be left clear.<br>
if (Opcode != SystemZISD::ATOMIC_SWAPW)<br>
Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,<br>
- DAG.getConstant(32 - BitSize, WideVT));<br>
+ DAG.getConstant(32 - BitSize, DL, WideVT));<br>
if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||<br>
Opcode == SystemZISD::ATOMIC_LOADW_NAND)<br>
Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,<br>
- DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));<br>
+ DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));<br>
<br>
// Construct the ATOMIC_LOADW_* node.<br>
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);<br>
SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,<br>
- DAG.getConstant(BitSize, WideVT) };<br>
+ DAG.getConstant(BitSize, DL, WideVT) };<br>
SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,<br>
NarrowVT, MMO);<br>
<br>
// Rotate the result of the final CS so that the field is in the lower<br>
// bits of a GR32, then truncate it.<br>
SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,<br>
- DAG.getConstant(BitSize, WideVT));<br>
+ DAG.getConstant(BitSize, DL, WideVT));<br>
SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);<br>
<br>
SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };<br>
@@ -2568,10 +2572,10 @@ SDValue SystemZTargetLowering::lowerATOM<br>
// available or the negative value is in the range of A(G)FHI.<br>
int64_t Value = (-Op2->getAPIntValue()).getSExtValue();<br>
if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())<br>
- NegSrc2 = DAG.getConstant(Value, MemVT);<br>
+ NegSrc2 = DAG.getConstant(Value, DL, MemVT);<br>
} else if (Subtarget.hasInterlockedAccess1())<br>
// Use LAA(G) if available.<br>
- NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, MemVT),<br>
+ NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),<br>
Src2);<br>
<br>
if (NegSrc2.getNode())<br>
@@ -2610,23 +2614,23 @@ SDValue SystemZTargetLowering::lowerATOM<br>
<br>
// Get the address of the containing word.<br>
SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,<br>
- DAG.getConstant(-4, PtrVT));<br>
+ DAG.getConstant(-4, DL, PtrVT));<br>
<br>
// Get the number of bits that the word must be rotated left in order<br>
// to bring the field to the top bits of a GR32.<br>
SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,<br>
- DAG.getConstant(3, PtrVT));<br>
+ DAG.getConstant(3, DL, PtrVT));<br>
BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);<br>
<br>
// Get the complementing shift amount, for rotating a field in the top<br>
// bits back to its proper position.<br>
SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,<br>
- DAG.getConstant(0, WideVT), BitShift);<br>
+ DAG.getConstant(0, DL, WideVT), BitShift);<br>
<br>
// Construct the ATOMIC_CMP_SWAPW node.<br>
SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);<br>
SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,<br>
- NegBitShift, DAG.getConstant(BitSize, WideVT) };<br>
+ NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };<br>
SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,<br>
VTList, Ops, NarrowVT, MMO);<br>
return AtomicOp;<br>
@@ -2655,15 +2659,16 @@ SDValue SystemZTargetLowering::lowerPREF<br>
// Just preserve the chain.<br>
return Op.getOperand(0);<br>
<br>
+ SDLoc DL(Op);<br>
bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();<br>
unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;<br>
auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());<br>
SDValue Ops[] = {<br>
Op.getOperand(0),<br>
- DAG.getConstant(Code, MVT::i32),<br>
+ DAG.getConstant(Code, DL, MVT::i32),<br>
Op.getOperand(1)<br>
};<br>
- return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),<br>
+ return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,<br>
Node->getVTList(), Ops,<br>
Node->getMemoryVT(), Node->getMemOperand());<br>
}<br>
@@ -2671,10 +2676,11 @@ SDValue SystemZTargetLowering::lowerPREF<br>
// Return an i32 that contains the value of CC immediately after After,<br>
// whose final operand must be MVT::Glue.<br>
static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {<br>
+ SDLoc DL(After);<br>
SDValue Glue = SDValue(After, After->getNumValues() - 1);<br>
- SDValue IPM = DAG.getNode(SystemZISD::IPM, SDLoc(After), MVT::i32, Glue);<br>
- return DAG.getNode(ISD::SRL, SDLoc(After), MVT::i32, IPM,<br>
- DAG.getConstant(SystemZ::IPM_CC, MVT::i32));<br>
+ SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);<br>
+ return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,<br>
+ DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));<br>
}<br>
<br>
SDValue<br>
@@ -2851,9 +2857,10 @@ SDValue SystemZTargetLowering::PerformDA<br>
SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,<br>
Inner.getOperand(0));<br>
SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,<br>
- DAG.getConstant(NewShlAmt, ShiftVT));<br>
+ DAG.getConstant(NewShlAmt, SDLoc(Inner),<br>
+ ShiftVT));<br>
return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,<br>
- DAG.getConstant(NewSraAmt, ShiftVT));<br>
+ DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));<br>
}<br>
}<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZOperands.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZOperands.td?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZOperands.td (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZOperands.td Tue Apr 28 06:56:37 2015<br>
@@ -134,72 +134,79 @@ class BDLMode<string type, string bitsiz<br>
// Bits 0-15 (counting from the lsb).<br>
def LL16 : SDNodeXForm<imm, [{<br>
uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;<br>
- return CurDAG->getTargetConstant(Value, MVT::i64);<br>
+ return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);<br>
}]>;<br>
<br>
// Bits 16-31 (counting from the lsb).<br>
def LH16 : SDNodeXForm<imm, [{<br>
uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;<br>
- return CurDAG->getTargetConstant(Value, MVT::i64);<br>
+ return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);<br>
}]>;<br>
<br>
// Bits 32-47 (counting from the lsb).<br>
def HL16 : SDNodeXForm<imm, [{<br>
uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;<br>
- return CurDAG->getTargetConstant(Value, MVT::i64);<br>
+ return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);<br>
}]>;<br>
<br>
// Bits 48-63 (counting from the lsb).<br>
def HH16 : SDNodeXForm<imm, [{<br>
uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;<br>
- return CurDAG->getTargetConstant(Value, MVT::i64);<br>
+ return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);<br>
}]>;<br>
<br>
// Low 32 bits.<br>
def LF32 : SDNodeXForm<imm, [{<br>
uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;<br>
- return CurDAG->getTargetConstant(Value, MVT::i64);<br>
+ return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);<br>
}]>;<br>
<br>
// High 32 bits.<br>
def HF32 : SDNodeXForm<imm, [{<br>
uint64_t Value = N->getZExtValue() >> 32;<br>
- return CurDAG->getTargetConstant(Value, MVT::i64);<br>
+ return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);<br>
}]>;<br>
<br>
// Truncate an immediate to a 8-bit signed quantity.<br>
def SIMM8 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
// Truncate an immediate to a 8-bit unsigned quantity.<br>
def UIMM8 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
// Truncate an immediate to a 16-bit signed quantity.<br>
def SIMM16 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
// Truncate an immediate to a 16-bit unsigned quantity.<br>
def UIMM16 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
// Truncate an immediate to a 32-bit signed quantity.<br>
def SIMM32 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
// Truncate an immediate to a 32-bit unsigned quantity.<br>
def UIMM32 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
// Negate and then truncate an immediate to a 32-bit unsigned quantity.<br>
def NEGIMM32 : SDNodeXForm<imm, [{<br>
- return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), MVT::i64);<br>
+ return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),<br>
+ MVT::i64);<br>
}]>;<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Modified: llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp Tue Apr 28 06:56:37 2015<br>
@@ -46,10 +46,10 @@ static SDValue emitMemMem(SelectionDAG &<br>
// number of straight-line MVCs as 6 * 256 - 1.<br>
if (Size > 6 * 256)<br>
return DAG.getNode(Loop, DL, MVT::Other, Chain, Dst, Src,<br>
- DAG.getConstant(Size, PtrVT),<br>
- DAG.getConstant(Size / 256, PtrVT));<br>
+ DAG.getConstant(Size, DL, PtrVT),<br>
+ DAG.getConstant(Size / 256, DL, PtrVT));<br>
return DAG.getNode(Sequence, DL, MVT::Other, Chain, Dst, Src,<br>
- DAG.getConstant(Size, PtrVT));<br>
+ DAG.getConstant(Size, DL, PtrVT));<br>
}<br>
<br>
SDValue SystemZSelectionDAGInfo::<br>
@@ -78,7 +78,8 @@ static SDValue memsetStore(SelectionDAG<br>
for (unsigned I = 1; I < Size; ++I)<br>
StoreVal |= ByteVal << (I * 8);<br>
return DAG.getStore(Chain, DL,<br>
- DAG.getConstant(StoreVal, MVT::getIntegerVT(Size * 8)),<br>
+ DAG.getConstant(StoreVal, DL,<br>
+ MVT::getIntegerVT(Size * 8)),<br>
Dst, DstPtrInfo, false, false, Align);<br>
}<br>
<br>
@@ -112,7 +113,7 @@ EmitTargetCodeForMemset(SelectionDAG &DA<br>
if (Size2 == 0)<br>
return Chain1;<br>
Dst = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,<br>
- DAG.getConstant(Size1, PtrVT));<br>
+ DAG.getConstant(Size1, DL, PtrVT));<br>
DstPtrInfo = DstPtrInfo.getWithOffset(Size1);<br>
SDValue Chain2 = memsetStore(DAG, DL, Chain, Dst, ByteVal, Size2,<br>
std::min(Align, Size1), DstPtrInfo);<br>
@@ -126,7 +127,7 @@ EmitTargetCodeForMemset(SelectionDAG &DA<br>
if (Bytes == 1)<br>
return Chain1;<br>
SDValue Dst2 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,<br>
- DAG.getConstant(1, PtrVT));<br>
+ DAG.getConstant(1, DL, PtrVT));<br>
SDValue Chain2 = DAG.getStore(Chain, DL, Byte, Dst2,<br>
DstPtrInfo.getWithOffset(1),<br>
false, false, 1);<br>
@@ -146,7 +147,7 @@ EmitTargetCodeForMemset(SelectionDAG &DA<br>
Chain = DAG.getStore(Chain, DL, Byte, Dst, DstPtrInfo,<br>
false, false, Align);<br>
SDValue DstPlus1 = DAG.getNode(ISD::ADD, DL, PtrVT, Dst,<br>
- DAG.getConstant(1, PtrVT));<br>
+ DAG.getConstant(1, DL, PtrVT));<br>
return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,<br>
Chain, DstPlus1, Dst, Bytes - 1);<br>
}<br>
@@ -169,10 +170,10 @@ static SDValue emitCLC(SelectionDAG &DAG<br>
// needs 2 branches, whereas a straight-line sequence would need 3 or more.<br>
if (Size > 3 * 256)<br>
return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2,<br>
- DAG.getConstant(Size, PtrVT),<br>
- DAG.getConstant(Size / 256, PtrVT));<br>
+ DAG.getConstant(Size, DL, PtrVT),<br>
+ DAG.getConstant(Size / 256, DL, PtrVT));<br>
return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2,<br>
- DAG.getConstant(Size, PtrVT));<br>
+ DAG.getConstant(Size, DL, PtrVT));<br>
}<br>
<br>
// Convert the current CC value into an integer that is 0 if CC == 0,<br>
@@ -182,9 +183,9 @@ static SDValue emitCLC(SelectionDAG &DAG<br>
static SDValue addIPMSequence(SDLoc DL, SDValue Glue, SelectionDAG &DAG) {<br>
SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);<br>
SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,<br>
- DAG.getConstant(SystemZ::IPM_CC, MVT::i32));<br>
+ DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));<br>
SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL,<br>
- DAG.getConstant(31, MVT::i32));<br>
+ DAG.getConstant(31, DL, MVT::i32));<br>
return ROTL;<br>
}<br>
<br>
@@ -213,7 +214,7 @@ EmitTargetCodeForMemchr(SelectionDAG &DA<br>
Length = DAG.getZExtOrTrunc(Length, DL, PtrVT);<br>
Char = DAG.getZExtOrTrunc(Char, DL, MVT::i32);<br>
Char = DAG.getNode(ISD::AND, DL, MVT::i32, Char,<br>
- DAG.getConstant(255, MVT::i32));<br>
+ DAG.getConstant(255, DL, MVT::i32));<br>
SDValue Limit = DAG.getNode(ISD::ADD, DL, PtrVT, Src, Length);<br>
SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,<br>
Limit, Src, Char);<br>
@@ -222,9 +223,10 @@ EmitTargetCodeForMemchr(SelectionDAG &DA<br>
<br>
// Now select between End and null, depending on whether the character<br>
// was found.<br>
- SDValue Ops[] = {End, DAG.getConstant(0, PtrVT),<br>
- DAG.getConstant(SystemZ::CCMASK_SRST, MVT::i32),<br>
- DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, MVT::i32), Glue};<br>
+ SDValue Ops[] = {End, DAG.getConstant(0, DL, PtrVT),<br>
+ DAG.getConstant(SystemZ::CCMASK_SRST, DL, MVT::i32),<br>
+ DAG.getConstant(SystemZ::CCMASK_SRST_FOUND, DL, MVT::i32),<br>
+ Glue};<br>
VTs = DAG.getVTList(PtrVT, MVT::Glue);<br>
End = DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);<br>
return std::make_pair(End, Chain);<br>
@@ -237,7 +239,7 @@ EmitTargetCodeForStrcpy(SelectionDAG &DA<br>
MachinePointerInfo SrcPtrInfo, bool isStpcpy) const {<br>
SDVTList VTs = DAG.getVTList(Dest.getValueType(), MVT::Other);<br>
SDValue EndDest = DAG.getNode(SystemZISD::STPCPY, DL, VTs, Chain, Dest, Src,<br>
- DAG.getConstant(0, MVT::i32));<br>
+ DAG.getConstant(0, DL, MVT::i32));<br>
return std::make_pair(isStpcpy ? EndDest : Dest, EndDest.getValue(1));<br>
}<br>
<br>
@@ -248,7 +250,7 @@ EmitTargetCodeForStrcmp(SelectionDAG &DA<br>
MachinePointerInfo Op2PtrInfo) const {<br>
SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue);<br>
SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2,<br>
- DAG.getConstant(0, MVT::i32));<br>
+ DAG.getConstant(0, DL, MVT::i32));<br>
Chain = Unused.getValue(1);<br>
SDValue Glue = Chain.getValue(2);<br>
return std::make_pair(addIPMSequence(DL, Glue, DAG), Chain);<br>
@@ -265,7 +267,7 @@ static std::pair<SDValue, SDValue> getBo<br>
EVT PtrVT = Src.getValueType();<br>
SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other, MVT::Glue);<br>
SDValue End = DAG.getNode(SystemZISD::SEARCH_STRING, DL, VTs, Chain,<br>
- Limit, Src, DAG.getConstant(0, MVT::i32));<br>
+ Limit, Src, DAG.getConstant(0, DL, MVT::i32));<br>
Chain = End.getValue(1);<br>
SDValue Len = DAG.getNode(ISD::SUB, DL, PtrVT, End, Src);<br>
return std::make_pair(Len, Chain);<br>
@@ -275,7 +277,7 @@ std::pair<SDValue, SDValue> SystemZSelec<br>
EmitTargetCodeForStrlen(SelectionDAG &DAG, SDLoc DL, SDValue Chain,<br>
SDValue Src, MachinePointerInfo SrcPtrInfo) const {<br>
EVT PtrVT = Src.getValueType();<br>
- return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, PtrVT));<br>
+ return getBoundedStrlen(DAG, DL, Chain, Src, DAG.getConstant(0, DL, PtrVT));<br>
}<br>
<br>
std::pair<SDValue, SDValue> SystemZSelectionDAGInfo::<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue Apr 28 06:56:37 2015<br>
@@ -233,14 +233,15 @@ namespace {<br>
<br>
void EmitSpecialCodeForMain();<br>
<br>
- inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base,<br>
- SDValue &Scale, SDValue &Index,<br>
- SDValue &Disp, SDValue &Segment) {<br>
+ inline void getAddressOperands(X86ISelAddressMode &AM, SDLoc DL,<br>
+ SDValue &Base, SDValue &Scale,<br>
+ SDValue &Index, SDValue &Disp,<br>
+ SDValue &Segment) {<br>
Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase)<br>
? CurDAG->getTargetFrameIndex(AM.Base_FrameIndex,<br>
TLI->getPointerTy())<br>
: AM.Base_Reg;<br>
- Scale = getI8Imm(AM.Scale);<br>
+ Scale = getI8Imm(AM.Scale, DL);<br>
Index = AM.IndexReg;<br>
// These are 32-bit even in 64-bit mode since RIP relative offset<br>
// is 32-bit.<br>
@@ -261,7 +262,7 @@ namespace {<br>
Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,<br>
AM.SymbolFlags);<br>
else<br>
- Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);<br>
+ Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);<br>
<br>
if (AM.Segment.getNode())<br>
Segment = AM.Segment;<br>
@@ -271,14 +272,14 @@ namespace {<br>
<br>
/// getI8Imm - Return a target constant with the specified value, of type<br>
/// i8.<br>
- inline SDValue getI8Imm(unsigned Imm) {<br>
- return CurDAG->getTargetConstant(Imm, MVT::i8);<br>
+ inline SDValue getI8Imm(unsigned Imm, SDLoc DL) {<br>
+ return CurDAG->getTargetConstant(Imm, DL, MVT::i8);<br>
}<br>
<br>
/// getI32Imm - Return a target constant with the specified value, of type<br>
/// i32.<br>
- inline SDValue getI32Imm(unsigned Imm) {<br>
- return CurDAG->getTargetConstant(Imm, MVT::i32);<br>
+ inline SDValue getI32Imm(unsigned Imm, SDLoc DL) {<br>
+ return CurDAG->getTargetConstant(Imm, DL, MVT::i32);<br>
}<br>
<br>
/// getGlobalBaseReg - Return an SDNode that returns the value of<br>
@@ -801,11 +802,11 @@ static bool FoldMaskAndShiftToExtract(Se<br>
<br>
MVT VT = N.getSimpleValueType();<br>
SDLoc DL(N);<br>
- SDValue Eight = DAG.getConstant(8, MVT::i8);<br>
- SDValue NewMask = DAG.getConstant(0xff, VT);<br>
+ SDValue Eight = DAG.getConstant(8, DL, MVT::i8);<br>
+ SDValue NewMask = DAG.getConstant(0xff, DL, VT);<br>
SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);<br>
SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);<br>
- SDValue ShlCount = DAG.getConstant(ScaleLog, MVT::i8);<br>
+ SDValue ShlCount = DAG.getConstant(ScaleLog, DL, MVT::i8);<br>
SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);<br>
<br>
// Insert the new nodes into the topological ordering. We must do this in<br>
@@ -849,7 +850,7 @@ static bool FoldMaskedShiftToScaledMask(<br>
<br>
MVT VT = N.getSimpleValueType();<br>
SDLoc DL(N);<br>
- SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT);<br>
+ SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, DL, VT);<br>
SDValue NewAnd = DAG.getNode(ISD::AND, DL, VT, X, NewMask);<br>
SDValue NewShift = DAG.getNode(ISD::SHL, DL, VT, NewAnd, Shift.getOperand(1));<br>
<br>
@@ -955,9 +956,9 @@ static bool FoldMaskAndShiftToScale(Sele<br>
X = NewX;<br>
}<br>
SDLoc DL(N);<br>
- SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8);<br>
+ SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, DL, MVT::i8);<br>
SDValue NewSRL = DAG.getNode(ISD::SRL, DL, VT, X, NewSRLAmt);<br>
- SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, MVT::i8);<br>
+ SDValue NewSHLAmt = DAG.getConstant(AMShiftAmt, DL, MVT::i8);<br>
SDValue NewSHL = DAG.getNode(ISD::SHL, DL, VT, NewSRL, NewSHLAmt);<br>
<br>
// Insert the new nodes into the topological ordering. We must do this in<br>
@@ -1198,7 +1199,7 @@ bool X86DAGToDAGISel::MatchAddressRecurs<br>
}<br>
<br>
// Ok, the transformation is legal and appears profitable. Go for it.<br>
- SDValue Zero = CurDAG->getConstant(0, N.getValueType());<br>
+ SDValue Zero = CurDAG->getConstant(0, dl, N.getValueType());<br>
SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS);<br>
AM.IndexReg = Neg;<br>
AM.Scale = 1;<br>
@@ -1357,7 +1358,7 @@ bool X86DAGToDAGISel::SelectAddr(SDNode<br>
if (!AM.IndexReg.getNode())<br>
AM.IndexReg = CurDAG->getRegister(0, VT);<br>
<br>
- getAddressOperands(AM, Base, Scale, Index, Disp, Segment);<br>
+ getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);<br>
return true;<br>
}<br>
<br>
@@ -1413,7 +1414,7 @@ bool X86DAGToDAGISel::SelectMOV64Imm32(S<br>
if ((uint32_t)ImmVal != (uint64_t)ImmVal)<br>
return false;<br>
<br>
- Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);<br>
+ Imm = CurDAG->getTargetConstant(ImmVal, SDLoc(N), MVT::i64);<br>
return true;<br>
}<br>
<br>
@@ -1449,9 +1450,9 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr<br>
// Base could already be %rip, particularly in the x32 ABI.<br>
Base = SDValue(CurDAG->getMachineNode(<br>
TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,<br>
- CurDAG->getTargetConstant(0, MVT::i64),<br>
+ CurDAG->getTargetConstant(0, DL, MVT::i64),<br>
Base,<br>
- CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),<br>
+ CurDAG->getTargetConstant(X86::sub_32bit, DL, MVT::i32)),<br>
0);<br>
}<br>
<br>
@@ -1463,9 +1464,10 @@ bool X86DAGToDAGISel::SelectLEA64_32Addr<br>
"Expect to be extending 32-bit registers for use in LEA");<br>
Index = SDValue(CurDAG->getMachineNode(<br>
TargetOpcode::SUBREG_TO_REG, DL, MVT::i64,<br>
- CurDAG->getTargetConstant(0, MVT::i64),<br>
+ CurDAG->getTargetConstant(0, DL, MVT::i64),<br>
Index,<br>
- CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),<br>
+ CurDAG->getTargetConstant(X86::sub_32bit, DL,<br>
+ MVT::i32)),<br>
0);<br>
}<br>
<br>
@@ -1531,7 +1533,7 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDVa<br>
if (Complexity <= 2)<br>
return false;<br>
<br>
- getAddressOperands(AM, Base, Scale, Index, Disp, Segment);<br>
+ getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);<br>
return true;<br>
}<br>
<br>
@@ -1555,7 +1557,7 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(<br>
AM.IndexReg = CurDAG->getRegister(0, MVT::i64);<br>
}<br>
<br>
- getAddressOperands(AM, Base, Scale, Index, Disp, Segment);<br>
+ getAddressOperands(AM, SDLoc(N), Base, Scale, Index, Disp, Segment);<br>
return true;<br>
}<br>
<br>
@@ -1725,7 +1727,7 @@ static SDValue getAtomicLoadArithTargetC<br>
// an immediate operand to sub. However, it still fits in 32 bits for the<br>
// add (since it is not negated) so we can return target-constant.<br>
if (CNVal == INT32_MIN)<br>
- return CurDAG->getTargetConstant(CNVal, NVT);<br>
+ return CurDAG->getTargetConstant(CNVal, dl, NVT);<br>
// For atomic-load-add, we could do some optimizations.<br>
if (Op == ADD) {<br>
// Translate to INC/DEC if ADD by 1 or -1.<br>
@@ -1740,7 +1742,7 @@ static SDValue getAtomicLoadArithTargetC<br>
CNVal = -CNVal;<br>
}<br>
}<br>
- return CurDAG->getTargetConstant(CNVal, NVT);<br>
+ return CurDAG->getTargetConstant(CNVal, dl, NVT);<br>
}<br>
<br>
// If the value operand is single-used, try to optimize it.<br>
@@ -2053,12 +2055,14 @@ SDNode *X86DAGToDAGISel::SelectGather(SD<br>
SDVTList VTs = CurDAG->getVTList(VSrc.getValueType(), VSrc.getValueType(),<br>
MVT::Other);<br>
<br>
+ SDLoc DL(Node);<br>
+<br>
// Memory Operands: Base, Scale, Index, Disp, Segment<br>
- SDValue Disp = CurDAG->getTargetConstant(0, MVT::i32);<br>
+ SDValue Disp = CurDAG->getTargetConstant(0, DL, MVT::i32);<br>
SDValue Segment = CurDAG->getRegister(0, MVT::i32);<br>
- const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue()), VIdx,<br>
+ const SDValue Ops[] = { VSrc, Base, getI8Imm(Scale->getSExtValue(), DL), VIdx,<br>
Disp, Segment, VMask, Chain};<br>
- SDNode *ResNode = CurDAG->getMachineNode(Opc, SDLoc(Node), VTs, Ops);<br>
+ SDNode *ResNode = CurDAG->getMachineNode(Opc, DL, VTs, Ops);<br>
// Node has 2 outputs: VDst and MVT::Other.<br>
// ResNode has 3 outputs: VDst, VMask_wb, and MVT::Other.<br>
// We replace VDst of Node with VDst of ResNode, and Other of Node with Other<br>
@@ -2232,13 +2236,13 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
}<br>
<br>
// Emit the smaller op and the shift.<br>
- SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT);<br>
+ SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, dl, CstVT);<br>
SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst);<br>
if (ShlVal == 1)<br>
return CurDAG->SelectNodeTo(Node, AddOp, NVT, SDValue(New, 0),<br>
SDValue(New, 0));<br>
return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0),<br>
- getI8Imm(ShlVal));<br>
+ getI8Imm(ShlVal, dl));<br>
}<br>
case X86ISD::UMUL8:<br>
case X86ISD::SMUL8: {<br>
@@ -2402,7 +2406,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
// Shift AX down 8 bits.<br>
Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16,<br>
Result,<br>
- CurDAG->getTargetConstant(8, MVT::i8)), 0);<br>
+ CurDAG->getTargetConstant(8, dl, MVT::i8)),<br>
+ 0);<br>
// Then truncate it down to i8.<br>
ReplaceUses(SDValue(Node, 1),<br>
CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result));<br>
@@ -2522,7 +2527,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
ClrNode =<br>
SDValue(CurDAG->getMachineNode(<br>
TargetOpcode::EXTRACT_SUBREG, dl, MVT::i16, ClrNode,<br>
- CurDAG->getTargetConstant(X86::sub_16bit, MVT::i32)),<br>
+ CurDAG->getTargetConstant(X86::sub_16bit, dl,<br>
+ MVT::i32)),<br>
0);<br>
break;<br>
case MVT::i32:<br>
@@ -2531,8 +2537,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
ClrNode =<br>
SDValue(CurDAG->getMachineNode(<br>
TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,<br>
- CurDAG->getTargetConstant(0, MVT::i64), ClrNode,<br>
- CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),<br>
+ CurDAG->getTargetConstant(0, dl, MVT::i64), ClrNode,<br>
+ CurDAG->getTargetConstant(X86::sub_32bit, dl,<br>
+ MVT::i32)),<br>
0);<br>
break;<br>
default:<br>
@@ -2584,8 +2591,9 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
Result =<br>
SDValue(CurDAG->getMachineNode(<br>
TargetOpcode::SUBREG_TO_REG, dl, MVT::i64,<br>
- CurDAG->getTargetConstant(0, MVT::i64), Result,<br>
- CurDAG->getTargetConstant(X86::sub_32bit, MVT::i32)),<br>
+ CurDAG->getTargetConstant(0, dl, MVT::i64), Result,<br>
+ CurDAG->getTargetConstant(X86::sub_32bit, dl,<br>
+ MVT::i32)),<br>
0);<br>
}<br>
} else {<br>
@@ -2642,7 +2650,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 &&<br>
(!(C->getZExtValue() & 0x80) ||<br>
HasNoSignedComparisonUses(Node))) {<br>
- SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8);<br>
+ SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl, MVT::i8);<br>
SDValue Reg = N0.getNode()->getOperand(0);<br>
<br>
// On x86-32, only the ABCD registers have 8-bit subregisters.<br>
@@ -2653,7 +2661,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;<br>
default: llvm_unreachable("Unsupported TEST operand type!");<br>
}<br>
- SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);<br>
+ SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);<br>
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,<br>
Reg.getValueType(), Reg, RC), 0);<br>
}<br>
@@ -2678,7 +2686,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
HasNoSignedComparisonUses(Node))) {<br>
// Shift the immediate right by 8 bits.<br>
SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8,<br>
- MVT::i8);<br>
+ dl, MVT::i8);<br>
SDValue Reg = N0.getNode()->getOperand(0);<br>
<br>
// Put the value in an ABCD register.<br>
@@ -2689,7 +2697,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break;<br>
default: llvm_unreachable("Unsupported TEST operand type!");<br>
}<br>
- SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);<br>
+ SDValue RC = CurDAG->getTargetConstant(TRC->getID(), dl, MVT::i32);<br>
Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl,<br>
Reg.getValueType(), Reg, RC), 0);<br>
<br>
@@ -2714,7 +2722,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
N0.getValueType() != MVT::i16 &&<br>
(!(C->getZExtValue() & 0x8000) ||<br>
HasNoSignedComparisonUses(Node))) {<br>
- SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16);<br>
+ SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,<br>
+ MVT::i16);<br>
SDValue Reg = N0.getNode()->getOperand(0);<br>
<br>
// Extract the 16-bit subregister.<br>
@@ -2736,7 +2745,8 @@ SDNode *X86DAGToDAGISel::Select(SDNode *<br>
N0.getValueType() == MVT::i64 &&<br>
(!(C->getZExtValue() & 0x80000000) ||<br>
HasNoSignedComparisonUses(Node))) {<br>
- SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32);<br>
+ SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), dl,<br>
+ MVT::i32);<br>
SDValue Reg = N0.getNode()->getOperand(0);<br>
<br>
// Extract the 32-bit subregister.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Apr 28 06:56:37 2015<br>
@@ -1892,7 +1892,7 @@ X86TargetLowering::LowerReturn(SDValue C<br>
SmallVector<SDValue, 6> RetOps;<br>
RetOps.push_back(Chain); // Operand #0 = Chain (updated below)<br>
// Operand #1 = Bytes To Pop<br>
- RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(),<br>
+ RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), dl,<br>
MVT::i16));<br>
<br>
// Copy the result values into the output registers.<br>
@@ -2095,7 +2095,7 @@ X86TargetLowering::LowerCallResult(SDVal<br>
if (CopyVT != VA.getValVT())<br>
Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val,<br>
// This truncation won't change the value.<br>
- DAG.getIntPtrConstant(1));<br>
+ DAG.getIntPtrConstant(1, dl));<br>
<br>
InFlag = Chain.getValue(2);<br>
InVals.push_back(Val);<br>
@@ -2155,7 +2155,7 @@ static SDValue<br>
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,<br>
ISD::ArgFlagsTy Flags, SelectionDAG &DAG,<br>
SDLoc dl) {<br>
- SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);<br>
+ SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);<br>
<br>
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),<br>
/*isVolatile*/false, /*AlwaysInline=*/true,<br>
@@ -2503,7 +2503,7 @@ X86TargetLowering::LowerFormalArguments(<br>
unsigned Offset = FuncInfo->getVarArgsGPOffset();<br>
for (SDValue Val : LiveGPRs) {<br>
SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,<br>
- DAG.getIntPtrConstant(Offset));<br>
+ DAG.getIntPtrConstant(Offset, dl));<br>
SDValue Store =<br>
DAG.getStore(Val.getValue(1), dl, Val, FIN,<br>
MachinePointerInfo::getFixedStack(<br>
@@ -2519,9 +2519,9 @@ X86TargetLowering::LowerFormalArguments(<br>
SaveXMMOps.push_back(Chain);<br>
SaveXMMOps.push_back(ALVal);<br>
SaveXMMOps.push_back(DAG.getIntPtrConstant(<br>
- FuncInfo->getRegSaveFrameIndex()));<br>
+ FuncInfo->getRegSaveFrameIndex(), dl));<br>
SaveXMMOps.push_back(DAG.getIntPtrConstant(<br>
- FuncInfo->getVarArgsFPOffset()));<br>
+ FuncInfo->getVarArgsFPOffset(), dl));<br>
SaveXMMOps.insert(SaveXMMOps.end(), LiveXMMRegs.begin(),<br>
LiveXMMRegs.end());<br>
MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl,<br>
@@ -2621,7 +2621,7 @@ X86TargetLowering::LowerFormalArguments(<br>
int UnwindHelpFI = MFI->CreateStackObject(8, 8, /*isSS=*/false);<br>
SDValue StackSlot = DAG.getFrameIndex(UnwindHelpFI, MVT::i64);<br>
MMI.getWinEHFuncInfo(MF.getFunction()).UnwindHelpFrameIdx = UnwindHelpFI;<br>
- SDValue Neg2 = DAG.getConstant(-2, MVT::i64);<br>
+ SDValue Neg2 = DAG.getConstant(-2, dl, MVT::i64);<br>
Chain = DAG.getStore(Chain, dl, Neg2, StackSlot,<br>
MachinePointerInfo::getFixedStack(UnwindHelpFI),<br>
/*isVolatile=*/true,<br>
@@ -2638,7 +2638,7 @@ X86TargetLowering::LowerMemOpCallTo(SDVa<br>
const CCValAssign &VA,<br>
ISD::ArgFlagsTy Flags) const {<br>
unsigned LocMemOffset = VA.getLocMemOffset();<br>
- SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);<br>
+ SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);<br>
PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);<br>
if (Flags.isByVal())<br>
return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl);<br>
@@ -2784,7 +2784,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
<br>
if (!IsSibcall)<br>
Chain = DAG.getCALLSEQ_START(<br>
- Chain, DAG.getIntPtrConstant(NumBytesToPush, true), dl);<br>
+ Chain, DAG.getIntPtrConstant(NumBytesToPush, dl, true), dl);<br>
<br>
SDValue RetAddrFrIdx;<br>
// Load return address for tail calls.<br>
@@ -2916,7 +2916,8 @@ X86TargetLowering::LowerCall(TargetLower<br>
&& "SSE registers cannot be used when SSE is disabled");<br>
<br>
RegsToPass.push_back(std::make_pair(unsigned(X86::AL),<br>
- DAG.getConstant(NumXMMRegs, MVT::i8)));<br>
+ DAG.getConstant(NumXMMRegs, dl,<br>
+ MVT::i8)));<br>
}<br>
<br>
if (isVarArg && IsMustTail) {<br>
@@ -2960,7 +2961,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
<br>
if (Flags.isByVal()) {<br>
// Copy relative to framepointer.<br>
- SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset());<br>
+ SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset(), dl);<br>
if (!StackPtr.getNode())<br>
StackPtr = DAG.getCopyFromReg(Chain, dl,<br>
RegInfo->getStackRegister(),<br>
@@ -3086,8 +3087,8 @@ X86TargetLowering::LowerCall(TargetLower<br>
<br>
if (!IsSibcall && isTailCall) {<br>
Chain = DAG.getCALLSEQ_END(Chain,<br>
- DAG.getIntPtrConstant(NumBytesToPop, true),<br>
- DAG.getIntPtrConstant(0, true), InFlag, dl);<br>
+ DAG.getIntPtrConstant(NumBytesToPop, dl, true),<br>
+ DAG.getIntPtrConstant(0, dl, true), InFlag, dl);<br>
InFlag = Chain.getValue(1);<br>
}<br>
<br>
@@ -3095,7 +3096,7 @@ X86TargetLowering::LowerCall(TargetLower<br>
Ops.push_back(Callee);<br>
<br>
if (isTailCall)<br>
- Ops.push_back(DAG.getConstant(FPDiff, MVT::i32));<br>
+ Ops.push_back(DAG.getConstant(FPDiff, dl, MVT::i32));<br>
<br>
// Add argument registers to the end of the list so that they are known live<br>
// into the call.<br>
@@ -3144,8 +3145,8 @@ X86TargetLowering::LowerCall(TargetLower<br>
// Returns a flag for retval copy to use.<br>
if (!IsSibcall) {<br>
Chain = DAG.getCALLSEQ_END(Chain,<br>
- DAG.getIntPtrConstant(NumBytesToPop, true),<br>
- DAG.getIntPtrConstant(NumBytesForCalleeToPop,<br>
+ DAG.getIntPtrConstant(NumBytesToPop, dl, true),<br>
+ DAG.getIntPtrConstant(NumBytesForCalleeToPop, dl,<br>
true),<br>
InFlag, dl);<br>
InFlag = Chain.getValue(1);<br>
@@ -3532,7 +3533,8 @@ static SDValue getTargetShuffleNode(unsi<br>
case X86ISD::PSHUFLW:<br>
case X86ISD::VPERMILPI:<br>
case X86ISD::VPERMI:<br>
- return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8));<br>
+ return DAG.getNode(Opc, dl, VT, V1,<br>
+ DAG.getConstant(TargetMask, dl, MVT::i8));<br>
}<br>
}<br>
<br>
@@ -3642,13 +3644,13 @@ static bool isX86CCUnsigned(unsigned X86<br>
/// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86<br>
/// specific condition code, returning the condition code and the LHS/RHS of the<br>
/// comparison to make.<br>
-static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP,<br>
+static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, SDLoc DL, bool isFP,<br>
SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) {<br>
if (!isFP) {<br>
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {<br>
if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {<br>
// X > -1 -> X == 0, jump !sign.<br>
- RHS = DAG.getConstant(0, RHS.getValueType());<br>
+ RHS = DAG.getConstant(0, DL, RHS.getValueType());<br>
return X86::COND_NS;<br>
}<br>
if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) {<br>
@@ -3657,7 +3659,7 @@ static unsigned TranslateX86CC(ISD::Cond<br>
}<br>
if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) {<br>
// X < 1 -> X <= 0<br>
- RHS = DAG.getConstant(0, RHS.getValueType());<br>
+ RHS = DAG.getConstant(0, DL, RHS.getValueType());<br>
return X86::COND_LE;<br>
}<br>
}<br>
@@ -3960,26 +3962,26 @@ static SDValue getZeroVector(EVT VT, con<br>
SDValue Vec;<br>
if (VT.is128BitVector()) { // SSE<br>
if (Subtarget->hasSSE2()) { // SSE2<br>
- SDValue Cst = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Cst = DAG.getConstant(0, dl, MVT::i32);<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);<br>
} else { // SSE1<br>
- SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);<br>
+ SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);<br>
}<br>
} else if (VT.is256BitVector()) { // AVX<br>
if (Subtarget->hasInt256()) { // AVX2<br>
- SDValue Cst = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Cst = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i32, Ops);<br>
} else {<br>
// 256-bit logic and arithmetic instructions in AVX are all<br>
// floating-point, no support for integer ops. Emit fp zeroed vectors.<br>
- SDValue Cst = DAG.getConstantFP(+0.0, MVT::f32);<br>
+ SDValue Cst = DAG.getConstantFP(+0.0, dl, MVT::f32);<br>
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops);<br>
}<br>
} else if (VT.is512BitVector()) { // AVX-512<br>
- SDValue Cst = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Cst = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst,<br>
Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst };<br>
Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i32, Ops);<br>
@@ -3989,7 +3991,7 @@ static SDValue getZeroVector(EVT VT, con<br>
&& "Unexpected vector type");<br>
assert((Subtarget->hasVLX() || VT.getVectorNumElements() >= 8)<br>
&& "Unexpected vector type");<br>
- SDValue Cst = DAG.getConstant(0, MVT::i1);<br>
+ SDValue Cst = DAG.getConstant(0, dl, MVT::i1);<br>
SmallVector<SDValue, 64> Ops(VT.getVectorNumElements(), Cst);<br>
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);<br>
} else<br>
@@ -4027,7 +4029,7 @@ static SDValue ExtractSubVector(SDValue<br>
makeArrayRef(Vec->op_begin() + NormalizedIdxVal,<br>
ElemsPerChunk));<br>
<br>
- SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);<br>
+ SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);<br>
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, VecIdx);<br>
}<br>
<br>
@@ -4071,7 +4073,7 @@ static SDValue InsertSubVector(SDValue R<br>
unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/vectorWidth)<br>
* ElemsPerChunk);<br>
<br>
- SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal);<br>
+ SDValue VecIdx = DAG.getIntPtrConstant(NormalizedIdxVal, dl);<br>
return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, VecIdx);<br>
}<br>
<br>
@@ -4093,7 +4095,7 @@ static SDValue Insert128BitVector(SDValu<br>
if (IdxVal == 0 && Result.getValueType().is256BitVector() &&<br>
Result.getOpcode() != ISD::UNDEF) {<br>
EVT ResultVT = Result.getValueType();<br>
- SDValue ZeroIndex = DAG.getIntPtrConstant(0);<br>
+ SDValue ZeroIndex = DAG.getIntPtrConstant(0, dl);<br>
SDValue Undef = DAG.getUNDEF(ResultVT);<br>
SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef,<br>
Vec, ZeroIndex);<br>
@@ -4105,7 +4107,7 @@ static SDValue Insert128BitVector(SDValu<br>
unsigned ScalarSize = ScalarType.getSizeInBits();<br>
assert((ScalarSize == 64 || ScalarSize == 32) && "Unknown float type");<br>
unsigned MaskVal = (ScalarSize == 64) ? 0x03 : 0x0f;<br>
- SDValue Mask = DAG.getConstant(MaskVal, MVT::i8);<br>
+ SDValue Mask = DAG.getConstant(MaskVal, dl, MVT::i8);<br>
return DAG.getNode(X86ISD::BLENDI, dl, ResultVT, Result, Vec256, Mask);<br>
}<br>
<br>
@@ -4121,7 +4123,7 @@ static SDValue Insert128BitVector(SDValu<br>
// will be created by InsertSubVector().<br>
MVT CastVT = Subtarget.hasAVX2() ? MVT::v8i32 : MVT::v8f32;<br>
<br>
- SDValue Mask = DAG.getConstant(0x0f, MVT::i8);<br>
+ SDValue Mask = DAG.getConstant(0x0f, dl, MVT::i8);<br>
Vec256 = DAG.getNode(ISD::BITCAST, dl, CastVT, Vec256);<br>
Vec256 = DAG.getNode(X86ISD::BLENDI, dl, CastVT, Result, Vec256, Mask);<br>
return DAG.getNode(ISD::BITCAST, dl, ResultVT, Vec256);<br>
@@ -4162,7 +4164,7 @@ static SDValue getOnesVector(MVT VT, boo<br>
SDLoc dl) {<br>
assert(VT.isVector() && "Expected a vector type");<br>
<br>
- SDValue Cst = DAG.getConstant(~0U, MVT::i32);<br>
+ SDValue Cst = DAG.getConstant(~0U, dl, MVT::i32);<br>
SDValue Vec;<br>
if (VT.is256BitVector()) {<br>
if (HasInt256) { // AVX2<br>
@@ -4492,7 +4494,7 @@ static SDValue LowerBuildVectorv16i8(SDV<br>
}<br>
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,<br>
MVT::v16i8, V, Op.getOperand(i),<br>
- DAG.getIntPtrConstant(i));<br>
+ DAG.getIntPtrConstant(i, dl));<br>
}<br>
}<br>
<br>
@@ -4520,7 +4522,7 @@ static SDValue LowerBuildVectorv16i8(SDV<br>
if (ThisIsNonZero) {<br>
ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i));<br>
ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16,<br>
- ThisElt, DAG.getConstant(8, MVT::i8));<br>
+ ThisElt, DAG.getConstant(8, dl, MVT::i8));<br>
if (LastIsNonZero)<br>
ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt);<br>
} else<br>
@@ -4528,7 +4530,7 @@ static SDValue LowerBuildVectorv16i8(SDV<br>
<br>
if (ThisElt.getNode())<br>
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt,<br>
- DAG.getIntPtrConstant(i/2));<br>
+ DAG.getIntPtrConstant(i/2, dl));<br>
}<br>
}<br>
<br>
@@ -4560,7 +4562,7 @@ static SDValue LowerBuildVectorv8i16(SDV<br>
}<br>
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl,<br>
MVT::v8i16, V, Op.getOperand(i),<br>
- DAG.getIntPtrConstant(i));<br>
+ DAG.getIntPtrConstant(i, dl));<br>
}<br>
}<br>
<br>
@@ -4667,9 +4669,10 @@ static SDValue LowerBuildVectorv4x32(SDV<br>
<br>
unsigned InsertPSMask = EltMaskIdx << 6 | EltIdx << 4 | ZMask;<br>
assert((InsertPSMask & ~0xFFu) == 0 && "Invalid mask!");<br>
- SDValue Result = DAG.getNode(X86ISD::INSERTPS, SDLoc(Op), MVT::v4f32, V1, V2,<br>
- DAG.getIntPtrConstant(InsertPSMask));<br>
- return DAG.getNode(ISD::BITCAST, SDLoc(Op), VT, Result);<br>
+ SDLoc DL(Op);<br>
+ SDValue Result = DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,<br>
+ DAG.getIntPtrConstant(InsertPSMask, DL));<br>
+ return DAG.getNode(ISD::BITCAST, DL, VT, Result);<br>
}<br>
<br>
/// Return a vector logical shift node.<br>
@@ -4682,7 +4685,7 @@ static SDValue getVShift(bool isLeft, EV<br>
SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp);<br>
MVT ScalarShiftTy = TLI.getScalarShiftAmountTy(SrcOp.getValueType());<br>
assert(NumBits % 8 == 0 && "Only support byte sized shifts");<br>
- SDValue ShiftVal = DAG.getConstant(NumBits/8, ScalarShiftTy);<br>
+ SDValue ShiftVal = DAG.getConstant(NumBits/8, dl, ScalarShiftTy);<br>
return DAG.getNode(ISD::BITCAST, dl, VT,<br>
DAG.getNode(Opc, dl, ShVT, SrcOp, ShiftVal));<br>
}<br>
@@ -4739,9 +4742,11 @@ LowerAsSplatVectorLoad(SDValue SrcOp, MV<br>
if ((Offset % RequiredAlign) & 3)<br>
return SDValue();<br>
int64_t StartOffset = Offset & ~(RequiredAlign-1);<br>
- if (StartOffset)<br>
- Ptr = DAG.getNode(ISD::ADD, SDLoc(Ptr), Ptr.getValueType(),<br>
- Ptr,DAG.getConstant(StartOffset, Ptr.getValueType()));<br>
+ if (StartOffset) {<br>
+ SDLoc DL(Ptr);<br>
+ Ptr = DAG.getNode(ISD::ADD, DL, Ptr.getValueType(), Ptr,<br>
+ DAG.getConstant(StartOffset, DL, Ptr.getValueType()));<br>
+ }<br>
<br>
int EltNo = (Offset - StartOffset) >> 2;<br>
unsigned NumElems = VT.getVectorNumElements();<br>
@@ -5134,7 +5139,7 @@ static SDValue buildFromShuffleMostly(SD<br>
for (unsigned i = 0, e = InsertIndices.size(); i != e; ++i) {<br>
unsigned Idx = InsertIndices[i];<br>
NV = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, NV, Op.getOperand(Idx),<br>
- DAG.getIntPtrConstant(Idx));<br>
+ DAG.getIntPtrConstant(Idx, DL));<br>
}<br>
<br>
return NV;<br>
@@ -5150,13 +5155,13 @@ X86TargetLowering::LowerBUILD_VECTORvXi1<br>
<br>
SDLoc dl(Op);<br>
if (ISD::isBuildVectorAllZeros(Op.getNode())) {<br>
- SDValue Cst = DAG.getTargetConstant(0, MVT::i1);<br>
+ SDValue Cst = DAG.getTargetConstant(0, dl, MVT::i1);<br>
SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);<br>
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);<br>
}<br>
<br>
if (ISD::isBuildVectorAllOnes(Op.getNode())) {<br>
- SDValue Cst = DAG.getTargetConstant(1, MVT::i1);<br>
+ SDValue Cst = DAG.getTargetConstant(1, dl, MVT::i1);<br>
SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Cst);<br>
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ops);<br>
}<br>
@@ -5186,15 +5191,15 @@ X86TargetLowering::LowerBUILD_VECTORvXi1<br>
<br>
if (AllContants) {<br>
SDValue FullMask = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1,<br>
- DAG.getConstant(Immediate, MVT::i16));<br>
+ DAG.getConstant(Immediate, dl, MVT::i16));<br>
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, FullMask,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
if (NumNonConsts == 1 && NonConstIdx != 0) {<br>
SDValue DstVec;<br>
if (NumConsts) {<br>
- SDValue VecAsImm = DAG.getConstant(Immediate,<br>
+ SDValue VecAsImm = DAG.getConstant(Immediate, dl,<br>
MVT::getIntegerVT(VT.getSizeInBits()));<br>
DstVec = DAG.getNode(ISD::BITCAST, dl, VT, VecAsImm);<br>
}<br>
@@ -5202,7 +5207,7 @@ X86TargetLowering::LowerBUILD_VECTORvXi1<br>
DstVec = DAG.getUNDEF(VT);<br>
return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, DstVec,<br>
Op.getOperand(NonConstIdx),<br>
- DAG.getIntPtrConstant(NonConstIdx));<br>
+ DAG.getIntPtrConstant(NonConstIdx, dl));<br>
}<br>
if (!IsSplat && (NonConstIdx != 0))<br>
llvm_unreachable("Unsupported BUILD_VECTOR operation");<br>
@@ -5210,12 +5215,12 @@ X86TargetLowering::LowerBUILD_VECTORvXi1<br>
SDValue Select;<br>
if (IsSplat)<br>
Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),<br>
- DAG.getConstant(-1, SelectVT),<br>
- DAG.getConstant(0, SelectVT));<br>
+ DAG.getConstant(-1, dl, SelectVT),<br>
+ DAG.getConstant(0, dl, SelectVT));<br>
else<br>
Select = DAG.getNode(ISD::SELECT, dl, SelectVT, Op.getOperand(0),<br>
- DAG.getConstant((Immediate | 1), SelectVT),<br>
- DAG.getConstant(Immediate, SelectVT));<br>
+ DAG.getConstant((Immediate | 1), dl, SelectVT),<br>
+ DAG.getConstant(Immediate, dl, SelectVT));<br>
return DAG.getNode(ISD::BITCAST, dl, VT, Select);<br>
}<br>
<br>
@@ -5733,7 +5738,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDV<br>
if (VT.is512BitVector()) {<br>
SDValue ZeroVec = getZeroVector(VT, Subtarget, DAG, dl);<br>
return DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, ZeroVec,<br>
- Item, DAG.getIntPtrConstant(0));<br>
+ Item, DAG.getIntPtrConstant(0, dl));<br>
}<br>
assert((VT.is128BitVector() || VT.is256BitVector()) &&<br>
"Expected an SSE value type!");<br>
@@ -5927,7 +5932,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDV<br>
for (unsigned i = 1; i < NumElems; ++i) {<br>
if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;<br>
Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,<br>
- Op.getOperand(i), DAG.getIntPtrConstant(i));<br>
+ Op.getOperand(i), DAG.getIntPtrConstant(i, dl));<br>
}<br>
return Result;<br>
}<br>
@@ -6025,10 +6030,10 @@ static SDValue LowerCONCAT_VECTORSvXi1(S<br>
if (IsZeroV1 && IsZeroV2)<br>
return getZeroVector(ResVT, Subtarget, DAG, dl);<br>
<br>
- SDValue ZeroIdx = DAG.getIntPtrConstant(0);<br>
+ SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);<br>
SDValue Undef = DAG.getUNDEF(ResVT);<br>
unsigned NumElems = ResVT.getVectorNumElements();<br>
- SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);<br>
+ SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);<br>
<br>
V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx);<br>
V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits);<br>
@@ -6196,7 +6201,7 @@ static bool isShuffleEquivalent(SDValue<br>
/// example.<br>
///<br>
/// NB: We rely heavily on "undef" masks preserving the input lane.<br>
-static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask,<br>
+static SDValue getV4X86ShuffleImm8ForMask(ArrayRef<int> Mask, SDLoc DL,<br>
SelectionDAG &DAG) {<br>
assert(Mask.size() == 4 && "Only 4-lane shuffle masks");<br>
assert(Mask[0] >= -1 && Mask[0] < 4 && "Out of bound mask element!");<br>
@@ -6209,7 +6214,7 @@ static SDValue getV4X86ShuffleImm8ForMas<br>
Imm |= (Mask[1] == -1 ? 1 : Mask[1]) << 2;<br>
Imm |= (Mask[2] == -1 ? 2 : Mask[2]) << 4;<br>
Imm |= (Mask[3] == -1 ? 3 : Mask[3]) << 6;<br>
- return DAG.getConstant(Imm, MVT::i8);<br>
+ return DAG.getConstant(Imm, DL, MVT::i8);<br>
}<br>
<br>
/// \brief Try to emit a blend instruction for a shuffle using bit math.<br>
@@ -6223,8 +6228,9 @@ static SDValue lowerVectorShuffleAsBitBl<br>
assert(VT.isInteger() && "Only supports integer vector types!");<br>
MVT EltVT = VT.getScalarType();<br>
int NumEltBits = EltVT.getSizeInBits();<br>
- SDValue Zero = DAG.getConstant(0, EltVT);<br>
- SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), EltVT);<br>
+ SDValue Zero = DAG.getConstant(0, DL, EltVT);<br>
+ SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,<br>
+ EltVT);<br>
SmallVector<SDValue, 16> MaskOps;<br>
for (int i = 0, Size = Mask.size(); i < Size; ++i) {<br>
if (Mask[i] != -1 && Mask[i] != i && Mask[i] != i + Size)<br>
@@ -6270,7 +6276,7 @@ static SDValue lowerVectorShuffleAsBlend<br>
case MVT::v4f64:<br>
case MVT::v8f32:<br>
return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V2,<br>
- DAG.getConstant(BlendMask, MVT::i8));<br>
+ DAG.getConstant(BlendMask, DL, MVT::i8));<br>
<br>
case MVT::v4i64:<br>
case MVT::v8i32:<br>
@@ -6294,7 +6300,7 @@ static SDValue lowerVectorShuffleAsBlend<br>
V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);<br>
return DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::BLENDI, DL, BlendVT, V1, V2,<br>
- DAG.getConstant(BlendMask, MVT::i8)));<br>
+ DAG.getConstant(BlendMask, DL, MVT::i8)));<br>
}<br>
// FALLTHROUGH<br>
case MVT::v8i16: {<br>
@@ -6311,7 +6317,7 @@ static SDValue lowerVectorShuffleAsBlend<br>
V2 = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V2);<br>
return DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::BLENDI, DL, MVT::v8i16, V1, V2,<br>
- DAG.getConstant(BlendMask, MVT::i8)));<br>
+ DAG.getConstant(BlendMask, DL, MVT::i8)));<br>
}<br>
<br>
case MVT::v16i16: {<br>
@@ -6325,7 +6331,7 @@ static SDValue lowerVectorShuffleAsBlend<br>
if (RepeatedMask[i] >= 16)<br>
BlendMask |= 1u << i;<br>
return DAG.getNode(X86ISD::BLENDI, DL, MVT::v16i16, V1, V2,<br>
- DAG.getConstant(BlendMask, MVT::i8));<br>
+ DAG.getConstant(BlendMask, DL, MVT::i8));<br>
}<br>
}<br>
// FALLTHROUGH<br>
@@ -6357,7 +6363,8 @@ static SDValue lowerVectorShuffleAsBlend<br>
for (int j = 0; j < Scale; ++j)<br>
VSELECTMask.push_back(<br>
Mask[i] < 0 ? DAG.getUNDEF(MVT::i8)<br>
- : DAG.getConstant(Mask[i] < Size ? -1 : 0, MVT::i8));<br>
+ : DAG.getConstant(Mask[i] < Size ? -1 : 0, DL,<br>
+ MVT::i8));<br>
<br>
V1 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V1);<br>
V2 = DAG.getNode(ISD::BITCAST, DL, BlendVT, V2);<br>
@@ -6551,7 +6558,8 @@ static SDValue lowerVectorShuffleAsByteR<br>
<br>
return DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::PALIGNR, DL, AlignVT, Hi, Lo,<br>
- DAG.getConstant(Rotation * Scale, MVT::i8)));<br>
+ DAG.getConstant(Rotation * Scale, DL,<br>
+ MVT::i8)));<br>
}<br>
<br>
assert(VT.getSizeInBits() == 128 &&<br>
@@ -6568,9 +6576,9 @@ static SDValue lowerVectorShuffleAsByteR<br>
Hi = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Hi);<br>
<br>
SDValue LoShift = DAG.getNode(X86ISD::VSHLDQ, DL, MVT::v2i64, Lo,<br>
- DAG.getConstant(LoByteShift, MVT::i8));<br>
+ DAG.getConstant(LoByteShift, DL, MVT::i8));<br>
SDValue HiShift = DAG.getNode(X86ISD::VSRLDQ, DL, MVT::v2i64, Hi,<br>
- DAG.getConstant(HiByteShift, MVT::i8));<br>
+ DAG.getConstant(HiByteShift, DL, MVT::i8));<br>
return DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(ISD::OR, DL, MVT::v2i64, LoShift, HiShift));<br>
}<br>
@@ -6629,8 +6637,9 @@ static SDValue lowerVectorShuffleAsBitMa<br>
MVT EltVT = VT.getScalarType();<br>
int NumEltBits = EltVT.getSizeInBits();<br>
MVT IntEltVT = MVT::getIntegerVT(NumEltBits);<br>
- SDValue Zero = DAG.getConstant(0, IntEltVT);<br>
- SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), IntEltVT);<br>
+ SDValue Zero = DAG.getConstant(0, DL, IntEltVT);<br>
+ SDValue AllOnes = DAG.getConstant(APInt::getAllOnesValue(NumEltBits), DL,<br>
+ IntEltVT);<br>
if (EltVT.isFloatingPoint()) {<br>
Zero = DAG.getNode(ISD::BITCAST, DL, EltVT, Zero);<br>
AllOnes = DAG.getNode(ISD::BITCAST, DL, EltVT, AllOnes);<br>
@@ -6727,7 +6736,8 @@ static SDValue lowerVectorShuffleAsShift<br>
"Illegal integer vector type");<br>
V = DAG.getNode(ISD::BITCAST, DL, ShiftVT, V);<br>
<br>
- V = DAG.getNode(OpCode, DL, ShiftVT, V, DAG.getConstant(ShiftAmt, MVT::i8));<br>
+ V = DAG.getNode(OpCode, DL, ShiftVT, V,<br>
+ DAG.getConstant(ShiftAmt, DL, MVT::i8));<br>
return DAG.getNode(ISD::BITCAST, DL, VT, V);<br>
};<br>
<br>
@@ -6781,19 +6791,19 @@ static SDValue lowerVectorShuffleAsSpeci<br>
ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,<br>
DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),<br>
- getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));<br>
}<br>
if (AnyExt && EltBits == 16 && Scale > 2) {<br>
int PSHUFDMask[4] = {0, -1, 0, -1};<br>
InputV = DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32,<br>
DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, InputV),<br>
- getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG));<br>
int PSHUFHWMask[4] = {1, -1, -1, -1};<br>
return DAG.getNode(<br>
ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::PSHUFHW, DL, MVT::v8i16,<br>
DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, InputV),<br>
- getV4X86ShuffleImm8ForMask(PSHUFHWMask, DAG)));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFHWMask, DL, DAG)));<br>
}<br>
<br>
// If this would require more than 2 unpack instructions to expand, use<br>
@@ -6804,7 +6814,7 @@ static SDValue lowerVectorShuffleAsSpeci<br>
SDValue PSHUFBMask[16];<br>
for (int i = 0; i < 16; ++i)<br>
PSHUFBMask[i] =<br>
- DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, MVT::i8);<br>
+ DAG.getConstant((i % Scale == 0) ? i / Scale : 0x80, DL, MVT::i8);<br>
InputV = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, InputV);<br>
return DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::PSHUFB, DL, MVT::v16i8, InputV,<br>
@@ -7062,7 +7072,7 @@ static SDValue lowerVectorShuffleAsEleme<br>
V2 = DAG.getNode(<br>
X86ISD::VSHLDQ, DL, MVT::v2i64, V2,<br>
DAG.getConstant(<br>
- V2Index * EltVT.getSizeInBits()/8,<br>
+ V2Index * EltVT.getSizeInBits()/8, DL,<br>
DAG.getTargetLoweringInfo().getScalarShiftAmountTy(MVT::v2i64)));<br>
V2 = DAG.getNode(ISD::BITCAST, DL, VT, V2);<br>
}<br>
@@ -7222,7 +7232,7 @@ static SDValue lowerVectorShuffleAsInser<br>
// Insert the V2 element into the desired position.<br>
SDLoc DL(Op);<br>
return DAG.getNode(X86ISD::INSERTPS, DL, MVT::v4f32, V1, V2,<br>
- DAG.getConstant(InsertPSMask, MVT::i8));<br>
+ DAG.getConstant(InsertPSMask, DL, MVT::i8));<br>
}<br>
<br>
/// \brief Try to lower a shuffle as a permute of the inputs followed by an<br>
@@ -7372,11 +7382,11 @@ static SDValue lowerV2F64VectorShuffle(S<br>
// If we have AVX, we can use VPERMILPS which will allow folding a load<br>
// into the shuffle.<br>
return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v2f64, V1,<br>
- DAG.getConstant(SHUFPDMask, MVT::i8));<br>
+ DAG.getConstant(SHUFPDMask, DL, MVT::i8));<br>
}<br>
<br>
- return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V1,<br>
- DAG.getConstant(SHUFPDMask, MVT::i8));<br>
+ return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V1,<br>
+ DAG.getConstant(SHUFPDMask, DL, MVT::i8));<br>
}<br>
assert(Mask[0] >= 0 && Mask[0] < 2 && "Non-canonicalized blend!");<br>
assert(Mask[1] >= 2 && "Non-canonicalized blend!");<br>
@@ -7419,8 +7429,8 @@ static SDValue lowerV2F64VectorShuffle(S<br>
return DAG.getNode(X86ISD::UNPCKH, DL, MVT::v2f64, V1, V2);<br>
<br>
unsigned SHUFPDMask = (Mask[0] == 1) | (((Mask[1] - 2) == 1) << 1);<br>
- return DAG.getNode(X86ISD::SHUFP, SDLoc(Op), MVT::v2f64, V1, V2,<br>
- DAG.getConstant(SHUFPDMask, MVT::i8));<br>
+ return DAG.getNode(X86ISD::SHUFP, DL, MVT::v2f64, V1, V2,<br>
+ DAG.getConstant(SHUFPDMask, DL, MVT::i8));<br>
}<br>
<br>
/// \brief Handle lowering of 2-lane 64-bit integer shuffles.<br>
@@ -7455,8 +7465,8 @@ static SDValue lowerV2I64VectorShuffle(S<br>
std::max(Mask[1], 0) * 2, std::max(Mask[1], 0) * 2 + 1};<br>
return DAG.getNode(<br>
ISD::BITCAST, DL, MVT::v2i64,<br>
- DAG.getNode(X86ISD::PSHUFD, SDLoc(Op), MVT::v4i32, V1,<br>
- getV4X86ShuffleImm8ForMask(WidenedMask, DAG)));<br>
+ DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,<br>
+ getV4X86ShuffleImm8ForMask(WidenedMask, DL, DAG)));<br>
}<br>
assert(Mask[0] != -1 && "No undef lanes in multi-input v2 shuffles!");<br>
assert(Mask[1] != -1 && "No undef lanes in multi-input v2 shuffles!");<br>
@@ -7590,7 +7600,7 @@ static SDValue lowerVectorShuffleWithSHU<br>
int V1Index = V2AdjIndex;<br>
int BlendMask[4] = {Mask[V2Index] - 4, 0, Mask[V1Index], 0};<br>
V2 = DAG.getNode(X86ISD::SHUFP, DL, VT, V2, V1,<br>
- getV4X86ShuffleImm8ForMask(BlendMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));<br>
<br>
// Now proceed to reconstruct the final blend as we have the necessary<br>
// high or low half formed.<br>
@@ -7629,7 +7639,7 @@ static SDValue lowerVectorShuffleWithSHU<br>
(Mask[0] >= 4 ? Mask[0] : Mask[1]) - 4,<br>
(Mask[2] >= 4 ? Mask[2] : Mask[3]) - 4};<br>
V1 = DAG.getNode(X86ISD::SHUFP, DL, VT, V1, V2,<br>
- getV4X86ShuffleImm8ForMask(BlendMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(BlendMask, DL, DAG));<br>
<br>
// Now we do a normal shuffle of V1 by giving V1 as both operands to<br>
// a blend.<br>
@@ -7641,7 +7651,7 @@ static SDValue lowerVectorShuffleWithSHU<br>
}<br>
}<br>
return DAG.getNode(X86ISD::SHUFP, DL, VT, LowV, HighV,<br>
- getV4X86ShuffleImm8ForMask(NewMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(NewMask, DL, DAG));<br>
}<br>
<br>
/// \brief Lower 4-lane 32-bit floating point shuffles.<br>
@@ -7681,13 +7691,13 @@ static SDValue lowerV4F32VectorShuffle(S<br>
// If we have AVX, we can use VPERMILPS which will allow folding a load<br>
// into the shuffle.<br>
return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f32, V1,<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
}<br>
<br>
// Otherwise, use a straight shuffle of a single input vector. We pass the<br>
// input vector to both operands to simulate this with a SHUFPS.<br>
return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f32, V1, V1,<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
}<br>
<br>
// There are special ways we can lower some single-element blends. However, we<br>
@@ -7773,7 +7783,7 @@ static SDValue lowerV4I32VectorShuffle(S<br>
Mask = UnpackHiMask;<br>
<br>
return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v4i32, V1,<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
}<br>
<br>
// Try to use shift instructions.<br>
@@ -7990,7 +8000,7 @@ static SDValue lowerV8I16GeneralSingleIn<br>
std::swap(PSHUFHalfMask[FixFreeIdx % 4], PSHUFHalfMask[FixIdx % 4]);<br>
V = DAG.getNode(FixIdx < 4 ? X86ISD::PSHUFLW : X86ISD::PSHUFHW, DL,<br>
MVT::v8i16, V,<br>
- getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFHalfMask, DL, DAG));<br>
<br>
for (int &M : Mask)<br>
if (M != -1 && M == FixIdx)<br>
@@ -8017,7 +8027,8 @@ static SDValue lowerV8I16GeneralSingleIn<br>
V = DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,<br>
DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),<br>
- getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,<br>
+ DAG)));<br>
<br>
// Adjust the mask to match the new locations of A and B.<br>
for (int &M : Mask)<br>
@@ -8253,15 +8264,16 @@ static SDValue lowerV8I16GeneralSingleIn<br>
// target half.<br>
if (!isNoopShuffleMask(PSHUFLMask))<br>
V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,<br>
- getV4X86ShuffleImm8ForMask(PSHUFLMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFLMask, DL, DAG));<br>
if (!isNoopShuffleMask(PSHUFHMask))<br>
V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,<br>
- getV4X86ShuffleImm8ForMask(PSHUFHMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFHMask, DL, DAG));<br>
if (!isNoopShuffleMask(PSHUFDMask))<br>
V = DAG.getNode(ISD::BITCAST, DL, VT,<br>
DAG.getNode(X86ISD::PSHUFD, DL, PSHUFDVT,<br>
DAG.getNode(ISD::BITCAST, DL, PSHUFDVT, V),<br>
- getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFDMask, DL,<br>
+ DAG)));<br>
<br>
// At this point, each half should contain all its inputs, and we can then<br>
// just shuffle them into their final position.<br>
@@ -8275,7 +8287,7 @@ static SDValue lowerV8I16GeneralSingleIn<br>
// Do a half shuffle for the low mask.<br>
if (!isNoopShuffleMask(LoMask))<br>
V = DAG.getNode(X86ISD::PSHUFLW, DL, VT, V,<br>
- getV4X86ShuffleImm8ForMask(LoMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(LoMask, DL, DAG));<br>
<br>
// Do a half shuffle with the high mask after shifting its values down.<br>
for (int &M : HiMask)<br>
@@ -8283,7 +8295,7 @@ static SDValue lowerV8I16GeneralSingleIn<br>
M -= 4;<br>
if (!isNoopShuffleMask(HiMask))<br>
V = DAG.getNode(X86ISD::PSHUFHW, DL, VT, V,<br>
- getV4X86ShuffleImm8ForMask(HiMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(HiMask, DL, DAG));<br>
<br>
return V;<br>
}<br>
@@ -8313,8 +8325,8 @@ static SDValue lowerVectorShuffleAsPSHUF<br>
: (Mask[i / Scale] - Size) * Scale + i % Scale;<br>
if (Zeroable[i / Scale])<br>
V1Idx = V2Idx = ZeroMask;<br>
- V1Mask[i] = DAG.getConstant(V1Idx, MVT::i8);<br>
- V2Mask[i] = DAG.getConstant(V2Idx, MVT::i8);<br>
+ V1Mask[i] = DAG.getConstant(V1Idx, DL, MVT::i8);<br>
+ V2Mask[i] = DAG.getConstant(V2Idx, DL, MVT::i8);<br>
V1InUse |= (ZeroMask != V1Idx);<br>
V2InUse |= (ZeroMask != V2Idx);<br>
}<br>
@@ -8757,7 +8769,7 @@ static SDValue lowerV16I8VectorShuffle(S<br>
MVT MaskVTs[] = { MVT::v8i16, MVT::v4i32, MVT::v2i64 };<br>
SDValue ByteClearMask =<br>
DAG.getNode(ISD::BITCAST, DL, MVT::v16i8,<br>
- DAG.getConstant(0xFF, MaskVTs[NumEvenDrops - 1]));<br>
+ DAG.getConstant(0xFF, DL, MaskVTs[NumEvenDrops - 1]));<br>
V1 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V1, ByteClearMask);<br>
if (!IsSingleInput)<br>
V2 = DAG.getNode(ISD::AND, DL, MVT::v16i8, V2, ByteClearMask);<br>
@@ -8803,7 +8815,7 @@ static SDValue lowerV16I8VectorShuffle(S<br>
// Use a mask to drop the high bytes.<br>
VLoHalf = DAG.getNode(ISD::BITCAST, DL, MVT::v8i16, V);<br>
VLoHalf = DAG.getNode(ISD::AND, DL, MVT::v8i16, VLoHalf,<br>
- DAG.getConstant(0x00FF, MVT::v8i16));<br>
+ DAG.getConstant(0x00FF, DL, MVT::v8i16));<br>
<br>
// This will be a single vector shuffle instead of a blend so nuke VHiHalf.<br>
VHiHalf = DAG.getUNDEF(MVT::v8i16);<br>
@@ -8949,9 +8961,9 @@ static SDValue splitAndLowerVectorShuffl<br>
auto *BV = dyn_cast<BuildVectorSDNode>(V);<br>
if (!BV) {<br>
LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigSplitVT, V,<br>
- DAG.getIntPtrConstant(OrigSplitNumElements));<br>
+ DAG.getIntPtrConstant(OrigSplitNumElements, DL));<br>
} else {<br>
<br>
SmallVector<SDValue, 16> LoOps, HiOps;<br>
@@ -9140,7 +9152,7 @@ static SDValue lowerVectorShuffleAsLaneP<br>
// allow folding it into a memory operand.<br>
unsigned PERMMask = 3 | 2 << 4;<br>
SDValue Flipped = DAG.getNode(X86ISD::VPERM2X128, DL, VT, DAG.getUNDEF(VT),<br>
- V1, DAG.getConstant(PERMMask, MVT::i8));<br>
+ V1, DAG.getConstant(PERMMask, DL, MVT::i8));<br>
return DAG.getVectorShuffle(VT, DL, V1, Flipped, FlippedBlendMask);<br>
}<br>
<br>
@@ -9177,9 +9189,10 @@ static SDValue lowerV2X128VectorShuffle(<br>
MVT SubVT = MVT::getVectorVT(VT.getVectorElementType(),<br>
VT.getVectorNumElements() / 2);<br>
SDValue LoV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, V1,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
SDValue HiV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT,<br>
- OnlyUsesV1 ? V1 : V2, DAG.getIntPtrConstant(0));<br>
+ OnlyUsesV1 ? V1 : V2,<br>
+ DAG.getIntPtrConstant(0, DL));<br>
return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoV, HiV);<br>
}<br>
}<br>
@@ -9228,7 +9241,7 @@ static SDValue lowerV2X128VectorShuffle(<br>
}<br>
<br>
return DAG.getNode(X86ISD::VPERM2X128, DL, VT, V1, V2,<br>
- DAG.getConstant(PermMask, MVT::i8));<br>
+ DAG.getConstant(PermMask, DL, MVT::i8));<br>
}<br>
<br>
/// \brief Lower a vector shuffle by first fixing the 128-bit lanes and then<br>
@@ -9364,13 +9377,13 @@ static SDValue lowerV4F64VectorShuffle(S<br>
unsigned VPERMILPMask = (Mask[0] == 1) | ((Mask[1] == 1) << 1) |<br>
((Mask[2] == 3) << 2) | ((Mask[3] == 3) << 3);<br>
return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v4f64, V1,<br>
- DAG.getConstant(VPERMILPMask, MVT::i8));<br>
+ DAG.getConstant(VPERMILPMask, DL, MVT::i8));<br>
}<br>
<br>
// With AVX2 we have direct support for this permutation.<br>
if (Subtarget->hasAVX2())<br>
return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4f64, V1,<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
<br>
// Otherwise, fall back.<br>
return lowerVectorShuffleAsLanePermuteAndBlend(DL, MVT::v4f64, V1, V2, Mask,<br>
@@ -9400,7 +9413,7 @@ static SDValue lowerV4F64VectorShuffle(S<br>
unsigned SHUFPDMask = (Mask[0] == 1) | ((Mask[1] == 5) << 1) |<br>
((Mask[2] == 3) << 2) | ((Mask[3] == 7) << 3);<br>
return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V1, V2,<br>
- DAG.getConstant(SHUFPDMask, MVT::i8));<br>
+ DAG.getConstant(SHUFPDMask, DL, MVT::i8));<br>
}<br>
if ((Mask[0] == -1 || (Mask[0] >= 4 && Mask[0] < 6)) &&<br>
(Mask[1] == -1 || Mask[1] < 2) &&<br>
@@ -9409,7 +9422,7 @@ static SDValue lowerV4F64VectorShuffle(S<br>
unsigned SHUFPDMask = (Mask[0] == 5) | ((Mask[1] == 1) << 1) |<br>
((Mask[2] == 7) << 2) | ((Mask[3] == 3) << 3);<br>
return DAG.getNode(X86ISD::SHUFP, DL, MVT::v4f64, V2, V1,<br>
- DAG.getConstant(SHUFPDMask, MVT::i8));<br>
+ DAG.getConstant(SHUFPDMask, DL, MVT::i8));<br>
}<br>
<br>
// Try to simplify this by merging 128-bit lanes to enable a lane-based<br>
@@ -9476,7 +9489,7 @@ static SDValue lowerV4I64VectorShuffle(S<br>
ISD::BITCAST, DL, MVT::v4i64,<br>
DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32,<br>
DAG.getNode(ISD::BITCAST, DL, MVT::v8i32, V1),<br>
- getV4X86ShuffleImm8ForMask(PSHUFDMask, DAG)));<br>
+ getV4X86ShuffleImm8ForMask(PSHUFDMask, DL, DAG)));<br>
}<br>
}<br>
<br>
@@ -9484,7 +9497,7 @@ static SDValue lowerV4I64VectorShuffle(S<br>
// lanes.<br>
if (isSingleInputShuffleMask(Mask))<br>
return DAG.getNode(X86ISD::VPERMI, DL, MVT::v4i64, V1,<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
<br>
// Try to use shift instructions.<br>
if (SDValue Shift =<br>
@@ -9554,7 +9567,7 @@ static SDValue lowerV8F32VectorShuffle(S<br>
<br>
if (isSingleInputShuffleMask(Mask))<br>
return DAG.getNode(X86ISD::VPERMILPI, DL, MVT::v8f32, V1,<br>
- getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));<br>
<br>
// Use dedicated unpack instructions for masks that match their pattern.<br>
if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))<br>
@@ -9581,7 +9594,7 @@ static SDValue lowerV8F32VectorShuffle(S<br>
SDValue VPermMask[8];<br>
for (int i = 0; i < 8; ++i)<br>
VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)<br>
- : DAG.getConstant(Mask[i], MVT::i32);<br>
+ : DAG.getConstant(Mask[i], DL, MVT::i32);<br>
if (!is128BitLaneCrossingShuffleMask(MVT::v8f32, Mask))<br>
return DAG.getNode(<br>
X86ISD::VPERMILPV, DL, MVT::v8f32, V1,<br>
@@ -9654,7 +9667,7 @@ static SDValue lowerV8I32VectorShuffle(S<br>
assert(RepeatedMask.size() == 4 && "Unexpected repeated mask size!");<br>
if (isSingleInputShuffleMask(Mask))<br>
return DAG.getNode(X86ISD::PSHUFD, DL, MVT::v8i32, V1,<br>
- getV4X86ShuffleImm8ForMask(RepeatedMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(RepeatedMask, DL, DAG));<br>
<br>
// Use dedicated unpack instructions for masks that match their pattern.<br>
if (isShuffleEquivalent(V1, V2, Mask, {0, 8, 1, 9, 4, 12, 5, 13}))<br>
@@ -9682,7 +9695,7 @@ static SDValue lowerV8I32VectorShuffle(S<br>
SDValue VPermMask[8];<br>
for (int i = 0; i < 8; ++i)<br>
VPermMask[i] = Mask[i] < 0 ? DAG.getUNDEF(MVT::i32)<br>
- : DAG.getConstant(Mask[i], MVT::i32);<br>
+ : DAG.getConstant(Mask[i], DL, MVT::i32);<br>
return DAG.getNode(<br>
X86ISD::VPERMV, DL, MVT::v8i32,<br>
DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i32, VPermMask), V1);<br>
@@ -9779,8 +9792,8 @@ static SDValue lowerV16I16VectorShuffle(<br>
<br>
int M = i < 8 ? Mask[i] : Mask[i] - 8;<br>
assert(M >= 0 && M < 8 && "Invalid single-input mask!");<br>
- PSHUFBMask[2 * i] = DAG.getConstant(2 * M, MVT::i8);<br>
- PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, MVT::i8);<br>
+ PSHUFBMask[2 * i] = DAG.getConstant(2 * M, DL, MVT::i8);<br>
+ PSHUFBMask[2 * i + 1] = DAG.getConstant(2 * M + 1, DL, MVT::i8);<br>
}<br>
return DAG.getNode(<br>
ISD::BITCAST, DL, MVT::v16i16,<br>
@@ -9871,7 +9884,8 @@ static SDValue lowerV32I8VectorShuffle(S<br>
PSHUFBMask[i] =<br>
Mask[i] < 0<br>
? DAG.getUNDEF(MVT::i8)<br>
- : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, MVT::i8);<br>
+ : DAG.getConstant(Mask[i] < 16 ? Mask[i] : Mask[i] - 16, DL,<br>
+ MVT::i8);<br>
<br>
return DAG.getNode(<br>
X86ISD::PSHUFB, DL, MVT::v32i8, V1,<br>
@@ -10469,11 +10483,11 @@ X86TargetLowering::ExtractBitFromMaskVec<br>
rc = getRegClassFor(MVT::v16i1);<br>
unsigned MaxSift = rc->getSize()*8 - 1;<br>
Vec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, Vec,<br>
- DAG.getConstant(MaxSift - IdxVal, MVT::i8));<br>
+ DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));<br>
Vec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, Vec,<br>
- DAG.getConstant(MaxSift, MVT::i8));<br>
+ DAG.getConstant(MaxSift, dl, MVT::i8));<br>
return DAG.getNode(X86ISD::VEXTRACT, dl, MVT::i1, Vec,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
SDValue<br>
@@ -10500,10 +10514,10 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E<br>
Idx = DAG.getZExtOrTrunc(Idx, dl, MaskEltVT);<br>
SDValue Mask = DAG.getNode(X86ISD::VINSERT, dl, MaskVT,<br>
getZeroVector(MaskVT, Subtarget, DAG, dl),<br>
- Idx, DAG.getConstant(0, getPointerTy()));<br>
+ Idx, DAG.getConstant(0, dl, getPointerTy()));<br>
SDValue Perm = DAG.getNode(X86ISD::VPERMV, dl, VecVT, Mask, Vec);<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(),<br>
- Perm, DAG.getConstant(0, getPointerTy()));<br>
+ Perm, DAG.getConstant(0, dl, getPointerTy()));<br>
}<br>
return SDValue();<br>
}<br>
@@ -10523,7 +10537,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E<br>
// IdxVal -= NumElems/2;<br>
IdxVal -= (IdxVal/ElemsPerChunk)*ElemsPerChunk;<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec,<br>
- DAG.getConstant(IdxVal, MVT::i32));<br>
+ DAG.getConstant(IdxVal, dl, MVT::i32));<br>
}<br>
<br>
assert(VecVT.is128BitVector() && "Unexpected vector length");<br>
@@ -10565,7 +10579,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E<br>
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),<br>
DAG.getUNDEF(VVT), Mask);<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
if (VT.getSizeInBits() == 64) {<br>
@@ -10584,7 +10598,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_E<br>
SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0),<br>
DAG.getUNDEF(VVT), Mask);<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
return SDValue();<br>
@@ -10615,13 +10629,13 @@ X86TargetLowering::InsertBitToMaskVector<br>
SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);<br>
if (Vec.getOpcode() == ISD::UNDEF)<br>
return DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,<br>
- DAG.getConstant(IdxVal, MVT::i8));<br>
+ DAG.getConstant(IdxVal, dl, MVT::i8));<br>
const TargetRegisterClass* rc = getRegClassFor(VecVT);<br>
unsigned MaxSift = rc->getSize()*8 - 1;<br>
EltInVec = DAG.getNode(X86ISD::VSHLI, dl, VecVT, EltInVec,<br>
- DAG.getConstant(MaxSift, MVT::i8));<br>
+ DAG.getConstant(MaxSift, dl, MVT::i8));<br>
EltInVec = DAG.getNode(X86ISD::VSRLI, dl, VecVT, EltInVec,<br>
- DAG.getConstant(MaxSift - IdxVal, MVT::i8));<br>
+ DAG.getConstant(MaxSift - IdxVal, dl, MVT::i8));<br>
return DAG.getNode(ISD::OR, dl, VecVT, Vec, EltInVec);<br>
}<br>
<br>
@@ -10654,7 +10668,7 @@ SDValue X86TargetLowering::LowerINSERT_V<br>
if ((Subtarget->hasAVX() && (EltVT == MVT::f64 || EltVT == MVT::f32)) ||<br>
(Subtarget->hasAVX2() && EltVT == MVT::i32)) {<br>
SDValue N1Vec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, N1);<br>
- N2 = DAG.getIntPtrConstant(1);<br>
+ N2 = DAG.getIntPtrConstant(1, dl);<br>
return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1Vec, N2);<br>
}<br>
}<br>
@@ -10667,7 +10681,7 @@ SDValue X86TargetLowering::LowerINSERT_V<br>
unsigned IdxIn128 = IdxVal - (IdxVal / NumEltsIn128) * NumEltsIn128;<br>
<br>
V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, N1,<br>
- DAG.getConstant(IdxIn128, MVT::i32));<br>
+ DAG.getConstant(IdxIn128, dl, MVT::i32));<br>
<br>
// Insert the changed part back into the bigger vector<br>
return Insert128BitVector(N0, V, IdxVal, DAG, dl);<br>
@@ -10689,7 +10703,7 @@ SDValue X86TargetLowering::LowerINSERT_V<br>
if (N1.getValueType() != MVT::i32)<br>
N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);<br>
if (N2.getValueType() != MVT::i32)<br>
- N2 = DAG.getIntPtrConstant(IdxVal);<br>
+ N2 = DAG.getIntPtrConstant(IdxVal, dl);<br>
return DAG.getNode(Opc, dl, VT, N0, N1, N2);<br>
}<br>
<br>
@@ -10713,11 +10727,11 @@ SDValue X86TargetLowering::LowerINSERT_V<br>
// But if optimizing for size and there's a load folding opportunity,<br>
// generate insertps because blendps does not have a 32-bit memory<br>
// operand form.<br>
- N2 = DAG.getIntPtrConstant(1);<br>
+ N2 = DAG.getIntPtrConstant(1, dl);<br>
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);<br>
return DAG.getNode(X86ISD::BLENDI, dl, VT, N0, N1, N2);<br>
}<br>
- N2 = DAG.getIntPtrConstant(IdxVal << 4);<br>
+ N2 = DAG.getIntPtrConstant(IdxVal << 4, dl);<br>
// Create this as a scalar to vector..<br>
N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1);<br>
return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2);<br>
@@ -10738,7 +10752,7 @@ SDValue X86TargetLowering::LowerINSERT_V<br>
if (N1.getValueType() != MVT::i32)<br>
N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1);<br>
if (N2.getValueType() != MVT::i32)<br>
- N2 = DAG.getIntPtrConstant(IdxVal);<br>
+ N2 = DAG.getIntPtrConstant(IdxVal, dl);<br>
return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2);<br>
}<br>
return SDValue();<br>
@@ -10847,10 +10861,10 @@ static SDValue LowerINSERT_SUBVECTOR(SDV<br>
if (OpVT.getVectorElementType() == MVT::i1) {<br>
if (IdxVal == 0 && Vec.getOpcode() == ISD::UNDEF) // the operation is legal<br>
return Op;<br>
- SDValue ZeroIdx = DAG.getIntPtrConstant(0);<br>
+ SDValue ZeroIdx = DAG.getIntPtrConstant(0, dl);<br>
SDValue Undef = DAG.getUNDEF(OpVT);<br>
unsigned NumElems = OpVT.getVectorNumElements();<br>
- SDValue ShiftBits = DAG.getConstant(NumElems/2, MVT::i8);<br>
+ SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8);<br>
<br>
if (IdxVal == OpVT.getVectorNumElements() / 2) {<br>
// Zero upper bits of the Vec<br>
@@ -11065,7 +11079,7 @@ X86TargetLowering::LowerGlobalAddress(co<br>
// addition for it.<br>
if (Offset != 0)<br>
Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,<br>
- DAG.getConstant(Offset, getPointerTy()));<br>
+ DAG.getConstant(Offset, dl, getPointerTy()));<br>
<br>
return Result;<br>
}<br>
@@ -11180,7 +11194,7 @@ static SDValue LowerToTLSExecModel(Globa<br>
is64Bit ? 257 : 256));<br>
<br>
SDValue ThreadPointer =<br>
- DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0),<br>
+ DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), DAG.getIntPtrConstant(0, dl),<br>
MachinePointerInfo(Ptr), false, false, false, 0);<br>
<br>
unsigned char OperandFlags = 0;<br>
@@ -11322,9 +11336,9 @@ X86TargetLowering::LowerGlobalTLSAddress<br>
<br>
SDValue TlsArray =<br>
Subtarget->is64Bit()<br>
- ? DAG.getIntPtrConstant(0x58)<br>
+ ? DAG.getIntPtrConstant(0x58, dl)<br>
: (Subtarget->isTargetWindowsGNU()<br>
- ? DAG.getIntPtrConstant(0x2C)<br>
+ ? DAG.getIntPtrConstant(0x2C, dl)<br>
: DAG.getExternalSymbol("_tls_array", getPointerTy()));<br>
<br>
SDValue ThreadPointer =<br>
@@ -11341,7 +11355,7 @@ X86TargetLowering::LowerGlobalTLSAddress<br>
IDX = DAG.getLoad(getPointerTy(), dl, Chain, IDX, MachinePointerInfo(),<br>
false, false, false, 0);<br>
<br>
- SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()),<br>
+ SDValue Scale = DAG.getConstant(Log2_64_Ceil(TD->getPointerSize()), dl,<br>
getPointerTy());<br>
IDX = DAG.getNode(ISD::SHL, dl, getPointerTy(), IDX, Scale);<br>
<br>
@@ -11378,10 +11392,10 @@ static SDValue LowerShiftParts(SDValue O<br>
// generic ISD nodes haven't. Insert an AND to be safe, it's optimized away<br>
// during isel.<br>
SDValue SafeShAmt = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,<br>
- DAG.getConstant(VTBits - 1, MVT::i8));<br>
+ DAG.getConstant(VTBits - 1, dl, MVT::i8));<br>
SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi,<br>
- DAG.getConstant(VTBits - 1, MVT::i8))<br>
- : DAG.getConstant(0, VT);<br>
+ DAG.getConstant(VTBits - 1, dl, MVT::i8))<br>
+ : DAG.getConstant(0, dl, VT);<br>
<br>
SDValue Tmp2, Tmp3;<br>
if (Op.getOpcode() == ISD::SHL_PARTS) {<br>
@@ -11396,12 +11410,12 @@ static SDValue LowerShiftParts(SDValue O<br>
// rely on the results of shld/shrd. Insert a test and select the appropriate<br>
// values for large shift amounts.<br>
SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt,<br>
- DAG.getConstant(VTBits, MVT::i8));<br>
+ DAG.getConstant(VTBits, dl, MVT::i8));<br>
SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32,<br>
- AndNode, DAG.getConstant(0, MVT::i8));<br>
+ AndNode, DAG.getConstant(0, dl, MVT::i8));<br>
<br>
SDValue Hi, Lo;<br>
- SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8);<br>
+ SDValue CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);<br>
SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond };<br>
SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };<br>
<br>
@@ -11580,7 +11594,7 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
}<br>
<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Result,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
// LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion.<br>
@@ -11588,7 +11602,7 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
SelectionDAG &DAG) const {<br>
SDLoc dl(Op);<br>
// FP constant to bias correct the final result.<br>
- SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),<br>
+ SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,<br>
MVT::f64);<br>
<br>
// Load the 32-bit value into an XMM register.<br>
@@ -11600,7 +11614,7 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
<br>
Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,<br>
DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
<br>
// Or the load with the bias.<br>
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64,<br>
@@ -11612,7 +11626,7 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
MVT::v2f64, Bias)));<br>
Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64,<br>
DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
<br>
// Subtract the bias.<br>
SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias);<br>
@@ -11622,7 +11636,7 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
<br>
if (DestVT.bitsLT(MVT::f64))<br>
return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
if (DestVT.bitsGT(MVT::f64))<br>
return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);<br>
<br>
@@ -11667,20 +11681,20 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV<br>
// -- v >> 16<br>
<br>
// Create the splat vector for 0x4b000000.<br>
- SDValue CstLow = DAG.getConstant(0x4b000000, MVT::i32);<br>
+ SDValue CstLow = DAG.getConstant(0x4b000000, DL, MVT::i32);<br>
SDValue CstLowArray[] = {CstLow, CstLow, CstLow, CstLow,<br>
CstLow, CstLow, CstLow, CstLow};<br>
SDValue VecCstLow = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,<br>
makeArrayRef(&CstLowArray[0], NumElts));<br>
// Create the splat vector for 0x53000000.<br>
- SDValue CstHigh = DAG.getConstant(0x53000000, MVT::i32);<br>
+ SDValue CstHigh = DAG.getConstant(0x53000000, DL, MVT::i32);<br>
SDValue CstHighArray[] = {CstHigh, CstHigh, CstHigh, CstHigh,<br>
CstHigh, CstHigh, CstHigh, CstHigh};<br>
SDValue VecCstHigh = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,<br>
makeArrayRef(&CstHighArray[0], NumElts));<br>
<br>
// Create the right shift.<br>
- SDValue CstShift = DAG.getConstant(16, MVT::i32);<br>
+ SDValue CstShift = DAG.getConstant(16, DL, MVT::i32);<br>
SDValue CstShiftArray[] = {CstShift, CstShift, CstShift, CstShift,<br>
CstShift, CstShift, CstShift, CstShift};<br>
SDValue VecCstShift = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT,<br>
@@ -11697,7 +11711,7 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV<br>
// Low will be bitcasted right away, so do not bother bitcasting back to its<br>
// original type.<br>
Low = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecBitcast,<br>
- VecCstLowBitcast, DAG.getConstant(0xaa, MVT::i32));<br>
+ VecCstLowBitcast, DAG.getConstant(0xaa, DL, MVT::i32));<br>
// uint4 hi = _mm_blend_epi16( _mm_srli_epi32(v,16),<br>
// (uint4) 0x53000000, 0xaa);<br>
SDValue VecCstHighBitcast =<br>
@@ -11707,9 +11721,9 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV<br>
// High will be bitcasted right away, so do not bother bitcasting back to<br>
// its original type.<br>
High = DAG.getNode(X86ISD::BLENDI, DL, VecI16VT, VecShiftBitcast,<br>
- VecCstHighBitcast, DAG.getConstant(0xaa, MVT::i32));<br>
+ VecCstHighBitcast, DAG.getConstant(0xaa, DL, MVT::i32));<br>
} else {<br>
- SDValue CstMask = DAG.getConstant(0xffff, MVT::i32);<br>
+ SDValue CstMask = DAG.getConstant(0xffff, DL, MVT::i32);<br>
SDValue VecCstMask = DAG.getNode(ISD::BUILD_VECTOR, DL, VecIntVT, CstMask,<br>
CstMask, CstMask, CstMask);<br>
// uint4 lo = (v & (uint4) 0xffff) | (uint4) 0x4b000000;<br>
@@ -11722,7 +11736,7 @@ static SDValue lowerUINT_TO_FP_vXi32(SDV<br>
<br>
// Create the vector constant for -(0x1.0p39f + 0x1.0p23f).<br>
SDValue CstFAdd = DAG.getConstantFP(<br>
- APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), MVT::f32);<br>
+ APFloat(APFloat::IEEEsingle, APInt(32, 0xD3000080)), DL, MVT::f32);<br>
SDValue CstFAddArray[] = {CstFAdd, CstFAdd, CstFAdd, CstFAdd,<br>
CstFAdd, CstFAdd, CstFAdd, CstFAdd};<br>
SDValue VecCstFAdd = DAG.getNode(ISD::BUILD_VECTOR, DL, VecFloatVT,<br>
@@ -11787,13 +11801,13 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
// Make a 64-bit buffer, and use it to build an FILD.<br>
SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64);<br>
if (SrcVT == MVT::i32) {<br>
- SDValue WordOff = DAG.getConstant(4, getPointerTy());<br>
+ SDValue WordOff = DAG.getConstant(4, dl, getPointerTy());<br>
SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl,<br>
getPointerTy(), StackSlot, WordOff);<br>
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),<br>
StackSlot, MachinePointerInfo(),<br>
false, false, 0);<br>
- SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32),<br>
+ SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, dl, MVT::i32),<br>
OffsetSlot, MachinePointerInfo(),<br>
false, false, 0);<br>
SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG);<br>
@@ -11825,8 +11839,8 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
// Check whether the sign bit is set.<br>
SDValue SignSet = DAG.getSetCC(dl,<br>
getSetCCResultType(*DAG.getContext(), MVT::i64),<br>
- Op.getOperand(0), DAG.getConstant(0, MVT::i64),<br>
- ISD::SETLT);<br>
+ Op.getOperand(0),<br>
+ DAG.getConstant(0, dl, MVT::i64), ISD::SETLT);<br>
<br>
// Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits.<br>
SDValue FudgePtr = DAG.getConstantPool(<br>
@@ -11834,8 +11848,8 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
getPointerTy());<br>
<br>
// Get a pointer to FF if the sign bit was set, or to 0 otherwise.<br>
- SDValue Zero = DAG.getIntPtrConstant(0);<br>
- SDValue Four = DAG.getIntPtrConstant(4);<br>
+ SDValue Zero = DAG.getIntPtrConstant(0, dl);<br>
+ SDValue Four = DAG.getIntPtrConstant(4, dl);<br>
SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet,<br>
Zero, Four);<br>
FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset);<br>
@@ -11847,7 +11861,8 @@ SDValue X86TargetLowering::LowerUINT_TO_<br>
MVT::f32, false, false, false, 4);<br>
// Extend everything to 80 bits to force it to be done on x87.<br>
SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge);<br>
- return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0));<br>
+ return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add,<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
std::pair<SDValue,SDValue><br>
@@ -12003,7 +12018,7 @@ static SDValue LowerZERO_EXTEND_AVX512(<br>
const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
// Now we have only mask extension<br>
assert(InVT.getVectorElementType() == MVT::i1);<br>
- SDValue Cst = DAG.getTargetConstant(1, ExtVT.getScalarType());<br>
+ SDValue Cst = DAG.getTargetConstant(1, DL, ExtVT.getScalarType());<br>
const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();<br>
SDValue CP = DAG.getConstantPool(C, TLI.getPointerTy());<br>
unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();<br>
@@ -12096,7 +12111,7 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
InVT = ExtVT;<br>
}<br>
<br>
- SDValue Cst = DAG.getTargetConstant(1, InVT.getVectorElementType());<br>
+ SDValue Cst = DAG.getTargetConstant(1, DL, InVT.getVectorElementType());<br>
const Constant *C = cast<ConstantSDNode>(Cst)->getConstantIntValue();<br>
SDValue CP = DAG.getConstantPool(C, getPointerTy());<br>
unsigned Alignment = cast<ConstantPoolSDNode>(CP)->getAlignment();<br>
@@ -12116,13 +12131,13 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
In = DAG.getVectorShuffle(MVT::v8i32, DL, In, DAG.getUNDEF(MVT::v8i32),<br>
ShufMask);<br>
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, In,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
}<br>
<br>
SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,<br>
- DAG.getIntPtrConstant(2));<br>
+ DAG.getIntPtrConstant(2, DL));<br>
OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpLo);<br>
OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v4i32, OpHi);<br>
static const int ShufMask[] = {0, 2, 4, 6};<br>
@@ -12136,16 +12151,16 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
<br>
SmallVector<SDValue,32> pshufbMask;<br>
for (unsigned i = 0; i < 2; ++i) {<br>
- pshufbMask.push_back(DAG.getConstant(0x0, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0x1, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0x4, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0x5, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0x8, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0x9, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0xc, MVT::i8));<br>
- pshufbMask.push_back(DAG.getConstant(0xd, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x0, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x1, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x4, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x5, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x8, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x9, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0xc, DL, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0xd, DL, MVT::i8));<br>
for (unsigned j = 0; j < 8; ++j)<br>
- pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8));<br>
+ pshufbMask.push_back(DAG.getConstant(0x80, DL, MVT::i8));<br>
}<br>
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v32i8, pshufbMask);<br>
In = DAG.getNode(X86ISD::PSHUFB, DL, MVT::v32i8, In, BV);<br>
@@ -12155,15 +12170,15 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
In = DAG.getVectorShuffle(MVT::v4i64, DL, In, DAG.getUNDEF(MVT::v4i64),<br>
&ShufMask[0]);<br>
In = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v2i64, In,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
return DAG.getNode(ISD::BITCAST, DL, VT, In);<br>
}<br>
<br>
SDValue OpLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
<br>
SDValue OpHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i32, In,<br>
- DAG.getIntPtrConstant(4));<br>
+ DAG.getIntPtrConstant(4, DL));<br>
<br>
OpLo = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpLo);<br>
OpHi = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, OpHi);<br>
@@ -12202,7 +12217,7 @@ SDValue X86TargetLowering::LowerTRUNCATE<br>
DAG.getNode(ISD::BITCAST, DL, NVT, In),<br>
DAG.getUNDEF(NVT), &MaskVec[0]);<br>
return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, V,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
}<br>
<br>
SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op,<br>
@@ -12339,7 +12354,7 @@ static SDValue LowerFCOPYSIGN(SDValue Op<br>
}<br>
// And if it is bigger, shrink it first.<br>
if (SrcVT.bitsGT(VT)) {<br>
- Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1));<br>
+ Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1, dl));<br>
SrcVT = VT;<br>
}<br>
<br>
@@ -12398,8 +12413,8 @@ static SDValue LowerFGETSIGN(SDValue Op,<br>
<br>
// Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1).<br>
SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0,<br>
- DAG.getConstant(1, VT));<br>
- return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT));<br>
+ DAG.getConstant(1, dl, VT));<br>
+ return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, dl, VT));<br>
}<br>
<br>
// Check whether an OR'd tree is PTEST-able.<br>
@@ -12520,7 +12535,7 @@ SDValue X86TargetLowering::EmitTest(SDVa<br>
if (Op.getValueType() == MVT::i1) {<br>
SDValue ExtOp = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, Op);<br>
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, ExtOp,<br>
- DAG.getConstant(0, MVT::i8));<br>
+ DAG.getConstant(0, dl, MVT::i8));<br>
}<br>
// CF and OF aren't always set the way we want. Determine which<br>
// of these we need.<br>
@@ -12564,7 +12579,7 @@ SDValue X86TargetLowering::EmitTest(SDVa<br>
// return DAG.getNode(X86ISD::CMP, dl, MVT::i1, Op,<br>
// DAG.getConstant(0, MVT::i1));<br>
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,<br>
- DAG.getConstant(0, Op.getValueType()));<br>
+ DAG.getConstant(0, dl, Op.getValueType()));<br>
}<br>
unsigned Opcode = 0;<br>
unsigned NumOperands = 0;<br>
@@ -12652,7 +12667,7 @@ SDValue X86TargetLowering::EmitTest(SDVa<br>
if (!Mask.isSignedIntN(32)) // Avoid large immediates.<br>
break;<br>
SDValue New = DAG.getNode(ISD::AND, dl, VT, Op->getOperand(0),<br>
- DAG.getConstant(Mask, VT));<br>
+ DAG.getConstant(Mask, dl, VT));<br>
DAG.ReplaceAllUsesWith(Op, New);<br>
Op = New;<br>
}<br>
@@ -12738,7 +12753,7 @@ SDValue X86TargetLowering::EmitTest(SDVa<br>
if (Opcode == 0)<br>
// Emit a CMP with 0, which is the TEST pattern.<br>
return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op,<br>
- DAG.getConstant(0, Op.getValueType()));<br>
+ DAG.getConstant(0, dl, Op.getValueType()));<br>
<br>
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);<br>
SmallVector<SDValue, 4> Ops(Op->op_begin(), Op->op_begin() + NumOperands);<br>
@@ -12803,7 +12818,7 @@ SDValue X86TargetLowering::ConvertCmpIfN<br>
SDValue TruncFPSW = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, Cmp);<br>
SDValue FNStSW = DAG.getNode(X86ISD::FNSTSW16r, dl, MVT::i16, TruncFPSW);<br>
SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW,<br>
- DAG.getConstant(8, MVT::i8));<br>
+ DAG.getConstant(8, dl, MVT::i8));<br>
SDValue TruncSrl = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Srl);<br>
return DAG.getNode(X86ISD::SAHF, dl, MVT::i32, TruncSrl);<br>
}<br>
@@ -12926,7 +12941,7 @@ SDValue X86TargetLowering::LowerToBT(SDV<br>
// Use BT if the immediate can't be encoded in a TEST instruction.<br>
if (!isUInt<32>(AndRHSVal) && isPowerOf2_64(AndRHSVal)) {<br>
LHS = AndLHS;<br>
- RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), LHS.getValueType());<br>
+ RHS = DAG.getConstant(Log2_64_Ceil(AndRHSVal), dl, LHS.getValueType());<br>
}<br>
}<br>
<br>
@@ -12948,7 +12963,7 @@ SDValue X86TargetLowering::LowerToBT(SDV<br>
SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS);<br>
X86::CondCode Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B;<br>
return DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(Cond, MVT::i8), BT);<br>
+ DAG.getConstant(Cond, dl, MVT::i8), BT);<br>
}<br>
<br>
return SDValue();<br>
@@ -13040,16 +13055,16 @@ static SDValue LowerBoolVSETCC_AVX512(SD<br>
"Unexpected type for boolean compare operation");<br>
ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get();<br>
SDValue NotOp0 = DAG.getNode(ISD::XOR, dl, VT, Op0,<br>
- DAG.getConstant(-1, VT));<br>
+ DAG.getConstant(-1, dl, VT));<br>
SDValue NotOp1 = DAG.getNode(ISD::XOR, dl, VT, Op1,<br>
- DAG.getConstant(-1, VT));<br>
+ DAG.getConstant(-1, dl, VT));<br>
switch (SetCCOpcode) {<br>
default: llvm_unreachable("Unexpected SETCC condition");<br>
case ISD::SETNE:<br>
// (x != y) -> ~(x ^ y)<br>
return DAG.getNode(ISD::XOR, dl, VT,<br>
DAG.getNode(ISD::XOR, dl, VT, Op0, Op1),<br>
- DAG.getConstant(-1, VT));<br>
+ DAG.getConstant(-1, dl, VT));<br>
case ISD::SETEQ:<br>
// (x == y) -> (x ^ y)<br>
return DAG.getNode(ISD::XOR, dl, VT, Op0, Op1);<br>
@@ -13109,7 +13124,7 @@ static SDValue LowerIntVSETCC_AVX512(SDV<br>
return DAG.getNode(Opc, dl, VT, Op0, Op1);<br>
Opc = Unsigned ? X86ISD::CMPMU: X86ISD::CMPM;<br>
return DAG.getNode(Opc, dl, VT, Op0, Op1,<br>
- DAG.getConstant(SSECC, MVT::i8));<br>
+ DAG.getConstant(SSECC, dl, MVT::i8));<br>
}<br>
<br>
/// \brief Try to turn a VSETULT into a VSETULE by modifying its second<br>
@@ -13136,7 +13151,7 @@ static SDValue ChangeVSETULTtoVSETULE(SD<br>
if (Val == 0)<br>
return SDValue();<br>
<br>
- ULTOp1.push_back(DAG.getConstant(Val - 1, EVT));<br>
+ ULTOp1.push_back(DAG.getConstant(Val - 1, dl, EVT));<br>
}<br>
<br>
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, ULTOp1);<br>
@@ -13176,14 +13191,14 @@ static SDValue LowerVSETCC(SDValue Op, c<br>
}<br>
<br>
SDValue Cmp0 = DAG.getNode(Opc, dl, VT, Op0, Op1,<br>
- DAG.getConstant(CC0, MVT::i8));<br>
+ DAG.getConstant(CC0, dl, MVT::i8));<br>
SDValue Cmp1 = DAG.getNode(Opc, dl, VT, Op0, Op1,<br>
- DAG.getConstant(CC1, MVT::i8));<br>
+ DAG.getConstant(CC1, dl, MVT::i8));<br>
return DAG.getNode(CombineOpc, dl, VT, Cmp0, Cmp1);<br>
}<br>
// Handle all other FP comparisons here.<br>
return DAG.getNode(Opc, dl, VT, Op0, Op1,<br>
- DAG.getConstant(SSECC, MVT::i8));<br>
+ DAG.getConstant(SSECC, dl, MVT::i8));<br>
}<br>
<br>
// Break 256-bit integer vector compare into smaller ones.<br>
@@ -13304,10 +13319,10 @@ static SDValue LowerVSETCC(SDValue Op, c<br>
// compare is always unsigned.<br>
SDValue SB;<br>
if (FlipSigns) {<br>
- SB = DAG.getConstant(0x80000000U, MVT::v4i32);<br>
+ SB = DAG.getConstant(0x80000000U, dl, MVT::v4i32);<br>
} else {<br>
- SDValue Sign = DAG.getConstant(0x80000000U, MVT::i32);<br>
- SDValue Zero = DAG.getConstant(0x00000000U, MVT::i32);<br>
+ SDValue Sign = DAG.getConstant(0x80000000U, dl, MVT::i32);<br>
+ SDValue Zero = DAG.getConstant(0x00000000U, dl, MVT::i32);<br>
SB = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,<br>
Sign, Zero, Sign, Zero);<br>
}<br>
@@ -13362,7 +13377,8 @@ static SDValue LowerVSETCC(SDValue Op, c<br>
// bits of the inputs before performing those operations.<br>
if (FlipSigns) {<br>
EVT EltVT = VT.getVectorElementType();<br>
- SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), VT);<br>
+ SDValue SB = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), dl,<br>
+ VT);<br>
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SB);<br>
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SB);<br>
}<br>
@@ -13430,7 +13446,7 @@ SDValue X86TargetLowering::LowerSETCC(SD<br>
<br>
CCode = X86::GetOppositeBranchCondition(CCode);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(CCode, MVT::i8),<br>
+ DAG.getConstant(CCode, dl, MVT::i8),<br>
Op0.getOperand(1));<br>
if (VT == MVT::i1)<br>
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);<br>
@@ -13442,18 +13458,18 @@ SDValue X86TargetLowering::LowerSETCC(SD<br>
(CC == ISD::SETEQ || CC == ISD::SETNE)) {<br>
<br>
ISD::CondCode NewCC = ISD::getSetCCInverse(CC, true);<br>
- return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, MVT::i1), NewCC);<br>
+ return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, MVT::i1), NewCC);<br>
}<br>
<br>
bool isFP = Op1.getSimpleValueType().isFloatingPoint();<br>
- unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG);<br>
+ unsigned X86CC = TranslateX86CC(CC, dl, isFP, Op0, Op1, DAG);<br>
if (X86CC == X86::COND_INVALID)<br>
return SDValue();<br>
<br>
SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, dl, DAG);<br>
EFLAGS = ConvertCmpIfNecessary(EFLAGS, DAG);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86CC, MVT::i8), EFLAGS);<br>
+ DAG.getConstant(X86CC, dl, MVT::i8), EFLAGS);<br>
if (VT == MVT::i1)<br>
return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, SetCC);<br>
return SetCC;<br>
@@ -13518,12 +13534,12 @@ SDValue X86TargetLowering::LowerSELECT(S<br>
if (SSECC != 8) {<br>
if (Subtarget->hasAVX512()) {<br>
SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CondOp0, CondOp1,<br>
- DAG.getConstant(SSECC, MVT::i8));<br>
+ DAG.getConstant(SSECC, DL, MVT::i8));<br>
return DAG.getNode(X86ISD::SELECT, DL, VT, Cmp, Op1, Op2);<br>
}<br>
<br>
SDValue Cmp = DAG.getNode(X86ISD::FSETCC, DL, VT, CondOp0, CondOp1,<br>
- DAG.getConstant(SSECC, MVT::i8));<br>
+ DAG.getConstant(SSECC, DL, MVT::i8));<br>
<br>
// If we have AVX, we can use a variable vector select (VBLENDV) instead<br>
// of 3 logic instructions for size savings and potentially speed.<br>
@@ -13555,7 +13571,7 @@ SDValue X86TargetLowering::LowerSELECT(S<br>
SDValue VSel = DAG.getNode(ISD::VSELECT, DL, VecVT, VCmp, VOp1, VOp2);<br>
<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT,<br>
- VSel, DAG.getIntPtrConstant(0));<br>
+ VSel, DAG.getIntPtrConstant(0, DL));<br>
}<br>
SDValue AndN = DAG.getNode(X86ISD::FANDN, DL, VT, Cmp, Op2);<br>
SDValue And = DAG.getNode(X86ISD::FAND, DL, VT, Cmp, Op1);<br>
@@ -13593,21 +13609,22 @@ SDValue X86TargetLowering::LowerSELECT(S<br>
(isAllOnes(Op1) == (CondCode == X86::COND_NE))) {<br>
SDVTList VTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);<br>
SDValue Neg = DAG.getNode(X86ISD::SUB, DL, VTs,<br>
- DAG.getConstant(0, CmpOp0.getValueType()),<br>
+ DAG.getConstant(0, DL,<br>
+ CmpOp0.getValueType()),<br>
CmpOp0);<br>
SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),<br>
- DAG.getConstant(X86::COND_B, MVT::i8),<br>
+ DAG.getConstant(X86::COND_B, DL, MVT::i8),<br>
SDValue(Neg.getNode(), 1));<br>
return Res;<br>
}<br>
<br>
Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32,<br>
- CmpOp0, DAG.getConstant(1, CmpOp0.getValueType()));<br>
+ CmpOp0, DAG.getConstant(1, DL, CmpOp0.getValueType()));<br>
Cmp = ConvertCmpIfNecessary(Cmp, DAG);<br>
<br>
SDValue Res = // Res = 0 or -1.<br>
DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),<br>
- DAG.getConstant(X86::COND_B, MVT::i8), Cmp);<br>
+ DAG.getConstant(X86::COND_B, DL, MVT::i8), Cmp);<br>
<br>
if (isAllOnes(Op1) != (CondCode == X86::COND_E))<br>
Res = DAG.getNOT(DL, Res, Res.getValueType());<br>
@@ -13679,7 +13696,7 @@ SDValue X86TargetLowering::LowerSELECT(S<br>
else<br>
Cond = X86Op.getValue(1);<br>
<br>
- CC = DAG.getConstant(X86Cond, MVT::i8);<br>
+ CC = DAG.getConstant(X86Cond, DL, MVT::i8);<br>
addTest = false;<br>
}<br>
<br>
@@ -13701,7 +13718,7 @@ SDValue X86TargetLowering::LowerSELECT(S<br>
}<br>
<br>
if (addTest) {<br>
- CC = DAG.getConstant(X86::COND_NE, MVT::i8);<br>
+ CC = DAG.getConstant(X86::COND_NE, DL, MVT::i8);<br>
Cond = EmitTest(Cond, X86::COND_NE, DL, DAG);<br>
}<br>
<br>
@@ -13716,7 +13733,8 @@ SDValue X86TargetLowering::LowerSELECT(S<br>
if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&<br>
(isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) {<br>
SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(),<br>
- DAG.getConstant(X86::COND_B, MVT::i8), Cond);<br>
+ DAG.getConstant(X86::COND_B, DL, MVT::i8),<br>
+ Cond);<br>
if (isAllOnes(Op1) != (CondCode == X86::COND_B))<br>
return DAG.getNOT(DL, Res, Res.getValueType());<br>
return Res;<br>
@@ -13976,7 +13994,7 @@ static SDValue LowerExtendedLoad(SDValue<br>
SmallVector<SDValue, 8> Chains;<br>
SDValue Ptr = Ld->getBasePtr();<br>
SDValue Increment =<br>
- DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, TLI.getPointerTy());<br>
+ DAG.getConstant(SclrLoadTy.getSizeInBits() / 8, dl, TLI.getPointerTy());<br>
SDValue Res = DAG.getUNDEF(LoadUnitVecVT);<br>
<br>
for (unsigned i = 0; i < NumLoads; ++i) {<br>
@@ -13992,7 +14010,7 @@ static SDValue LowerExtendedLoad(SDValue<br>
Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoadUnitVecVT, ScalarLoad);<br>
else<br>
Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, LoadUnitVecVT, Res,<br>
- ScalarLoad, DAG.getIntPtrConstant(i));<br>
+ ScalarLoad, DAG.getIntPtrConstant(i, dl));<br>
<br>
Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);<br>
}<br>
@@ -14032,7 +14050,8 @@ static SDValue LowerExtendedLoad(SDValue<br>
unsigned Amt = RegVT.getVectorElementType().getSizeInBits() -<br>
MemVT.getVectorElementType().getSizeInBits();<br>
Shuff =<br>
- DAG.getNode(ISD::SRA, dl, RegVT, Shuff, DAG.getConstant(Amt, RegVT));<br>
+ DAG.getNode(ISD::SRA, dl, RegVT, Shuff,<br>
+ DAG.getConstant(Amt, dl, RegVT));<br>
<br>
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), TF);<br>
return Shuff;<br>
@@ -14199,7 +14218,7 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
else<br>
Cond = X86Op.getValue(1);<br>
<br>
- CC = DAG.getConstant(X86Cond, MVT::i8);<br>
+ CC = DAG.getConstant(X86Cond, dl, MVT::i8);<br>
addTest = false;<br>
} else {<br>
unsigned CondOpc;<br>
@@ -14230,7 +14249,7 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
X86::CondCode CCode =<br>
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);<br>
CCode = X86::GetOppositeBranchCondition(CCode);<br>
- CC = DAG.getConstant(CCode, MVT::i8);<br>
+ CC = DAG.getConstant(CCode, dl, MVT::i8);<br>
SDNode *User = *Op.getNode()->use_begin();<br>
// Look for an unconditional branch following this conditional branch.<br>
// We need this because we need to reverse the successors in order<br>
@@ -14248,7 +14267,7 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
X86::CondCode CCode =<br>
(X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0);<br>
CCode = X86::GetOppositeBranchCondition(CCode);<br>
- CC = DAG.getConstant(CCode, MVT::i8);<br>
+ CC = DAG.getConstant(CCode, dl, MVT::i8);<br>
Cond = Cmp;<br>
addTest = false;<br>
}<br>
@@ -14261,7 +14280,7 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
X86::CondCode CCode =<br>
(X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0);<br>
CCode = X86::GetOppositeBranchCondition(CCode);<br>
- CC = DAG.getConstant(CCode, MVT::i8);<br>
+ CC = DAG.getConstant(CCode, dl, MVT::i8);<br>
Cond = Cond.getOperand(0).getOperand(1);<br>
addTest = false;<br>
} else if (Cond.getOpcode() == ISD::SETCC &&<br>
@@ -14287,10 +14306,10 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,<br>
Cond.getOperand(0), Cond.getOperand(1));<br>
Cmp = ConvertCmpIfNecessary(Cmp, DAG);<br>
- CC = DAG.getConstant(X86::COND_NE, MVT::i8);<br>
+ CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);<br>
Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),<br>
Chain, Dest, CC, Cmp);<br>
- CC = DAG.getConstant(X86::COND_P, MVT::i8);<br>
+ CC = DAG.getConstant(X86::COND_P, dl, MVT::i8);<br>
Cond = Cmp;<br>
addTest = false;<br>
}<br>
@@ -14317,10 +14336,10 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
SDValue Cmp = DAG.getNode(X86ISD::CMP, dl, MVT::i32,<br>
Cond.getOperand(0), Cond.getOperand(1));<br>
Cmp = ConvertCmpIfNecessary(Cmp, DAG);<br>
- CC = DAG.getConstant(X86::COND_NE, MVT::i8);<br>
+ CC = DAG.getConstant(X86::COND_NE, dl, MVT::i8);<br>
Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(),<br>
Chain, Dest, CC, Cmp);<br>
- CC = DAG.getConstant(X86::COND_NP, MVT::i8);<br>
+ CC = DAG.getConstant(X86::COND_NP, dl, MVT::i8);<br>
Cond = Cmp;<br>
addTest = false;<br>
Dest = FalseBB;<br>
@@ -14348,7 +14367,7 @@ SDValue X86TargetLowering::LowerBRCOND(S<br>
<br>
if (addTest) {<br>
X86::CondCode X86Cond = Inverted ? X86::COND_E : X86::COND_NE;<br>
- CC = DAG.getConstant(X86Cond, MVT::i8);<br>
+ CC = DAG.getConstant(X86Cond, dl, MVT::i8);<br>
Cond = EmitTest(Cond, X86Cond, dl, DAG);<br>
}<br>
Cond = ConvertCmpIfNecessary(Cond, DAG);<br>
@@ -14385,7 +14404,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALL<br>
<br>
// Chain the dynamic stack allocation so that it doesn't modify the stack<br>
// pointer when other instructions are using the stack.<br>
- Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true),<br>
+ Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, dl, true),<br>
SDLoc(Node));<br>
<br>
SDValue Size = Tmp2.getOperand(1);<br>
@@ -14397,11 +14416,11 @@ X86TargetLowering::LowerDYNAMIC_STACKALL<br>
Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value<br>
if (Align > StackAlign)<br>
Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,<br>
- DAG.getConstant(-(uint64_t)Align, VT));<br>
+ DAG.getConstant(-(uint64_t)Align, dl, VT));<br>
Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain<br>
<br>
- Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true),<br>
- DAG.getIntPtrConstant(0, true), SDValue(),<br>
+ Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),<br>
+ DAG.getIntPtrConstant(0, dl, true), SDValue(),<br>
SDLoc(Node));<br>
<br>
SDValue Ops[2] = { Tmp1, Tmp2 };<br>
@@ -14457,7 +14476,7 @@ X86TargetLowering::LowerDYNAMIC_STACKALL<br>
<br>
if (Align) {<br>
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),<br>
- DAG.getConstant(-(uint64_t)Align, VT));<br>
+ DAG.getConstant(-(uint64_t)Align, dl, VT));<br>
Chain = DAG.getCopyToReg(Chain, dl, SPReg, SP);<br>
}<br>
<br>
@@ -14492,22 +14511,22 @@ SDValue X86TargetLowering::LowerVASTART(<br>
// Store gp_offset<br>
SDValue Store = DAG.getStore(Op.getOperand(0), DL,<br>
DAG.getConstant(FuncInfo->getVarArgsGPOffset(),<br>
- MVT::i32),<br>
+ DL, MVT::i32),<br>
FIN, MachinePointerInfo(SV), false, false, 0);<br>
MemOps.push_back(Store);<br>
<br>
// Store fp_offset<br>
FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),<br>
- FIN, DAG.getIntPtrConstant(4));<br>
+ FIN, DAG.getIntPtrConstant(4, DL));<br>
Store = DAG.getStore(Op.getOperand(0), DL,<br>
- DAG.getConstant(FuncInfo->getVarArgsFPOffset(),<br>
+ DAG.getConstant(FuncInfo->getVarArgsFPOffset(), DL,<br>
MVT::i32),<br>
FIN, MachinePointerInfo(SV, 4), false, false, 0);<br>
MemOps.push_back(Store);<br>
<br>
// Store ptr to overflow_arg_area<br>
FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),<br>
- FIN, DAG.getIntPtrConstant(4));<br>
+ FIN, DAG.getIntPtrConstant(4, DL));<br>
SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),<br>
getPointerTy());<br>
Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN,<br>
@@ -14517,7 +14536,7 @@ SDValue X86TargetLowering::LowerVASTART(<br>
<br>
// Store ptr to reg_save_area.<br>
FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(),<br>
- FIN, DAG.getIntPtrConstant(8));<br>
+ FIN, DAG.getIntPtrConstant(8, DL));<br>
SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(),<br>
getPointerTy());<br>
Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN,<br>
@@ -14567,9 +14586,9 @@ SDValue X86TargetLowering::LowerVAARG(SD<br>
<br>
// Insert VAARG_64 node into the DAG<br>
// VAARG_64 returns two values: Variable Argument Address, Chain<br>
- SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, MVT::i32),<br>
- DAG.getConstant(ArgMode, MVT::i8),<br>
- DAG.getConstant(Align, MVT::i32)};<br>
+ SDValue InstOps[] = {Chain, SrcPtr, DAG.getConstant(ArgSize, dl, MVT::i32),<br>
+ DAG.getConstant(ArgMode, dl, MVT::i8),<br>
+ DAG.getConstant(Align, dl, MVT::i32)};<br>
SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other);<br>
SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl,<br>
VTs, InstOps, MVT::i64,<br>
@@ -14600,7 +14619,7 @@ static SDValue LowerVACOPY(SDValue Op, c<br>
SDLoc DL(Op);<br>
<br>
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,<br>
- DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,<br>
+ DAG.getIntPtrConstant(24, DL), 8, /*isVolatile*/false,<br>
false, false,<br>
MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));<br>
}<br>
@@ -14621,7 +14640,7 @@ static SDValue getTargetVShiftByConstNod<br>
if (Opc == X86ISD::VSRAI)<br>
ShiftAmt = ElementType.getSizeInBits() - 1;<br>
else<br>
- return DAG.getConstant(0, VT);<br>
+ return DAG.getConstant(0, dl, VT);<br>
}<br>
<br>
assert((Opc == X86ISD::VSHLI || Opc == X86ISD::VSRLI || Opc == X86ISD::VSRAI)<br>
@@ -14646,7 +14665,7 @@ static SDValue getTargetVShiftByConstNod<br>
}<br>
ND = cast<ConstantSDNode>(CurrentOp);<br>
const APInt &C = ND->getAPIntValue();<br>
- Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), ElementType));<br>
+ Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));<br>
}<br>
break;<br>
case X86ISD::VSRLI:<br>
@@ -14658,7 +14677,7 @@ static SDValue getTargetVShiftByConstNod<br>
}<br>
ND = cast<ConstantSDNode>(CurrentOp);<br>
const APInt &C = ND->getAPIntValue();<br>
- Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), ElementType));<br>
+ Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));<br>
}<br>
break;<br>
case X86ISD::VSRAI:<br>
@@ -14670,7 +14689,7 @@ static SDValue getTargetVShiftByConstNod<br>
}<br>
ND = cast<ConstantSDNode>(CurrentOp);<br>
const APInt &C = ND->getAPIntValue();<br>
- Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), ElementType));<br>
+ Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));<br>
}<br>
break;<br>
}<br>
@@ -14678,7 +14697,8 @@ static SDValue getTargetVShiftByConstNod<br>
return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);<br>
}<br>
<br>
- return DAG.getNode(Opc, dl, VT, SrcOp, DAG.getConstant(ShiftAmt, MVT::i8));<br>
+ return DAG.getNode(Opc, dl, VT, SrcOp,<br>
+ DAG.getConstant(ShiftAmt, dl, MVT::i8));<br>
}<br>
<br>
// getTargetVShiftNode - Handle vector element shifts where the shift amount<br>
@@ -14716,7 +14736,7 @@ static SDValue getTargetVShiftNode(unsig<br>
SmallVector<SDValue, 4> ShOps;<br>
ShOps.push_back(ShAmt);<br>
if (SVT == MVT::i32) {<br>
- ShOps.push_back(DAG.getConstant(0, SVT));<br>
+ ShOps.push_back(DAG.getConstant(0, dl, SVT));<br>
ShOps.push_back(DAG.getUNDEF(SVT));<br>
}<br>
ShOps.push_back(DAG.getUNDEF(SVT));<br>
@@ -14757,7 +14777,7 @@ static SDValue getVectorMaskingNode(SDVa<br>
// are extracted by EXTRACT_SUBVECTOR.<br>
SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
<br>
switch (Op.getOpcode()) {<br>
default: break;<br>
@@ -14915,22 +14935,23 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
Op.getOperand(2));<br>
}<br>
SDValue CmpMask = getVectorMaskingNode(Cmp, Mask,<br>
- DAG.getTargetConstant(0, MaskVT),<br>
+ DAG.getTargetConstant(0, dl,<br>
+ MaskVT),<br>
Subtarget, DAG);<br>
SDValue Res = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, BitcastVT,<br>
DAG.getUNDEF(BitcastVT), CmpMask,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);<br>
}<br>
case COMI: { // Comparison intrinsics<br>
ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;<br>
SDValue LHS = Op.getOperand(1);<br>
SDValue RHS = Op.getOperand(2);<br>
- unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);<br>
+ unsigned X86CC = TranslateX86CC(CC, dl, true, LHS, RHS, DAG);<br>
assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");<br>
SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86CC, MVT::i8), Cond);<br>
+ DAG.getConstant(X86CC, dl, MVT::i8), Cond);<br>
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);<br>
}<br>
case VSHIFT:<br>
@@ -14957,7 +14978,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
SDLoc dl(Op);<br>
SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
<br>
return DAG.getNode(IntrData->Opc0, dl, VT, VMask, DataToCompress,<br>
PassThru);<br>
@@ -14972,7 +14993,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
SDLoc dl(Op);<br>
SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
return DAG.getNode(IntrData->Opc0, dl, VT, VMask, Op.getOperand(1),<br>
Op.getOperand(2));<br>
}<br>
@@ -15062,7 +15083,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
SDValue RHS = Op.getOperand(2);<br>
unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST;<br>
SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS);<br>
- SDValue CC = DAG.getConstant(X86CC, MVT::i8);<br>
+ SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test);<br>
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);<br>
}<br>
@@ -15071,7 +15092,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
unsigned X86CC = (IntNo == Intrinsic::x86_avx512_kortestz_w)? X86::COND_E: X86::COND_B;<br>
SDValue LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(1));<br>
SDValue RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i1, Op.getOperand(2));<br>
- SDValue CC = DAG.getConstant(X86CC, MVT::i8);<br>
+ SDValue CC = DAG.getConstant(X86CC, dl, MVT::i8);<br>
SDValue Test = DAG.getNode(X86ISD::KORTEST, dl, MVT::i32, LHS, RHS);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i1, CC, Test);<br>
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);<br>
@@ -15136,7 +15157,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32);<br>
SDValue PCMP = DAG.getNode(Opcode, dl, VTs, NewOps);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86CC, MVT::i8),<br>
+ DAG.getConstant(X86CC, dl, MVT::i8),<br>
SDValue(PCMP.getNode(), 1));<br>
return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);<br>
}<br>
@@ -15163,17 +15184,17 @@ static SDValue getGatherNode(unsigned Op<br>
SDLoc dl(Op);<br>
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);<br>
assert(C && "Invalid scale type");<br>
- SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);<br>
+ SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);<br>
EVT MaskVT = MVT::getVectorVT(MVT::i1,<br>
Index.getSimpleValueType().getVectorNumElements());<br>
SDValue MaskInReg;<br>
ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);<br>
if (MaskC)<br>
- MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);<br>
+ MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);<br>
else<br>
MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);<br>
SDVTList VTs = DAG.getVTList(Op.getValueType(), MaskVT, MVT::Other);<br>
- SDValue Disp = DAG.getTargetConstant(0, MVT::i32);<br>
+ SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);<br>
SDValue Segment = DAG.getRegister(0, MVT::i32);<br>
if (Src.getOpcode() == ISD::UNDEF)<br>
Src = getZeroVector(Op.getValueType(), Subtarget, DAG, dl);<br>
@@ -15189,15 +15210,15 @@ static SDValue getScatterNode(unsigned O<br>
SDLoc dl(Op);<br>
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);<br>
assert(C && "Invalid scale type");<br>
- SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);<br>
- SDValue Disp = DAG.getTargetConstant(0, MVT::i32);<br>
+ SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);<br>
+ SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);<br>
SDValue Segment = DAG.getRegister(0, MVT::i32);<br>
EVT MaskVT = MVT::getVectorVT(MVT::i1,<br>
Index.getSimpleValueType().getVectorNumElements());<br>
SDValue MaskInReg;<br>
ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);<br>
if (MaskC)<br>
- MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);<br>
+ MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);<br>
else<br>
MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);<br>
SDVTList VTs = DAG.getVTList(MaskVT, MVT::Other);<br>
@@ -15212,15 +15233,15 @@ static SDValue getPrefetchNode(unsigned<br>
SDLoc dl(Op);<br>
ConstantSDNode *C = dyn_cast<ConstantSDNode>(ScaleOp);<br>
assert(C && "Invalid scale type");<br>
- SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), MVT::i8);<br>
- SDValue Disp = DAG.getTargetConstant(0, MVT::i32);<br>
+ SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);<br>
+ SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);<br>
SDValue Segment = DAG.getRegister(0, MVT::i32);<br>
EVT MaskVT =<br>
MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());<br>
SDValue MaskInReg;<br>
ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask);<br>
if (MaskC)<br>
- MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), MaskVT);<br>
+ MaskInReg = DAG.getTargetConstant(MaskC->getSExtValue(), dl, MaskVT);<br>
else<br>
MaskInReg = DAG.getNode(ISD::BITCAST, dl, MaskVT, Mask);<br>
//SDVTList VTs = DAG.getVTList(MVT::Other);<br>
@@ -15261,7 +15282,7 @@ static void getReadPerformanceCounter(SD<br>
// The EAX register is loaded with the low-order 32 bits. The EDX register<br>
// is loaded with the supported high-order bits of the counter.<br>
SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,<br>
- DAG.getConstant(32, MVT::i8));<br>
+ DAG.getConstant(32, DL, MVT::i8));<br>
Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));<br>
Results.push_back(Chain);<br>
return;<br>
@@ -15315,7 +15336,7 @@ static void getReadTimeStampCounter(SDNo<br>
// The EDX register is loaded with the high-order 32 bits of the MSR, and<br>
// the EAX register is loaded with the low-order 32 bits.<br>
SDValue Tmp = DAG.getNode(ISD::SHL, DL, MVT::i64, HI,<br>
- DAG.getConstant(32, MVT::i8));<br>
+ DAG.getConstant(32, DL, MVT::i8));<br>
Results.push_back(DAG.getNode(ISD::OR, DL, MVT::i64, LO, Tmp));<br>
Results.push_back(Chain);<br>
return;<br>
@@ -15360,8 +15381,8 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD<br>
// If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.<br>
// Otherwise return the value from Rand, which is always 0, casted to i32.<br>
SDValue Ops[] = { DAG.getZExtOrTrunc(Result, dl, Op->getValueType(1)),<br>
- DAG.getConstant(1, Op->getValueType(1)),<br>
- DAG.getConstant(X86::COND_B, MVT::i32),<br>
+ DAG.getConstant(1, dl, Op->getValueType(1)),<br>
+ DAG.getConstant(X86::COND_B, dl, MVT::i32),<br>
SDValue(Result.getNode(), 1) };<br>
SDValue isValid = DAG.getNode(X86ISD::CMOV, dl,<br>
DAG.getVTList(Op->getValueType(1), MVT::Glue),<br>
@@ -15421,7 +15442,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD<br>
SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);<br>
SDValue InTrans = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86::COND_NE, MVT::i8),<br>
+ DAG.getConstant(X86::COND_NE, dl, MVT::i8),<br>
InTrans);<br>
SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);<br>
return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),<br>
@@ -15433,14 +15454,14 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD<br>
SDVTList CFVTs = DAG.getVTList(Op->getValueType(0), MVT::Other);<br>
SDVTList VTs = DAG.getVTList(Op.getOperand(3)->getValueType(0), MVT::Other);<br>
SDValue GenCF = DAG.getNode(X86ISD::ADD, dl, CFVTs, Op.getOperand(2),<br>
- DAG.getConstant(-1, MVT::i8));<br>
+ DAG.getConstant(-1, dl, MVT::i8));<br>
SDValue Res = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(3),<br>
Op.getOperand(4), GenCF.getValue(1));<br>
SDValue Store = DAG.getStore(Op.getOperand(0), dl, Res.getValue(0),<br>
Op.getOperand(5), MachinePointerInfo(),<br>
false, false, 0);<br>
SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86::COND_B, MVT::i8),<br>
+ DAG.getConstant(X86::COND_B, dl, MVT::i8),<br>
Res.getValue(1));<br>
Results.push_back(SetCC);<br>
Results.push_back(Store);<br>
@@ -15464,7 +15485,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD<br>
Mask.getValueType().getSizeInBits());<br>
SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
<br>
SDValue Compressed = DAG.getNode(IntrData->Opc0, dl, VT, VMask,<br>
DataToCompress, DAG.getUNDEF(VT));<br>
@@ -15488,7 +15509,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SD<br>
Mask.getValueType().getSizeInBits());<br>
SDValue VMask = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MaskVT,<br>
DAG.getNode(ISD::BITCAST, dl, BitcastVT, Mask),<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
<br>
SDValue DataToExpand = DAG.getLoad(VT, dl, Chain, Addr, MachinePointerInfo(),<br>
false, false, false, 0);<br>
@@ -15516,7 +15537,7 @@ SDValue X86TargetLowering::LowerRETURNAD<br>
if (Depth > 0) {<br>
SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);<br>
const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
- SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), PtrVT);<br>
+ SDValue Offset = DAG.getConstant(RegInfo->getSlotSize(), dl, PtrVT);<br>
return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),<br>
DAG.getNode(ISD::ADD, dl, PtrVT,<br>
FrameAddr, Offset),<br>
@@ -15584,7 +15605,7 @@ unsigned X86TargetLowering::getRegisterB<br>
SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op,<br>
SelectionDAG &DAG) const {<br>
const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo();<br>
- return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize());<br>
+ return DAG.getIntPtrConstant(2 * RegInfo->getSlotSize(), SDLoc(Op));<br>
}<br>
<br>
SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {<br>
@@ -15603,7 +15624,8 @@ SDValue X86TargetLowering::LowerEH_RETUR<br>
unsigned StoreAddrReg = (PtrVT == MVT::i64) ? X86::RCX : X86::ECX;<br>
<br>
SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Frame,<br>
- DAG.getIntPtrConstant(RegInfo->getSlotSize()));<br>
+ DAG.getIntPtrConstant(RegInfo->getSlotSize(),<br>
+ dl));<br>
StoreAddr = DAG.getNode(ISD::ADD, dl, PtrVT, StoreAddr, Offset);<br>
Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(),<br>
false, false, 0);<br>
@@ -15658,12 +15680,12 @@ SDValue X86TargetLowering::LowerINIT_TRA<br>
// Load the pointer to the nested function into R11.<br>
unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11<br>
SDValue Addr = Trmp;<br>
- OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),<br>
+ OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),<br>
Addr, MachinePointerInfo(TrmpAddr),<br>
false, false, 0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,<br>
- DAG.getConstant(2, MVT::i64));<br>
+ DAG.getConstant(2, dl, MVT::i64));<br>
OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr,<br>
MachinePointerInfo(TrmpAddr, 2),<br>
false, false, 2);<br>
@@ -15672,13 +15694,13 @@ SDValue X86TargetLowering::LowerINIT_TRA<br>
// R10 is specified in X86CallingConv.td<br>
OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,<br>
- DAG.getConstant(10, MVT::i64));<br>
- OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),<br>
+ DAG.getConstant(10, dl, MVT::i64));<br>
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),<br>
Addr, MachinePointerInfo(TrmpAddr, 10),<br>
false, false, 0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,<br>
- DAG.getConstant(12, MVT::i64));<br>
+ DAG.getConstant(12, dl, MVT::i64));<br>
OutChains[3] = DAG.getStore(Root, dl, Nest, Addr,<br>
MachinePointerInfo(TrmpAddr, 12),<br>
false, false, 2);<br>
@@ -15686,16 +15708,16 @@ SDValue X86TargetLowering::LowerINIT_TRA<br>
// Jump to the nested function.<br>
OpCode = (JMP64r << 8) | REX_WB; // jmpq *...<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,<br>
- DAG.getConstant(20, MVT::i64));<br>
- OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16),<br>
+ DAG.getConstant(20, dl, MVT::i64));<br>
+ OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, dl, MVT::i16),<br>
Addr, MachinePointerInfo(TrmpAddr, 20),<br>
false, false, 0);<br>
<br>
unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,<br>
- DAG.getConstant(22, MVT::i64));<br>
- OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr,<br>
- MachinePointerInfo(TrmpAddr, 22),<br>
+ DAG.getConstant(22, dl, MVT::i64));<br>
+ OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, dl, MVT::i8),<br>
+ Addr, MachinePointerInfo(TrmpAddr, 22),<br>
false, false, 0);<br>
<br>
return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);<br>
@@ -15748,32 +15770,32 @@ SDValue X86TargetLowering::LowerINIT_TRA<br>
SDValue Addr, Disp;<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(10, MVT::i32));<br>
+ DAG.getConstant(10, dl, MVT::i32));<br>
Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr);<br>
<br>
// This is storing the opcode for MOV32ri.<br>
const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte.<br>
const unsigned char N86Reg = TRI->getEncodingValue(NestReg) & 0x7;<br>
OutChains[0] = DAG.getStore(Root, dl,<br>
- DAG.getConstant(MOV32ri|N86Reg, MVT::i8),<br>
+ DAG.getConstant(MOV32ri|N86Reg, dl, MVT::i8),<br>
Trmp, MachinePointerInfo(TrmpAddr),<br>
false, false, 0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(1, MVT::i32));<br>
+ DAG.getConstant(1, dl, MVT::i32));<br>
OutChains[1] = DAG.getStore(Root, dl, Nest, Addr,<br>
MachinePointerInfo(TrmpAddr, 1),<br>
false, false, 1);<br>
<br>
const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode.<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(5, MVT::i32));<br>
- OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr,<br>
- MachinePointerInfo(TrmpAddr, 5),<br>
+ DAG.getConstant(5, dl, MVT::i32));<br>
+ OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, dl, MVT::i8),<br>
+ Addr, MachinePointerInfo(TrmpAddr, 5),<br>
false, false, 1);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(6, MVT::i32));<br>
+ DAG.getConstant(6, dl, MVT::i32));<br>
OutChains[3] = DAG.getStore(Root, dl, Disp, Addr,<br>
MachinePointerInfo(TrmpAddr, 6),<br>
false, false, 1);<br>
@@ -15830,20 +15852,20 @@ SDValue X86TargetLowering::LowerFLT_ROUN<br>
SDValue CWD1 =<br>
DAG.getNode(ISD::SRL, DL, MVT::i16,<br>
DAG.getNode(ISD::AND, DL, MVT::i16,<br>
- CWD, DAG.getConstant(0x800, MVT::i16)),<br>
- DAG.getConstant(11, MVT::i8));<br>
+ CWD, DAG.getConstant(0x800, DL, MVT::i16)),<br>
+ DAG.getConstant(11, DL, MVT::i8));<br>
SDValue CWD2 =<br>
DAG.getNode(ISD::SRL, DL, MVT::i16,<br>
DAG.getNode(ISD::AND, DL, MVT::i16,<br>
- CWD, DAG.getConstant(0x400, MVT::i16)),<br>
- DAG.getConstant(9, MVT::i8));<br>
+ CWD, DAG.getConstant(0x400, DL, MVT::i16)),<br>
+ DAG.getConstant(9, DL, MVT::i8));<br>
<br>
SDValue RetVal =<br>
DAG.getNode(ISD::AND, DL, MVT::i16,<br>
DAG.getNode(ISD::ADD, DL, MVT::i16,<br>
DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2),<br>
- DAG.getConstant(1, MVT::i16)),<br>
- DAG.getConstant(3, MVT::i16));<br>
+ DAG.getConstant(1, DL, MVT::i16)),<br>
+ DAG.getConstant(3, DL, MVT::i16));<br>
<br>
return DAG.getNode((VT.getSizeInBits() < 16 ?<br>
ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal);<br>
@@ -15869,14 +15891,15 @@ static SDValue LowerCTLZ(SDValue Op, Sel<br>
// If src is zero (i.e. bsr sets ZF), returns NumBits.<br>
SDValue Ops[] = {<br>
Op,<br>
- DAG.getConstant(NumBits+NumBits-1, OpVT),<br>
- DAG.getConstant(X86::COND_E, MVT::i8),<br>
+ DAG.getConstant(NumBits + NumBits - 1, dl, OpVT),<br>
+ DAG.getConstant(X86::COND_E, dl, MVT::i8),<br>
Op.getValue(1)<br>
};<br>
Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops);<br>
<br>
// Finally xor with NumBits-1.<br>
- Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));<br>
+ Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,<br>
+ DAG.getConstant(NumBits - 1, dl, OpVT));<br>
<br>
if (VT == MVT::i8)<br>
Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);<br>
@@ -15901,7 +15924,8 @@ static SDValue LowerCTLZ_ZERO_UNDEF(SDVa<br>
Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);<br>
<br>
// And xor with NumBits-1.<br>
- Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT));<br>
+ Op = DAG.getNode(ISD::XOR, dl, OpVT, Op,<br>
+ DAG.getConstant(NumBits - 1, dl, OpVT));<br>
<br>
if (VT == MVT::i8)<br>
Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op);<br>
@@ -15921,8 +15945,8 @@ static SDValue LowerCTTZ(SDValue Op, Sel<br>
// If src is zero (i.e. bsf sets ZF), returns NumBits.<br>
SDValue Ops[] = {<br>
Op,<br>
- DAG.getConstant(NumBits, VT),<br>
- DAG.getConstant(X86::COND_E, MVT::i8),<br>
+ DAG.getConstant(NumBits, dl, VT),<br>
+ DAG.getConstant(X86::COND_E, dl, MVT::i8),<br>
Op.getValue(1)<br>
};<br>
return DAG.getNode(X86ISD::CMOV, dl, VT, Ops);<br>
@@ -15989,8 +16013,8 @@ static SDValue LowerMUL(SDValue Op, cons<br>
if (Subtarget->hasInt256()) {<br>
if (VT == MVT::v32i8) {<br>
MVT SubVT = MVT::getVectorVT(MVT::i8, VT.getVectorNumElements() / 2);<br>
- SDValue Lo = DAG.getIntPtrConstant(0);<br>
- SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2);<br>
+ SDValue Lo = DAG.getIntPtrConstant(0, dl);<br>
+ SDValue Hi = DAG.getIntPtrConstant(VT.getVectorNumElements() / 2, dl);<br>
SDValue ALo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Lo);<br>
SDValue BLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, B, Lo);<br>
SDValue AHi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, SubVT, A, Hi);<br>
@@ -16024,8 +16048,8 @@ static SDValue LowerMUL(SDValue Op, cons<br>
BLo = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);<br>
ALo = DAG.getNode(ISD::BITCAST, dl, ExVT, ALo);<br>
BLo = DAG.getNode(ISD::BITCAST, dl, ExVT, BLo);<br>
- ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, ExVT));<br>
- BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, ExVT));<br>
+ ALo = DAG.getNode(ISD::SRA, dl, ExVT, ALo, DAG.getConstant(8, dl, ExVT));<br>
+ BLo = DAG.getNode(ISD::SRA, dl, ExVT, BLo, DAG.getConstant(8, dl, ExVT));<br>
}<br>
<br>
// Extract the hi parts and sign extend to i16<br>
@@ -16044,15 +16068,15 @@ static SDValue LowerMUL(SDValue Op, cons<br>
BHi = DAG.getVectorShuffle(VT, dl, B, B, ShufMask);<br>
AHi = DAG.getNode(ISD::BITCAST, dl, ExVT, AHi);<br>
BHi = DAG.getNode(ISD::BITCAST, dl, ExVT, BHi);<br>
- AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, ExVT));<br>
- BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, ExVT));<br>
+ AHi = DAG.getNode(ISD::SRA, dl, ExVT, AHi, DAG.getConstant(8, dl, ExVT));<br>
+ BHi = DAG.getNode(ISD::SRA, dl, ExVT, BHi, DAG.getConstant(8, dl, ExVT));<br>
}<br>
<br>
// Multiply, mask the lower 8bits of the lo/hi results and pack<br>
SDValue RLo = DAG.getNode(ISD::MUL, dl, ExVT, ALo, BLo);<br>
SDValue RHi = DAG.getNode(ISD::MUL, dl, ExVT, AHi, BHi);<br>
- RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, ExVT));<br>
- RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, ExVT));<br>
+ RLo = DAG.getNode(ISD::AND, dl, ExVT, RLo, DAG.getConstant(255, dl, ExVT));<br>
+ RHi = DAG.getNode(ISD::AND, dl, ExVT, RHi, DAG.getConstant(255, dl, ExVT));<br>
return DAG.getNode(X86ISD::PACKUS, dl, VT, RLo, RHi);<br>
}<br>
<br>
@@ -16228,7 +16252,8 @@ static SDValue LowerMUL_LOHI(SDValue Op,<br>
// unsigned multiply.<br>
if (IsSigned && !Subtarget->hasSSE41()) {<br>
SDValue ShAmt =<br>
- DAG.getConstant(31, DAG.getTargetLoweringInfo().getShiftAmountTy(VT));<br>
+ DAG.getConstant(31, dl,<br>
+ DAG.getTargetLoweringInfo().getShiftAmountTy(VT));<br>
SDValue T1 = DAG.getNode(ISD::AND, dl, VT,<br>
DAG.getNode(ISD::SRA, dl, VT, Op0, ShAmt), Op1);<br>
SDValue T2 = DAG.getNode(ISD::AND, dl, VT,<br>
@@ -16283,7 +16308,7 @@ static SDValue LowerScalarImmediateShift<br>
SHL = DAG.getNode(ISD::BITCAST, dl, VT, SHL);<br>
// Zero out the rightmost bits.<br>
SmallVector<SDValue, 32> V(<br>
- NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), MVT::i8));<br>
+ NumElts, DAG.getConstant(uint8_t(-1U << ShiftAmt), dl, MVT::i8));<br>
return DAG.getNode(ISD::AND, dl, VT, SHL,<br>
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));<br>
}<br>
@@ -16294,7 +16319,7 @@ static SDValue LowerScalarImmediateShift<br>
SRL = DAG.getNode(ISD::BITCAST, dl, VT, SRL);<br>
// Zero out the leftmost bits.<br>
SmallVector<SDValue, 32> V(<br>
- NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, MVT::i8));<br>
+ NumElts, DAG.getConstant(uint8_t(-1U) >> ShiftAmt, dl, MVT::i8));<br>
return DAG.getNode(ISD::AND, dl, VT, SRL,<br>
DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V));<br>
}<br>
@@ -16308,7 +16333,8 @@ static SDValue LowerScalarImmediateShift<br>
// R s>> a === ((R u>> a) ^ m) - m<br>
SDValue Res = DAG.getNode(ISD::SRL, dl, VT, R, Amt);<br>
SmallVector<SDValue, 32> V(NumElts,<br>
- DAG.getConstant(128 >> ShiftAmt, MVT::i8));<br>
+ DAG.getConstant(128 >> ShiftAmt, dl,<br>
+ MVT::i8));<br>
SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, V);<br>
Res = DAG.getNode(ISD::XOR, dl, VT, Res, Mask);<br>
Res = DAG.getNode(ISD::SUB, dl, VT, Res, Mask);<br>
@@ -<a href="tel:16413" value="+4916413" target="_blank">16413</a>,7 +16439,7 @@ static SDValue LowerScalarVariableShift(<br>
if (!BaseShAmt)<br>
// Avoid introducing an extract element from a shuffle.<br>
BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InVec,<br>
- DAG.getIntPtrConstant(SplatIdx));<br>
+ DAG.getIntPtrConstant(SplatIdx, dl));<br>
}<br>
}<br>
<br>
@@ -16571,7 +16597,7 @@ static SDValue LowerShift(SDValue Op, co<br>
Elts.push_back(DAG.getUNDEF(SVT));<br>
continue;<br>
}<br>
- Elts.push_back(DAG.getConstant(One.shl(ShAmt), SVT));<br>
+ Elts.push_back(DAG.getConstant(One.shl(ShAmt), dl, SVT));<br>
}<br>
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Elts);<br>
return DAG.getNode(ISD::MUL, dl, VT, R, BV);<br>
@@ -16579,9 +16605,10 @@ static SDValue LowerShift(SDValue Op, co<br>
<br>
// Lower SHL with variable shift amount.<br>
if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) {<br>
- Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, VT));<br>
+ Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(23, dl, VT));<br>
<br>
- Op = DAG.getNode(ISD::ADD, dl, VT, Op, DAG.getConstant(0x3f800000U, VT));<br>
+ Op = DAG.getNode(ISD::ADD, dl, VT, Op,<br>
+ DAG.getConstant(0x3f800000U, dl, VT));<br>
Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op);<br>
Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op);<br>
return DAG.getNode(ISD::MUL, dl, VT, Op, R);<br>
@@ -16645,10 +16672,10 @@ static SDValue LowerShift(SDValue Op, co<br>
// Replace this node with two shifts followed by a MOVSS/MOVSD.<br>
EVT CastVT = MVT::v4i32;<br>
SDValue Splat1 =<br>
- DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), VT);<br>
+ DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);<br>
SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);<br>
SDValue Splat2 =<br>
- DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), VT);<br>
+ DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);<br>
SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);<br>
if (TargetOpcode == X86ISD::MOVSD)<br>
CastVT = MVT::v2i64;<br>
@@ -16664,16 +16691,16 @@ static SDValue LowerShift(SDValue Op, co<br>
assert(Subtarget->hasSSE2() && "Need SSE2 for pslli/pcmpeq.");<br>
<br>
// a = a << 5;<br>
- Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, VT));<br>
+ Op = DAG.getNode(ISD::SHL, dl, VT, Amt, DAG.getConstant(5, dl, VT));<br>
Op = DAG.getNode(ISD::BITCAST, dl, VT, Op);<br>
<br>
// Turn 'a' into a mask suitable for VSELECT<br>
- SDValue VSelM = DAG.getConstant(0x80, VT);<br>
+ SDValue VSelM = DAG.getConstant(0x80, dl, VT);<br>
SDValue OpVSel = DAG.getNode(ISD::AND, dl, VT, VSelM, Op);<br>
OpVSel = DAG.getNode(X86ISD::PCMPEQ, dl, VT, OpVSel, VSelM);<br>
<br>
- SDValue CM1 = DAG.getConstant(0x0f, VT);<br>
- SDValue CM2 = DAG.getConstant(0x3f, VT);<br>
+ SDValue CM1 = DAG.getConstant(0x0f, dl, VT);<br>
+ SDValue CM2 = DAG.getConstant(0x3f, dl, VT);<br>
<br>
// r = VSELECT(r, psllw(r & (char16)15, 4), a);<br>
SDValue M = DAG.getNode(ISD::AND, dl, VT, R, CM1);<br>
@@ -<a href="tel:16814" value="+4916814" target="_blank">16814</a>,7 +16841,7 @@ static SDValue LowerXALUO(SDValue Op, Se<br>
<br>
SDValue SetCC =<br>
DAG.getNode(X86ISD::SETCC, DL, MVT::i8,<br>
- DAG.getConstant(X86::COND_O, MVT::i32),<br>
+ DAG.getConstant(X86::COND_O, DL, MVT::i32),<br>
SDValue(Sum.getNode(), 2));<br>
<br>
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);<br>
@@ -<a href="tel:16827" value="+4916827" target="_blank">16827</a>,7 +16854,7 @@ static SDValue LowerXALUO(SDValue Op, Se<br>
<br>
SDValue SetCC =<br>
DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1),<br>
- DAG.getConstant(Cond, MVT::i32),<br>
+ DAG.getConstant(Cond, DL, MVT::i32),<br>
SDValue(Sum.getNode(), 1));<br>
<br>
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC);<br>
@@ -<a href="tel:16979" value="+4916979" target="_blank">16979</a>,13 +17006,13 @@ static SDValue LowerATOMIC_FENCE(SDValue<br>
return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));<br>
<br>
SDValue Chain = Op.getOperand(0);<br>
- SDValue Zero = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Zero = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Ops[] = {<br>
- DAG.getRegister(X86::ESP, MVT::i32), // Base<br>
- DAG.getTargetConstant(1, MVT::i8), // Scale<br>
- DAG.getRegister(0, MVT::i32), // Index<br>
- DAG.getTargetConstant(0, MVT::i32), // Disp<br>
- DAG.getRegister(0, MVT::i32), // Segment.<br>
+ DAG.getRegister(X86::ESP, MVT::i32), // Base<br>
+ DAG.getTargetConstant(1, dl, MVT::i8), // Scale<br>
+ DAG.getRegister(0, MVT::i32), // Index<br>
+ DAG.getTargetConstant(0, dl, MVT::i32), // Disp<br>
+ DAG.getRegister(0, MVT::i32), // Segment.<br>
Zero,<br>
Chain<br>
};<br>
@@ -17018,7 +17045,7 @@ static SDValue LowerCMP_SWAP(SDValue Op,<br>
SDValue Ops[] = { cpIn.getValue(0),<br>
Op.getOperand(1),<br>
Op.getOperand(3),<br>
- DAG.getTargetConstant(size, MVT::i8),<br>
+ DAG.getTargetConstant(size, DL, MVT::i8),<br>
cpIn.getValue(1) };<br>
SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);<br>
MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand();<br>
@@ -17030,7 +17057,8 @@ static SDValue LowerCMP_SWAP(SDValue Op,<br>
SDValue EFLAGS = DAG.getCopyFromReg(cpOut.getValue(1), DL, X86::EFLAGS,<br>
MVT::i32, cpOut.getValue(2));<br>
SDValue Success = DAG.getNode(X86ISD::SETCC, DL, Op->getValueType(1),<br>
- DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);<br>
+ DAG.getConstant(X86::COND_E, DL, MVT::i8),<br>
+ EFLAGS);<br>
<br>
DAG.ReplaceAllUsesOfValueWith(Op.getValue(0), cpOut);<br>
DAG.ReplaceAllUsesOfValueWith(Op.getValue(1), Success);<br>
@@ -17059,7 +17087,7 @@ static SDValue LowerBITCAST(SDValue Op,<br>
SmallVector<SDValue, 16> Elts;<br>
for (unsigned i = 0, e = NumElts; i != e; ++i)<br>
Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT, InVec,<br>
- DAG.getIntPtrConstant(i)));<br>
+ DAG.getIntPtrConstant(i, dl)));<br>
<br>
// Explicitly mark the extra elements as Undef.<br>
Elts.append(NumElts, DAG.getUNDEF(SVT));<br>
@@ -17068,7 +17096,7 @@ static SDValue LowerBITCAST(SDValue Op,<br>
SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, Elts);<br>
SDValue ToV2F64 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, BV);<br>
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, ToV2F64,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, dl));<br>
}<br>
<br>
assert(Subtarget->is64Bit() && !Subtarget->hasSSE2() &&<br>
@@ -17123,12 +17151,15 @@ static SDValue LowerCTPOP(SDValue Op, co<br>
bool NeedsBitcast = EltVT == MVT::i32;<br>
MVT BitcastVT = VT.is256BitVector() ? MVT::v4i64 : MVT::v2i64;<br>
<br>
- SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), EltVT);<br>
- SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), EltVT);<br>
- SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), EltVT);<br>
+ SDValue Cst55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), dl,<br>
+ EltVT);<br>
+ SDValue Cst33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), dl,<br>
+ EltVT);<br>
+ SDValue Cst0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), dl,<br>
+ EltVT);<br>
<br>
// v = v - ((v >> 1) & 0x55555555...)<br>
- SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, EltVT));<br>
+ SmallVector<SDValue, 8> Ones(NumElts, DAG.getConstant(1, dl, EltVT));<br>
SDValue OnesV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Ones);<br>
SDValue Srl = DAG.getNode(ISD::SRL, dl, VT, Op, OnesV);<br>
if (NeedsBitcast)<br>
@@ -17147,7 +17178,7 @@ static SDValue LowerCTPOP(SDValue Op, co<br>
// v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...)<br>
SmallVector<SDValue, 8> Mask33(NumElts, Cst33);<br>
SDValue M33 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Mask33);<br>
- SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, EltVT));<br>
+ SmallVector<SDValue, 8> Twos(NumElts, DAG.getConstant(2, dl, EltVT));<br>
SDValue TwosV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Twos);<br>
<br>
Srl = DAG.getNode(ISD::SRL, dl, VT, Sub, TwosV);<br>
@@ -17166,7 +17197,7 @@ static SDValue LowerCTPOP(SDValue Op, co<br>
SDValue Add = DAG.getNode(ISD::ADD, dl, VT, AndLHS, AndRHS);<br>
<br>
// v = (v + (v >> 4)) & 0x0F0F0F0F...<br>
- SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, EltVT));<br>
+ SmallVector<SDValue, 8> Fours(NumElts, DAG.getConstant(4, dl, EltVT));<br>
SDValue FoursV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Fours);<br>
Srl = DAG.getNode(ISD::SRL, dl, VT, Add, FoursV);<br>
Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);<br>
@@ -17199,7 +17230,7 @@ static SDValue LowerCTPOP(SDValue Op, co<br>
Add = And;<br>
SmallVector<SDValue, 8> Csts;<br>
for (unsigned i = 8; i <= Len/2; i *= 2) {<br>
- Csts.assign(NumElts, DAG.getConstant(i, EltVT));<br>
+ Csts.assign(NumElts, DAG.getConstant(i, dl, EltVT));<br>
SDValue CstsV = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Csts);<br>
Srl = DAG.getNode(ISD::SRL, dl, VT, Add, CstsV);<br>
Add = DAG.getNode(ISD::ADD, dl, VT, Add, Srl);<br>
@@ -17207,7 +17238,8 @@ static SDValue LowerCTPOP(SDValue Op, co<br>
}<br>
<br>
// The result is on the least significant 6-bits on i32 and 7-bits on i64.<br>
- SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), EltVT);<br>
+ SDValue Cst3F = DAG.getConstant(APInt(Len, Len == 32 ? 0x3F : 0x7F), dl,<br>
+ EltVT);<br>
SmallVector<SDValue, 8> Cst3FV(NumElts, Cst3F);<br>
SDValue M3F = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Cst3FV);<br>
if (NeedsBitcast) {<br>
@@ -17226,7 +17258,7 @@ static SDValue LowerLOAD_SUB(SDValue Op,<br>
SDLoc dl(Node);<br>
EVT T = Node->getValueType(0);<br>
SDValue negOp = DAG.getNode(ISD::SUB, dl, T,<br>
- DAG.getConstant(0, T), Node->getOperand(2));<br>
+ DAG.getConstant(0, dl, T), Node->getOperand(2));<br>
return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl,<br>
cast<AtomicSDNode>(Node)->getMemoryVT(),<br>
Node->getOperand(0),<br>
@@ -17332,9 +17364,9 @@ static SDValue LowerFSINCOS(SDValue Op,<br>
<br>
// Returned in bits 0:31 and 32:64 xmm0.<br>
SDValue SinVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,<br>
- CallResult.first, DAG.getIntPtrConstant(0));<br>
+ CallResult.first, DAG.getIntPtrConstant(0, dl));<br>
SDValue CosVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ArgVT,<br>
- CallResult.first, DAG.getIntPtrConstant(1));<br>
+ CallResult.first, DAG.getIntPtrConstant(1, dl));<br>
SDVTList Tys = DAG.getVTList(ArgVT, ArgVT);<br>
return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, SinVal, CosVal);<br>
}<br>
@@ -17501,7 +17533,7 @@ void X86TargetLowering::ReplaceNodeResul<br>
return;<br>
SDValue ZExtIn = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v2i64,<br>
N->getOperand(0));<br>
- SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL),<br>
+ SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), dl,<br>
MVT::f64);<br>
SDValue VBias = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2f64, Bias, Bias);<br>
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, ZExtIn,<br>
@@ -17544,9 +17576,9 @@ void X86TargetLowering::ReplaceNodeResul<br>
EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32;<br>
SDValue cpInL, cpInH;<br>
cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),<br>
- DAG.getConstant(0, HalfT));<br>
+ DAG.getConstant(0, dl, HalfT));<br>
cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2),<br>
- DAG.getConstant(1, HalfT));<br>
+ DAG.getConstant(1, dl, HalfT));<br>
cpInL = DAG.getCopyToReg(N->getOperand(0), dl,<br>
Regs64bit ? X86::RAX : X86::EAX,<br>
cpInL, SDValue());<br>
@@ -17555,9 +17587,9 @@ void X86TargetLowering::ReplaceNodeResul<br>
cpInH, cpInL.getValue(1));<br>
SDValue swapInL, swapInH;<br>
swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),<br>
- DAG.getConstant(0, HalfT));<br>
+ DAG.getConstant(0, dl, HalfT));<br>
swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3),<br>
- DAG.getConstant(1, HalfT));<br>
+ DAG.getConstant(1, dl, HalfT));<br>
swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl,<br>
Regs64bit ? X86::RBX : X86::EBX,<br>
swapInL, cpInH.getValue(1));<br>
@@ -17584,7 +17616,7 @@ void X86TargetLowering::ReplaceNodeResul<br>
MVT::i32, cpOutH.getValue(2));<br>
SDValue Success =<br>
DAG.getNode(X86ISD::SETCC, dl, MVT::i8,<br>
- DAG.getConstant(X86::COND_E, MVT::i8), EFLAGS);<br>
+ DAG.getConstant(X86::COND_E, dl, MVT::i8), EFLAGS);<br>
Success = DAG.getZExtOrTrunc(Success, dl, N->getValueType(1));<br>
<br>
Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF));<br>
@@ -17634,7 +17666,7 @@ void X86TargetLowering::ReplaceNodeResul<br>
SmallVector<SDValue, 8> Elts;<br>
for (unsigned i = 0, e = NumElts; i != e; ++i)<br>
Elts.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, SVT,<br>
- ToVecInt, DAG.getIntPtrConstant(i)));<br>
+ ToVecInt, DAG.getIntPtrConstant(i, dl)));<br>
<br>
Results.push_back(DAG.getNode(ISD::BUILD_VECTOR, dl, DstVT, Elts));<br>
}<br>
@@ -19845,7 +19877,7 @@ static bool combineX86ShuffleChain(SDVal<br>
int M = Mask[i / Ratio] != SM_SentinelZero<br>
? Ratio * Mask[i / Ratio] + i % Ratio<br>
: 255;<br>
- PSHUFBMask.push_back(DAG.getConstant(M, MVT::i8));<br>
+ PSHUFBMask.push_back(DAG.getConstant(M, DL, MVT::i8));<br>
}<br>
MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);<br>
Op = DAG.getNode(ISD::BITCAST, DL, ByteVT, Input);<br>
@@ -20151,7 +20183,7 @@ combineRedundantDWordShuffle(SDValue N,<br>
for (int &M : Mask)<br>
M = VMask[M];<br>
V = DAG.getNode(V.getOpcode(), DL, V.getValueType(), V.getOperand(0),<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
<br>
// Rebuild the chain around this new shuffle.<br>
while (!Chain.empty()) {<br>
@@ -20238,7 +20270,7 @@ static bool combineRedundantHalfShuffle(<br>
for (int &M : Mask)<br>
M = VMask[M];<br>
V = DAG.getNode(V.getOpcode(), DL, MVT::v8i16, V.getOperand(0),<br>
- getV4X86ShuffleImm8ForMask(Mask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(Mask, DL, DAG));<br>
<br>
// Check that the shuffles didn't cancel each other out. If not, we need to<br>
// combine to the new one.<br>
@@ -20297,7 +20329,7 @@ static SDValue PerformTargetShuffleCombi<br>
V = DAG.getNode(ISD::BITCAST, DL, DVT, V);<br>
DCI.AddToWorklist(V.getNode());<br>
V = DAG.getNode(X86ISD::PSHUFD, DL, DVT, V,<br>
- getV4X86ShuffleImm8ForMask(DMask, DAG));<br>
+ getV4X86ShuffleImm8ForMask(DMask, DL, DAG));<br>
DCI.AddToWorklist(V.getNode());<br>
return DAG.getNode(ISD::BITCAST, DL, VT, V);<br>
}<br>
@@ -20727,11 +20759,11 @@ static SDValue PerformEXTRACT_VECTOR_ELT<br>
SDValue Cst = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, InputVector);<br>
EVT VecIdxTy = DAG.getTargetLoweringInfo().getVectorIdxTy();<br>
SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,<br>
- DAG.getConstant(0, VecIdxTy));<br>
+ DAG.getConstant(0, dl, VecIdxTy));<br>
SDValue TopHalf = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, Cst,<br>
- DAG.getConstant(1, VecIdxTy));<br>
+ DAG.getConstant(1, dl, VecIdxTy));<br>
<br>
- SDValue ShAmt = DAG.getConstant(32,<br>
+ SDValue ShAmt = DAG.getConstant(32, dl,<br>
DAG.getTargetLoweringInfo().getShiftAmountTy(MVT::i64));<br>
Vals[0] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, BottomHalf);<br>
Vals[1] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32,<br>
@@ -20751,7 +20783,7 @@ static SDValue PerformEXTRACT_VECTOR_ELT<br>
// Replace each use (extract) with a load of the appropriate element.<br>
for (unsigned i = 0; i < 4; ++i) {<br>
uint64_t Offset = EltSize * i;<br>
- SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy());<br>
+ SDValue OffsetVal = DAG.getConstant(Offset, dl, TLI.getPointerTy());<br>
<br>
SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(),<br>
StackPtr, OffsetVal);<br>
@@ -21112,21 +21144,21 @@ static SDValue PerformSELECTCombine(SDNo<br>
TrueC->getAPIntValue().isPowerOf2()) {<br>
if (NeedsCondInvert) // Invert the condition if needed.<br>
Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,<br>
- DAG.getConstant(1, Cond.getValueType()));<br>
+ DAG.getConstant(1, DL, Cond.getValueType()));<br>
<br>
// Zero extend the condition if needed.<br>
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond);<br>
<br>
unsigned ShAmt = TrueC->getAPIntValue().logBase2();<br>
return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond,<br>
- DAG.getConstant(ShAmt, MVT::i8));<br>
+ DAG.getConstant(ShAmt, DL, MVT::i8));<br>
}<br>
<br>
// Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst.<br>
if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {<br>
if (NeedsCondInvert) // Invert the condition if needed.<br>
Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,<br>
- DAG.getConstant(1, Cond.getValueType()));<br>
+ DAG.getConstant(1, DL, Cond.getValueType()));<br>
<br>
// Zero extend the condition if needed.<br>
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,<br>
@@ -21161,7 +21193,7 @@ static SDValue PerformSELECTCombine(SDNo<br>
APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();<br>
if (NeedsCondInvert) // Invert the condition if needed.<br>
Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,<br>
- DAG.getConstant(1, Cond.getValueType()));<br>
+ DAG.getConstant(1, DL, Cond.getValueType()));<br>
<br>
// Zero extend the condition if needed.<br>
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),<br>
@@ -21169,7 +21201,8 @@ static SDValue PerformSELECTCombine(SDNo<br>
// Scale the condition by the difference.<br>
if (Diff != 1)<br>
Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,<br>
- DAG.getConstant(Diff, Cond.getValueType()));<br>
+ DAG.getConstant(Diff, DL,<br>
+ Cond.getValueType()));<br>
<br>
// Add the base if non-zero.<br>
if (FalseC->getAPIntValue() != 0)<br>
@@ -21257,7 +21290,7 @@ static SDValue PerformSELECTCombine(SDNo<br>
(-OpRHSConst->getAPIntValue() - 1))<br>
return DAG.getNode(<br>
X86ISD::SUBUS, DL, VT, OpLHS,<br>
- DAG.getConstant(-OpRHSConst->getAPIntValue(), VT));<br>
+ DAG.getConstant(-OpRHSConst->getAPIntValue(), DL, VT));<br>
<br>
// Another special case: If C was a sign bit, the sub has been<br>
// canonicalized into a xor.<br>
@@ -21271,7 +21304,7 @@ static SDValue PerformSELECTCombine(SDNo<br>
// don't rely on particular values of undef lanes.<br>
return DAG.getNode(<br>
X86ISD::SUBUS, DL, VT, OpLHS,<br>
- DAG.getConstant(OpRHSConst->getAPIntValue(), VT));<br>
+ DAG.getConstant(OpRHSConst->getAPIntValue(), DL, VT));<br>
}<br>
}<br>
}<br>
@@ -21665,7 +21698,7 @@ static SDValue PerformCMOVCombine(SDNode<br>
// Extra check as FCMOV only supports a subset of X86 cond.<br>
(FalseOp.getValueType() != MVT::f80 || hasFPCMov(CC))) {<br>
SDValue Ops[] = { FalseOp, TrueOp,<br>
- DAG.getConstant(CC, MVT::i8), Flags };<br>
+ DAG.getConstant(CC, DL, MVT::i8), Flags };<br>
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);<br>
}<br>
<br>
@@ -21687,14 +21720,14 @@ static SDValue PerformCMOVCombine(SDNode<br>
// shift amount.<br>
if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) {<br>
Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,<br>
- DAG.getConstant(CC, MVT::i8), Cond);<br>
+ DAG.getConstant(CC, DL, MVT::i8), Cond);<br>
<br>
// Zero extend the condition if needed.<br>
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond);<br>
<br>
unsigned ShAmt = TrueC->getAPIntValue().logBase2();<br>
Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond,<br>
- DAG.getConstant(ShAmt, MVT::i8));<br>
+ DAG.getConstant(ShAmt, DL, MVT::i8));<br>
if (N->getNumValues() == 2) // Dead flag value?<br>
return DCI.CombineTo(N, Cond, SDValue());<br>
return Cond;<br>
@@ -21704,7 +21737,7 @@ static SDValue PerformCMOVCombine(SDNode<br>
// for any integer data type, including i8/i16.<br>
if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) {<br>
Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,<br>
- DAG.getConstant(CC, MVT::i8), Cond);<br>
+ DAG.getConstant(CC, DL, MVT::i8), Cond);<br>
<br>
// Zero extend the condition if needed.<br>
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL,<br>
@@ -21742,14 +21775,14 @@ static SDValue PerformCMOVCombine(SDNode<br>
if (isFastMultiplier) {<br>
APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue();<br>
Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8,<br>
- DAG.getConstant(CC, MVT::i8), Cond);<br>
+ DAG.getConstant(CC, DL, MVT::i8), Cond);<br>
// Zero extend the condition if needed.<br>
Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0),<br>
Cond);<br>
// Scale the condition by the difference.<br>
if (Diff != 1)<br>
Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond,<br>
- DAG.getConstant(Diff, Cond.getValueType()));<br>
+ DAG.getConstant(Diff, DL, Cond.getValueType()));<br>
<br>
// Add the base if non-zero.<br>
if (FalseC->getAPIntValue() != 0)<br>
@@ -21795,7 +21828,7 @@ static SDValue PerformCMOVCombine(SDNode<br>
if (CC == X86::COND_E &&<br>
CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {<br>
SDValue Ops[] = { FalseOp, Cond.getOperand(0),<br>
- DAG.getConstant(CC, MVT::i8), Cond };<br>
+ DAG.getConstant(CC, DL, MVT::i8), Cond };<br>
return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);<br>
}<br>
}<br>
@@ -21829,10 +21862,10 @@ static SDValue PerformCMOVCombine(SDNode<br>
CC1 = X86::GetOppositeBranchCondition(CC1);<br>
}<br>
<br>
- SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, MVT::i8),<br>
+ SDValue LOps[] = {FalseOp, TrueOp, DAG.getConstant(CC0, DL, MVT::i8),<br>
Flags};<br>
SDValue LCMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), LOps);<br>
- SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, MVT::i8), Flags};<br>
+ SDValue Ops[] = {LCMOV, TrueOp, DAG.getConstant(CC1, DL, MVT::i8), Flags};<br>
SDValue CMOV = DAG.getNode(X86ISD::CMOV, DL, N->getVTList(), Ops);<br>
DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SDValue(CMOV.getNode(), 1));<br>
return CMOV;<br>
@@ -21930,8 +21963,9 @@ static SDValue PerformINTRINSIC_WO_CHAIN<br>
<br>
// Replace this packed shift intrinsic with a target independent<br>
// shift dag node.<br>
- SDValue Splat = DAG.getConstant(C, VT);<br>
- return DAG.getNode(ISD::SRA, SDLoc(N), VT, Op0, Splat);<br>
+ SDLoc DL(N);<br>
+ SDValue Splat = DAG.getConstant(C, DL, VT);<br>
+ return DAG.getNode(ISD::SRA, DL, VT, Op0, Splat);<br>
}<br>
}<br>
}<br>
@@ -21981,17 +22015,17 @@ static SDValue PerformMulCombine(SDNode<br>
SDValue NewMul;<br>
if (isPowerOf2_64(MulAmt1))<br>
NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),<br>
- DAG.getConstant(Log2_64(MulAmt1), MVT::i8));<br>
+ DAG.getConstant(Log2_64(MulAmt1), DL, MVT::i8));<br>
else<br>
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0),<br>
- DAG.getConstant(MulAmt1, VT));<br>
+ DAG.getConstant(MulAmt1, DL, VT));<br>
<br>
if (isPowerOf2_64(MulAmt2))<br>
NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul,<br>
- DAG.getConstant(Log2_64(MulAmt2), MVT::i8));<br>
+ DAG.getConstant(Log2_64(MulAmt2), DL, MVT::i8));<br>
else<br>
NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul,<br>
- DAG.getConstant(MulAmt2, VT));<br>
+ DAG.getConstant(MulAmt2, DL, VT));<br>
<br>
// Do not add new nodes to DAG combiner worklist.<br>
DCI.CombineTo(N, NewMul, false);<br>
@@ -22018,9 +22052,11 @@ static SDValue PerformSHLCombine(SDNode<br>
APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();<br>
APInt ShAmt = N1C->getAPIntValue();<br>
Mask = Mask.shl(ShAmt);<br>
- if (Mask != 0)<br>
- return DAG.getNode(ISD::AND, SDLoc(N), VT,<br>
- N00, DAG.getConstant(Mask, VT));<br>
+ if (Mask != 0) {<br>
+ SDLoc DL(N);<br>
+ return DAG.getNode(ISD::AND, DL, VT,<br>
+ N00, DAG.getConstant(Mask, DL, VT));<br>
+ }<br>
}<br>
}<br>
<br>
@@ -22150,7 +22186,8 @@ static SDValue CMPEQCombine(SDNode *N, S<br>
unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4;<br>
if (Subtarget->hasAVX512()) {<br>
SDValue FSetCC = DAG.getNode(X86ISD::FSETCC, DL, MVT::i1, CMP00,<br>
- CMP01, DAG.getConstant(x86cc, MVT::i8));<br>
+ CMP01,<br>
+ DAG.getConstant(x86cc, DL, MVT::i8));<br>
if (N->getValueType(0) != MVT::i1)<br>
return DAG.getNode(ISD::ZERO_EXTEND, DL, N->getValueType(0),<br>
FSetCC);<br>
@@ -22158,7 +22195,8 @@ static SDValue CMPEQCombine(SDNode *N, S<br>
}<br>
SDValue OnesOrZeroesF = DAG.getNode(X86ISD::FSETCC, DL,<br>
CMP00.getValueType(), CMP00, CMP01,<br>
- DAG.getConstant(x86cc, MVT::i8));<br>
+ DAG.getConstant(x86cc, DL,<br>
+ MVT::i8));<br>
<br>
bool is64BitFP = (CMP00.getValueType() == MVT::f64);<br>
MVT IntVT = is64BitFP ? MVT::i64 : MVT::i32;<br>
@@ -22174,14 +22212,16 @@ static SDValue CMPEQCombine(SDNode *N, S<br>
SDValue Vector32 = DAG.getNode(ISD::BITCAST, DL, MVT::v4f32,<br>
Vector64);<br>
OnesOrZeroesF = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::f32,<br>
- Vector32, DAG.getIntPtrConstant(0));<br>
+ Vector32, DAG.getIntPtrConstant(0, DL));<br>
IntVT = MVT::i32;<br>
}<br>
<br>
- SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT, OnesOrZeroesF);<br>
+ SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, IntVT,<br>
+ OnesOrZeroesF);<br>
SDValue ANDed = DAG.getNode(ISD::AND, DL, IntVT, OnesOrZeroesI,<br>
- DAG.getConstant(1, IntVT));<br>
- SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed);<br>
+ DAG.getConstant(1, DL, IntVT));<br>
+ SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,<br>
+ ANDed);<br>
return OneBitOfTruth;<br>
}<br>
}<br>
@@ -22293,7 +22333,7 @@ static SDValue WidenMaskArithmetic(SDNod<br>
APInt Mask = APInt::getAllOnesValue(InBits);<br>
Mask = Mask.zext(VT.getScalarType().getSizeInBits());<br>
return DAG.getNode(ISD::AND, DL, VT,<br>
- Op, DAG.getConstant(Mask, VT));<br>
+ Op, DAG.getConstant(Mask, DL, VT));<br>
}<br>
case ISD::SIGN_EXTEND:<br>
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, VT,<br>
@@ -22389,8 +22429,8 @@ static SDValue VectorZextCombine(SDNode<br>
Mask.push_back(i / ZextRatio);<br>
<br>
SDValue NewShuffle = DAG.getVectorShuffle(Shuffle->getValueType(0), DL,<br>
- Shuffle->getOperand(0), DAG.getConstant(0, SrcType), Mask);<br>
- return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);<br>
+ Shuffle->getOperand(0), DAG.getConstant(0, DL, SrcType), Mask);<br>
+ return DAG.getNode(ISD::BITCAST, DL, N0.getValueType(), NewShuffle);<br>
}<br>
<br>
static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG,<br>
@@ -22425,7 +22465,8 @@ static SDValue PerformAndCombine(SDNode<br>
uint64_t MaskSize = countPopulation(Mask);<br>
if (Shift + MaskSize <= VT.getSizeInBits())<br>
return DAG.getNode(X86ISD::BEXTR, DL, VT, N0.getOperand(0),<br>
- DAG.getConstant(Shift | (MaskSize << 8), VT));<br>
+ DAG.getConstant(Shift | (MaskSize << 8), DL,<br>
+ VT));<br>
}<br>
}<br>
} // BEXTR<br>
@@ -22640,10 +22681,10 @@ static SDValue performIntegerAbsCombine(<br>
if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {<br>
// Generate SUB & CMOV.<br>
SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),<br>
- DAG.getConstant(0, VT), N0.getOperand(0));<br>
+ DAG.getConstant(0, DL, VT), N0.getOperand(0));<br>
<br>
SDValue Ops[] = { N0.getOperand(0), Neg,<br>
- DAG.getConstant(X86::COND_GE, MVT::i8),<br>
+ DAG.getConstant(X86::COND_GE, DL, MVT::i8),<br>
SDValue(Neg.getNode(), 1) };<br>
return DAG.getNode(X86ISD::CMOV, DL, DAG.getVTList(VT, MVT::Glue), Ops);<br>
}<br>
@@ -22688,7 +22729,7 @@ static SDValue PerformLOADCombine(SDNode<br>
return SDValue();<br>
<br>
SDValue Ptr = Ld->getBasePtr();<br>
- SDValue Increment = DAG.getConstant(16, TLI.getPointerTy());<br>
+ SDValue Increment = DAG.getConstant(16, dl, TLI.getPointerTy());<br>
<br>
EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(),<br>
NumElems/2);<br>
@@ -22767,7 +22808,7 @@ static SDValue PerformMLOADCombine(SDNod<br>
for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)<br>
ShuffleVec[i] = NumElems*SizeRatio;<br>
NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,<br>
- DAG.getConstant(0, WideVecVT),<br>
+ DAG.getConstant(0, dl, WideVecVT),<br>
&ShuffleVec[0]);<br>
}<br>
else {<br>
@@ -22779,7 +22820,7 @@ static SDValue PerformMLOADCombine(SDNod<br>
<br>
unsigned NumConcat = WidenNumElts / MaskNumElts;<br>
SmallVector<SDValue, 16> Ops(NumConcat);<br>
- SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());<br>
+ SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());<br>
Ops[0] = Mask;<br>
for (unsigned i = 1; i != NumConcat; ++i)<br>
Ops[i] = ZeroVal;<br>
@@ -22851,7 +22892,7 @@ static SDValue PerformMSTORECombine(SDNo<br>
for (unsigned i = NumElems; i != NumElems*SizeRatio; ++i)<br>
ShuffleVec[i] = NumElems*SizeRatio;<br>
NewMask = DAG.getVectorShuffle(WideVecVT, dl, NewMask,<br>
- DAG.getConstant(0, WideVecVT),<br>
+ DAG.getConstant(0, dl, WideVecVT),<br>
&ShuffleVec[0]);<br>
}<br>
else {<br>
@@ -22863,7 +22904,7 @@ static SDValue PerformMSTORECombine(SDNo<br>
<br>
unsigned NumConcat = WidenNumElts / MaskNumElts;<br>
SmallVector<SDValue, 16> Ops(NumConcat);<br>
- SDValue ZeroVal = DAG.getConstant(0, Mask.getValueType());<br>
+ SDValue ZeroVal = DAG.getConstant(0, dl, Mask.getValueType());<br>
Ops[0] = Mask;<br>
for (unsigned i = 1; i != NumConcat; ++i)<br>
Ops[i] = ZeroVal;<br>
@@ -22897,7 +22938,7 @@ static SDValue PerformSTORECombine(SDNod<br>
SDValue Value0 = Extract128BitVector(StoredVal, 0, DAG, dl);<br>
SDValue Value1 = Extract128BitVector(StoredVal, NumElems/2, DAG, dl);<br>
<br>
- SDValue Stride = DAG.getConstant(16, TLI.getPointerTy());<br>
+ SDValue Stride = DAG.getConstant(16, dl, TLI.getPointerTy());<br>
SDValue Ptr0 = St->getBasePtr();<br>
SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride);<br>
<br>
@@ -22970,7 +23011,7 @@ static SDValue PerformSTORECombine(SDNod<br>
assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits());<br>
SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff);<br>
SmallVector<SDValue, 8> Chains;<br>
- SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8,<br>
+ SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, dl,<br>
TLI.getPointerTy());<br>
SDValue Ptr = St->getBasePtr();<br>
<br>
@@ -22978,7 +23019,7 @@ static SDValue PerformSTORECombine(SDNod<br>
for (unsigned i=0, e=(ToSz*NumElems)/StoreType.getSizeInBits(); i!=e; ++i) {<br>
SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,<br>
StoreType, ShuffWide,<br>
- DAG.getIntPtrConstant(i));<br>
+ DAG.getIntPtrConstant(i, dl));<br>
SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr,<br>
St->getPointerInfo(), St->isVolatile(),<br>
St->isNonTemporal(), St->getAlignment());<br>
@@ -23062,7 +23103,7 @@ static SDValue PerformSTORECombine(SDNod<br>
// Otherwise, lower to two pairs of 32-bit loads / stores.<br>
SDValue LoAddr = Ld->getBasePtr();<br>
SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr,<br>
- DAG.getConstant(4, MVT::i32));<br>
+ DAG.getConstant(4, LdDL, MVT::i32));<br>
<br>
SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr,<br>
Ld->getPointerInfo(),<br>
@@ -23083,7 +23124,7 @@ static SDValue PerformSTORECombine(SDNod<br>
<br>
LoAddr = St->getBasePtr();<br>
HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr,<br>
- DAG.getConstant(4, MVT::i32));<br>
+ DAG.getConstant(4, StDL, MVT::i32));<br>
<br>
SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr,<br>
St->getPointerInfo(),<br>
@@ -23507,7 +23548,7 @@ static SDValue PerformZExtCombine(SDNode<br>
return DAG.getNode(ISD::AND, dl, VT,<br>
DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,<br>
N00.getOperand(0), N00.getOperand(1)),<br>
- DAG.getConstant(1, VT));<br>
+ DAG.getConstant(1, dl, VT));<br>
}<br>
}<br>
<br>
@@ -23519,7 +23560,7 @@ static SDValue PerformZExtCombine(SDNode<br>
return DAG.getNode(ISD::AND, dl, VT,<br>
DAG.getNode(X86ISD::SETCC_CARRY, dl, VT,<br>
N00.getOperand(0), N00.getOperand(1)),<br>
- DAG.getConstant(1, VT));<br>
+ DAG.getConstant(1, dl, VT));<br>
}<br>
}<br>
if (VT.is256BitVector()) {<br>
@@ -23558,18 +23599,18 @@ static SDValue PerformISDSETCCCombine(SD<br>
if ((CC == ISD::SETNE || CC == ISD::SETEQ) && LHS.getOpcode() == ISD::SUB)<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(LHS.getOperand(0)))<br>
if (C->getAPIntValue() == 0 && LHS.hasOneUse()) {<br>
- SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), LHS.getValueType(), RHS,<br>
+ SDValue addV = DAG.getNode(ISD::ADD, DL, LHS.getValueType(), RHS,<br>
LHS.getOperand(1));<br>
- return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,<br>
- DAG.getConstant(0, addV.getValueType()), CC);<br>
+ return DAG.getSetCC(DL, N->getValueType(0), addV,<br>
+ DAG.getConstant(0, DL, addV.getValueType()), CC);<br>
}<br>
if ((CC == ISD::SETNE || CC == ISD::SETEQ) && RHS.getOpcode() == ISD::SUB)<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS.getOperand(0)))<br>
if (C->getAPIntValue() == 0 && RHS.hasOneUse()) {<br>
- SDValue addV = DAG.getNode(ISD::ADD, SDLoc(N), RHS.getValueType(), LHS,<br>
+ SDValue addV = DAG.getNode(ISD::ADD, DL, RHS.getValueType(), LHS,<br>
RHS.getOperand(1));<br>
- return DAG.getSetCC(SDLoc(N), N->getValueType(0), addV,<br>
- DAG.getConstant(0, addV.getValueType()), CC);<br>
+ return DAG.getSetCC(DL, N->getValueType(0), addV,<br>
+ DAG.getConstant(0, DL, addV.getValueType()), CC);<br>
}<br>
<br>
if (VT.getScalarType() == MVT::i1 &&<br>
@@ -23593,9 +23634,9 @@ static SDValue PerformISDSETCCCombine(SD<br>
assert(VT == LHS.getOperand(0).getValueType() &&<br>
"Uexpected operand type");<br>
if (CC == ISD::SETGT)<br>
- return DAG.getConstant(0, VT);<br>
+ return DAG.getConstant(0, DL, VT);<br>
if (CC == ISD::SETLE)<br>
- return DAG.getConstant(1, VT);<br>
+ return DAG.getConstant(1, DL, VT);<br>
if (CC == ISD::SETEQ || CC == ISD::SETGE)<br>
return DAG.getNOT(DL, LHS.getOperand(0), VT);<br>
<br>
@@ -23616,7 +23657,8 @@ static SDValue NarrowVectorLoadToElement<br>
SDValue Addr = Load->getOperand(1);<br>
SDValue NewAddr = DAG.getNode(<br>
ISD::ADD, dl, Addr.getSimpleValueType(), Addr,<br>
- DAG.getConstant(Index * EVT.getStoreSize(), Addr.getSimpleValueType()));<br>
+ DAG.getConstant(Index * EVT.getStoreSize(), dl,<br>
+ Addr.getSimpleValueType()));<br>
<br>
SDValue NewLoad =<br>
DAG.getLoad(EVT, dl, Load->getChain(), NewAddr,<br>
@@ -23672,7 +23714,7 @@ static SDValue PerformBLENDICombine(SDNo<br>
if (VT == MVT::v2f64)<br>
if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))<br>
if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {<br>
- SDValue NewMask = DAG.getConstant(1, MVT::i8);<br>
+ SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);<br>
return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);<br>
}<br>
<br>
@@ -23687,12 +23729,14 @@ static SDValue MaterializeSETB(SDLoc DL,<br>
if (VT == MVT::i8)<br>
return DAG.getNode(ISD::AND, DL, VT,<br>
DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,<br>
- DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS),<br>
- DAG.getConstant(1, VT));<br>
+ DAG.getConstant(X86::COND_B, DL, MVT::i8),<br>
+ EFLAGS),<br>
+ DAG.getConstant(1, DL, VT));<br>
assert (VT == MVT::i1 && "Unexpected type for SECCC node");<br>
return DAG.getNode(ISD::TRUNCATE, DL, MVT::i1,<br>
DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8,<br>
- DAG.getConstant(X86::COND_B, MVT::i8), EFLAGS));<br>
+ DAG.getConstant(X86::COND_B, DL, MVT::i8),<br>
+ EFLAGS));<br>
}<br>
<br>
// Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT<br>
@@ -23731,7 +23775,7 @@ static SDValue PerformSETCCCombine(SDNod<br>
<br>
Flags = checkBoolTestSetCCCombine(EFLAGS, CC);<br>
if (Flags.getNode()) {<br>
- SDValue Cond = DAG.getConstant(CC, MVT::i8);<br>
+ SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);<br>
return DAG.getNode(X86ISD::SETCC, DL, N->getVTList(), Cond, Flags);<br>
}<br>
<br>
@@ -23753,7 +23797,7 @@ static SDValue PerformBrCondCombine(SDNo<br>
<br>
Flags = checkBoolTestSetCCCombine(EFLAGS, CC);<br>
if (Flags.getNode()) {<br>
- SDValue Cond = DAG.getConstant(CC, MVT::i8);<br>
+ SDValue Cond = DAG.getConstant(CC, DL, MVT::i8);<br>
return DAG.getNode(X86ISD::BRCOND, DL, N->getVTList(), Chain, Dest, Cond,<br>
Flags);<br>
}<br>
@@ -23857,12 +23901,13 @@ static SDValue PerformADCCombine(SDNode<br>
SDValue(N, 1).use_empty()) {<br>
SDLoc DL(N);<br>
EVT VT = N->getValueType(0);<br>
- SDValue CarryOut = DAG.getConstant(0, N->getValueType(1));<br>
+ SDValue CarryOut = DAG.getConstant(0, DL, N->getValueType(1));<br>
SDValue Res1 = DAG.getNode(ISD::AND, DL, VT,<br>
DAG.getNode(X86ISD::SETCC_CARRY, DL, VT,<br>
- DAG.getConstant(X86::COND_B,MVT::i8),<br>
+ DAG.getConstant(X86::COND_B, DL,<br>
+ MVT::i8),<br>
N->getOperand(2)),<br>
- DAG.getConstant(1, VT));<br>
+ DAG.getConstant(1, DL, VT));<br>
return DCI.CombineTo(N, Res1, CarryOut);<br>
}<br>
<br>
@@ -23897,16 +23942,17 @@ static SDValue OptimizeConditionalInDecr<br>
<br>
SDValue CmpOp0 = Cmp.getOperand(0);<br>
SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0,<br>
- DAG.getConstant(1, CmpOp0.getValueType()));<br>
+ DAG.getConstant(1, DL, CmpOp0.getValueType()));<br>
<br>
SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1);<br>
if (CC == X86::COND_NE)<br>
return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB,<br>
DL, OtherVal.getValueType(), OtherVal,<br>
- DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp);<br>
+ DAG.getConstant(-1ULL, DL, OtherVal.getValueType()),<br>
+ NewCmp);<br>
return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC,<br>
DL, OtherVal.getValueType(), OtherVal,<br>
- DAG.getConstant(0, OtherVal.getValueType()), NewCmp);<br>
+ DAG.getConstant(0, DL, OtherVal.getValueType()), NewCmp);<br>
}<br>
<br>
/// PerformADDCombine - Do target-specific dag combines on integer adds.<br>
@@ -23942,9 +23988,9 @@ static SDValue PerformSubCombine(SDNode<br>
EVT VT = Op0.getValueType();<br>
SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,<br>
Op1.getOperand(0),<br>
- DAG.getConstant(~XorC, VT));<br>
+ DAG.getConstant(~XorC, SDLoc(Op1), VT));<br>
return DAG.getNode(ISD::ADD, SDLoc(N), VT, NewXor,<br>
- DAG.getConstant(C->getAPIntValue()+1, VT));<br>
+ DAG.getConstant(C->getAPIntValue() + 1, SDLoc(N), VT));<br>
}<br>
}<br>
<br>
@@ -24014,7 +24060,7 @@ static SDValue performVZEXTCombine(SDNod<br>
OrigVT = MVT::getVectorVT(OrigVT.getVectorElementType(),<br>
OrigVT.getVectorNumElements() / Ratio);<br>
OrigV = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, OrigVT, OrigV,<br>
- DAG.getIntPtrConstant(0));<br>
+ DAG.getIntPtrConstant(0, DL));<br>
}<br>
Op = DAG.getNode(ISD::BITCAST, DL, OpVT, OrigV);<br>
return DAG.getNode(X86ISD::VZEXT, DL, VT, Op);<br>
@@ -24495,7 +24541,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
case 'I':<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (C->getZExtValue() <= 31) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24503,7 +24550,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
case 'J':<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (C->getZExtValue() <= 63) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24511,7 +24559,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
case 'K':<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (isInt<8>(C->getSExtValue())) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24520,7 +24569,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||<br>
(Subtarget->is64Bit() && C->getZExtValue() == 0xffffffff)) {<br>
- Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24528,7 +24578,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
case 'M':<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (C->getZExtValue() <= 3) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24536,7 +24587,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
case 'N':<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (C->getZExtValue() <= 255) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24544,7 +24596,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
case 'O':<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (C->getZExtValue() <= 127) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24555,7 +24608,7 @@ void X86TargetLowering::LowerAsmOperandF<br>
if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),<br>
C->getSExtValue())) {<br>
// Widen to 64 bits here to get it sign extended.<br>
- Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64);<br>
+ Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), MVT::i64);<br>
break;<br>
}<br>
// FIXME gcc accepts some relocatable values here too, but only in certain<br>
@@ -24568,7 +24621,8 @@ void X86TargetLowering::LowerAsmOperandF<br>
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {<br>
if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),<br>
C->getZExtValue())) {<br>
- Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType());<br>
+ Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),<br>
+ Op.getValueType());<br>
break;<br>
}<br>
}<br>
@@ -24580,7 +24634,7 @@ void X86TargetLowering::LowerAsmOperandF<br>
// Literal immediates are always ok.<br>
if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {<br>
// Widen to 64 bits here to get it sign extended.<br>
- Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64);<br>
+ Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);<br>
break;<br>
}<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue Apr 28 06:56:37 2015<br>
@@ -17,12 +17,12 @@<br>
<br>
def GetLo32XForm : SDNodeXForm<imm, [{<br>
// Transformation function: get the low 32 bits.<br>
- return getI32Imm((unsigned)N->getZExtValue());<br>
+ return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));<br>
}]>;<br>
<br>
def GetLo8XForm : SDNodeXForm<imm, [{<br>
// Transformation function: get the low 8 bits.<br>
- return getI8Imm((uint8_t)N->getZExtValue());<br>
+ return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));<br>
}]>;<br>
<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue Apr 28 06:56:37 2015<br>
@@ -566,7 +566,7 @@ def fp32imm0 : PatLeaf<(f32 fpimm), [{<br>
<br>
def I8Imm : SDNodeXForm<imm, [{<br>
// Transformation function: get the low 8 bits.<br>
- return getI8Imm((uint8_t)N->getZExtValue());<br>
+ return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));<br>
}]>;<br>
<br>
def FROUND_NO_EXC : ImmLeaf<i32, [{ return Imm == 8; }]>;<br>
@@ -577,31 +577,31 @@ def FROUND_CURRENT : ImmLeaf<i32, [{<br>
// BYTE_imm - Transform bit immediates into byte immediates.<br>
def BYTE_imm : SDNodeXForm<imm, [{<br>
// Transformation function: imm >> 3<br>
- return getI32Imm(N->getZExtValue() >> 3);<br>
+ return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));<br>
}]>;<br>
<br>
// EXTRACT_get_vextract128_imm xform function: convert extract_subvector index<br>
// to VEXTRACTF128/VEXTRACTI128 imm.<br>
def EXTRACT_get_vextract128_imm : SDNodeXForm<extract_subvector, [{<br>
- return getI8Imm(X86::getExtractVEXTRACT128Immediate(N));<br>
+ return getI8Imm(X86::getExtractVEXTRACT128Immediate(N), SDLoc(N));<br>
}]>;<br>
<br>
// INSERT_get_vinsert128_imm xform function: convert insert_subvector index to<br>
// VINSERTF128/VINSERTI128 imm.<br>
def INSERT_get_vinsert128_imm : SDNodeXForm<insert_subvector, [{<br>
- return getI8Imm(X86::getInsertVINSERT128Immediate(N));<br>
+ return getI8Imm(X86::getInsertVINSERT128Immediate(N), SDLoc(N));<br>
}]>;<br>
<br>
// EXTRACT_get_vextract256_imm xform function: convert extract_subvector index<br>
// to VEXTRACTF64x4 imm.<br>
def EXTRACT_get_vextract256_imm : SDNodeXForm<extract_subvector, [{<br>
- return getI8Imm(X86::getExtractVEXTRACT256Immediate(N));<br>
+ return getI8Imm(X86::getExtractVEXTRACT256Immediate(N), SDLoc(N));<br>
}]>;<br>
<br>
// INSERT_get_vinsert256_imm xform function: convert insert_subvector index to<br>
// VINSERTF64x4 imm.<br>
def INSERT_get_vinsert256_imm : SDNodeXForm<insert_subvector, [{<br>
- return getI8Imm(X86::getInsertVINSERT256Immediate(N));<br>
+ return getI8Imm(X86::getInsertVINSERT256Immediate(N), SDLoc(N));<br>
}]>;<br>
<br>
def vextract128_extract : PatFrag<(ops node:$bigvec, node:$index),<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Tue Apr 28 06:56:37 2015<br>
@@ -2223,7 +2223,7 @@ let Predicates = [HasBMI2], Defs = [EFLA<br>
<br>
def CountTrailingOnes : SDNodeXForm<imm, [{<br>
// Count the trailing ones in the immediate.<br>
- return getI8Imm(countTrailingOnes(N->getZExtValue()));<br>
+ return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));<br>
}]>;<br>
<br>
def BZHIMask : ImmLeaf<i64, [{<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrShiftRotate.td Tue Apr 28 06:56:37 2015<br>
@@ -850,12 +850,12 @@ def SHRD64mri8 : RIi8<0xAC, MRMDestMem,<br>
<br>
def ROT32L2R_imm8 : SDNodeXForm<imm, [{<br>
// Convert a ROTL shamt to a ROTR shamt on 32-bit integer.<br>
- return getI8Imm(32 - N->getZExtValue());<br>
+ return getI8Imm(32 - N->getZExtValue(), SDLoc(N));<br>
}]>;<br>
<br>
def ROT64L2R_imm8 : SDNodeXForm<imm, [{<br>
// Convert a ROTL shamt to a ROTR shamt on 64-bit integer.<br>
- return getI8Imm(64 - N->getZExtValue());<br>
+ return getI8Imm(64 - N->getZExtValue(), SDLoc(N));<br>
}]>;<br>
<br>
multiclass bmi_rotate<string asm, RegisterClass RC, X86MemOperand x86memop> {<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86SelectionDAGInfo.cpp Tue Apr 28 06:56:37 2015<br>
@@ -138,22 +138,22 @@ X86SelectionDAGInfo::EmitTargetCodeForMe<br>
default: // Byte aligned<br>
AVT = MVT::i8;<br>
ValReg = X86::AL;<br>
- Count = DAG.getIntPtrConstant(SizeVal);<br>
+ Count = DAG.getIntPtrConstant(SizeVal, dl);<br>
break;<br>
}<br>
<br>
if (AVT.bitsGT(MVT::i8)) {<br>
unsigned UBytes = AVT.getSizeInBits() / 8;<br>
- Count = DAG.getIntPtrConstant(SizeVal / UBytes);<br>
+ Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);<br>
BytesLeft = SizeVal % UBytes;<br>
}<br>
<br>
- Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, AVT),<br>
+ Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),<br>
InFlag);<br>
InFlag = Chain.getValue(1);<br>
} else {<br>
AVT = MVT::i8;<br>
- Count = DAG.getIntPtrConstant(SizeVal);<br>
+ Count = DAG.getIntPtrConstant(SizeVal, dl);<br>
Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);<br>
InFlag = Chain.getValue(1);<br>
}<br>
@@ -174,7 +174,8 @@ X86SelectionDAGInfo::EmitTargetCodeForMe<br>
Count = Size;<br>
EVT CVT = Count.getValueType();<br>
SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,<br>
- DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT));<br>
+ DAG.getConstant((AVT == MVT::i64) ? 7 : 3, dl,<br>
+ CVT));<br>
Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX :<br>
X86::ECX,<br>
Left, InFlag);<br>
@@ -190,9 +191,9 @@ X86SelectionDAGInfo::EmitTargetCodeForMe<br>
<br>
Chain = DAG.getMemset(Chain, dl,<br>
DAG.getNode(ISD::ADD, dl, AddrVT, Dst,<br>
- DAG.getConstant(Offset, AddrVT)),<br>
+ DAG.getConstant(Offset, dl, AddrVT)),<br>
Src,<br>
- DAG.getConstant(BytesLeft, SizeVT),<br>
+ DAG.getConstant(BytesLeft, dl, SizeVT),<br>
Align, isVolatile, false,<br>
DstPtrInfo.getWithOffset(Offset));<br>
}<br>
@@ -248,7 +249,7 @@ SDValue X86SelectionDAGInfo::EmitTargetC<br>
<br>
unsigned UBytes = AVT.getSizeInBits() / 8;<br>
unsigned CountVal = SizeVal / UBytes;<br>
- SDValue Count = DAG.getIntPtrConstant(CountVal);<br>
+ SDValue Count = DAG.getIntPtrConstant(CountVal, dl);<br>
unsigned BytesLeft = SizeVal % UBytes;<br>
<br>
SDValue InFlag;<br>
@@ -279,10 +280,12 @@ SDValue X86SelectionDAGInfo::EmitTargetC<br>
EVT SizeVT = Size.getValueType();<br>
Results.push_back(DAG.getMemcpy(Chain, dl,<br>
DAG.getNode(ISD::ADD, dl, DstVT, Dst,<br>
- DAG.getConstant(Offset, DstVT)),<br>
+ DAG.getConstant(Offset, dl,<br>
+ DstVT)),<br>
DAG.getNode(ISD::ADD, dl, SrcVT, Src,<br>
- DAG.getConstant(Offset, SrcVT)),<br>
- DAG.getConstant(BytesLeft, SizeVT),<br>
+ DAG.getConstant(Offset, dl,<br>
+ SrcVT)),<br>
+ DAG.getConstant(BytesLeft, dl, SizeVT),<br>
Align, isVolatile, AlwaysInline, false,<br>
DstPtrInfo.getWithOffset(Offset),<br>
SrcPtrInfo.getWithOffset(Offset)));<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Tue Apr 28 06:56:37 2015<br>
@@ -47,8 +47,8 @@ namespace {<br>
<br>
/// getI32Imm - Return a target constant with the specified value, of type<br>
/// i32.<br>
- inline SDValue getI32Imm(unsigned Imm) {<br>
- return CurDAG->getTargetConstant(Imm, MVT::i32);<br>
+ inline SDValue getI32Imm(unsigned Imm, SDLoc dl) {<br>
+ return CurDAG->getTargetConstant(Imm, dl, MVT::i32);<br>
}<br>
<br>
inline bool immMskBitp(SDNode *inN) const {<br>
@@ -90,7 +90,7 @@ bool XCoreDAGToDAGISel::SelectADDRspii(S<br>
FrameIndexSDNode *FIN = nullptr;<br>
if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) {<br>
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);<br>
- Offset = CurDAG->getTargetConstant(0, MVT::i32);<br>
+ Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), MVT::i32);<br>
return true;<br>
}<br>
if (Addr.getOpcode() == ISD::ADD) {<br>
@@ -100,7 +100,8 @@ bool XCoreDAGToDAGISel::SelectADDRspii(S<br>
&& (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {<br>
// Constant positive word offset from frame index<br>
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);<br>
- Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32);<br>
+ Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),<br>
+ MVT::i32);<br>
return true;<br>
}<br>
}<br>
@@ -138,7 +139,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDNode<br>
if (immMskBitp(N)) {<br>
// Transformation function: get the size of a mask<br>
// Look for the first non-zero bit<br>
- SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val));<br>
+ SDValue MskSize = getI32Imm(32 - countLeadingZeros((uint32_t)Val), dl);<br>
return CurDAG->getMachineNode(XCore::MKMSK_rus, dl,<br>
MVT::i32, MskSize);<br>
}<br>
@@ -256,7 +257,7 @@ SDNode *XCoreDAGToDAGISel::SelectBRIND(S<br>
// after with clrsr 1. If any resources owned by the thread are ready an event<br>
// will be taken. If no resource is ready we branch to the address which was<br>
// the operand to the checkevent intrinsic.<br>
- SDValue constOne = getI32Imm(1);<br>
+ SDValue constOne = getI32Imm(1, dl);<br>
SDValue Glue =<br>
SDValue(CurDAG->getMachineNode(XCore::SETSR_branch_u6, dl, MVT::Glue,<br>
constOne, Chain), 0);<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Tue Apr 28 06:56:37 2015<br>
@@ -298,7 +298,7 @@ LowerGlobalAddress(SDValue Op, Selection<br>
GA = getGlobalAddressWrapper(GA, GV, DAG);<br>
// Handle the rest of the offset.<br>
if (Offset != FoldedOffset) {<br>
- SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32);<br>
+ SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, DL, MVT::i32);<br>
GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);<br>
}<br>
return GA;<br>
@@ -368,7 +368,7 @@ LowerBR_JT(SDValue Op, SelectionDAG &DAG<br>
}<br>
assert((NumEntries >> 31) == 0);<br>
SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,<br>
- DAG.getConstant(1, MVT::i32));<br>
+ DAG.getConstant(1, dl, MVT::i32));<br>
return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,<br>
ScaledIndex);<br>
}<br>
@@ -393,12 +393,12 @@ lowerLoadWordFromAlignedBasePlusOffset(S<br>
HighOffset);<br>
} else {<br>
LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,<br>
- DAG.getConstant(LowOffset, MVT::i32));<br>
+ DAG.getConstant(LowOffset, DL, MVT::i32));<br>
HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,<br>
- DAG.getConstant(HighOffset, MVT::i32));<br>
+ DAG.getConstant(HighOffset, DL, MVT::i32));<br>
}<br>
- SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32);<br>
- SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32);<br>
+ SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, DL, MVT::i32);<br>
+ SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, DL, MVT::i32);<br>
<br>
SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,<br>
LowAddr, MachinePointerInfo(),<br>
@@ -469,14 +469,14 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG)<br>
LD->isVolatile(), LD->isNonTemporal(),<br>
LD->isInvariant(), 2);<br>
SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,<br>
- DAG.getConstant(2, MVT::i32));<br>
+ DAG.getConstant(2, DL, MVT::i32));<br>
SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,<br>
HighAddr,<br>
LD->getPointerInfo().getWithOffset(2),<br>
MVT::i16, LD->isVolatile(),<br>
LD->isNonTemporal(), LD->isInvariant(), 2);<br>
SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,<br>
- DAG.getConstant(16, MVT::i32));<br>
+ DAG.getConstant(16, DL, MVT::i32));<br>
SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);<br>
Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),<br>
High.getValue(1));<br>
@@ -529,13 +529,13 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG<br>
if (ST->getAlignment() == 2) {<br>
SDValue Low = Value;<br>
SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,<br>
- DAG.getConstant(16, MVT::i32));<br>
+ DAG.getConstant(16, dl, MVT::i32));<br>
SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,<br>
ST->getPointerInfo(), MVT::i16,<br>
ST->isVolatile(), ST->isNonTemporal(),<br>
2);<br>
SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,<br>
- DAG.getConstant(2, MVT::i32));<br>
+ DAG.getConstant(2, dl, MVT::i32));<br>
SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,<br>
ST->getPointerInfo().getWithOffset(2),<br>
MVT::i16, ST->isVolatile(),<br>
@@ -573,7 +573,7 @@ LowerSMUL_LOHI(SDValue Op, SelectionDAG<br>
SDLoc dl(Op);<br>
SDValue LHS = Op.getOperand(0);<br>
SDValue RHS = Op.getOperand(1);<br>
- SDValue Zero = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Zero = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,<br>
DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,<br>
LHS, RHS);<br>
@@ -590,7 +590,7 @@ LowerUMUL_LOHI(SDValue Op, SelectionDAG<br>
SDLoc dl(Op);<br>
SDValue LHS = Op.getOperand(0);<br>
SDValue RHS = Op.getOperand(1);<br>
- SDValue Zero = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Zero = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,<br>
DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,<br>
Zero, Zero);<br>
@@ -675,13 +675,13 @@ TryExpandADDWithMul(SDNode *N, Selection<br>
SDLoc dl(N);<br>
SDValue LL, RL, AddendL, AddendH;<br>
LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Mul.getOperand(0), DAG.getConstant(0, MVT::i32));<br>
+ Mul.getOperand(0), DAG.getConstant(0, dl, MVT::i32));<br>
RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Mul.getOperand(1), DAG.getConstant(0, MVT::i32));<br>
+ Mul.getOperand(1), DAG.getConstant(0, dl, MVT::i32));<br>
AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Other, DAG.getConstant(0, MVT::i32));<br>
+ Other, DAG.getConstant(0, dl, MVT::i32));<br>
AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Other, DAG.getConstant(1, MVT::i32));<br>
+ Other, DAG.getConstant(1, dl, MVT::i32));<br>
APInt HighMask = APInt::getHighBitsSet(64, 32);<br>
unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));<br>
unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));<br>
@@ -704,9 +704,9 @@ TryExpandADDWithMul(SDNode *N, Selection<br>
}<br>
SDValue LH, RH;<br>
LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Mul.getOperand(0), DAG.getConstant(1, MVT::i32));<br>
+ Mul.getOperand(0), DAG.getConstant(1, dl, MVT::i32));<br>
RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Mul.getOperand(1), DAG.getConstant(1, MVT::i32));<br>
+ Mul.getOperand(1), DAG.getConstant(1, dl, MVT::i32));<br>
SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,<br>
DAG.getVTList(MVT::i32, MVT::i32), AddendH,<br>
AddendL, LL, RL);<br>
@@ -735,18 +735,22 @@ ExpandADDSUB(SDNode *N, SelectionDAG &DA<br>
<br>
// Extract components<br>
SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- N->getOperand(0), DAG.getConstant(0, MVT::i32));<br>
+ N->getOperand(0),<br>
+ DAG.getConstant(0, dl, MVT::i32));<br>
SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- N->getOperand(0), DAG.getConstant(1, MVT::i32));<br>
+ N->getOperand(0),<br>
+ DAG.getConstant(1, dl, MVT::i32));<br>
SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- N->getOperand(1), DAG.getConstant(0, MVT::i32));<br>
+ N->getOperand(1),<br>
+ DAG.getConstant(0, dl, MVT::i32));<br>
SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- N->getOperand(1), DAG.getConstant(1, MVT::i32));<br>
+ N->getOperand(1),<br>
+ DAG.getConstant(1, dl, MVT::i32));<br>
<br>
// Expand<br>
unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :<br>
XCoreISD::LSUB;<br>
- SDValue Zero = DAG.getConstant(0, MVT::i32);<br>
+ SDValue Zero = DAG.getConstant(0, dl, MVT::i32);<br>
SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),<br>
LHSL, RHSL, Zero);<br>
SDValue Carry(Lo.getNode(), 1);<br>
@@ -775,7 +779,8 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG<br>
false, false, false, 0);<br>
// Increment the pointer, VAList, to the next vararg<br>
SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,<br>
- DAG.getIntPtrConstant(VT.getSizeInBits() / 8));<br>
+ DAG.getIntPtrConstant(VT.getSizeInBits() / 8,<br>
+ dl));<br>
// Store the incremented VAList to the legalized pointer<br>
InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,<br>
MachinePointerInfo(SV), false, false, 0);<br>
@@ -910,30 +915,30 @@ LowerINIT_TRAMPOLINE(SDValue Op, Selecti<br>
SDValue Addr = Trmp;<br>
<br>
SDLoc dl(Op);<br>
- OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),<br>
- Addr, MachinePointerInfo(TrmpAddr), false, false,<br>
- 0);<br>
+ OutChains[0] = DAG.getStore(Chain, dl,<br>
+ DAG.getConstant(0x0a3cd805, dl, MVT::i32), Addr,<br>
+ MachinePointerInfo(TrmpAddr), false, false, 0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(4, MVT::i32));<br>
- OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),<br>
- Addr, MachinePointerInfo(TrmpAddr, 4), false,<br>
- false, 0);<br>
+ DAG.getConstant(4, dl, MVT::i32));<br>
+ OutChains[1] = DAG.getStore(Chain, dl,<br>
+ DAG.getConstant(0xd80456c0, dl, MVT::i32), Addr,<br>
+ MachinePointerInfo(TrmpAddr, 4), false, false, 0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(8, MVT::i32));<br>
- OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),<br>
- Addr, MachinePointerInfo(TrmpAddr, 8), false,<br>
- false, 0);<br>
+ DAG.getConstant(8, dl, MVT::i32));<br>
+ OutChains[2] = DAG.getStore(Chain, dl,<br>
+ DAG.getConstant(0x27fb0a3c, dl, MVT::i32), Addr,<br>
+ MachinePointerInfo(TrmpAddr, 8), false, false, 0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(12, MVT::i32));<br>
+ DAG.getConstant(12, dl, MVT::i32));<br>
OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,<br>
MachinePointerInfo(TrmpAddr, 12), false, false,<br>
0);<br>
<br>
Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,<br>
- DAG.getConstant(16, MVT::i32));<br>
+ DAG.getConstant(16, dl, MVT::i32));<br>
OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,<br>
MachinePointerInfo(TrmpAddr, 16), false, false,<br>
0);<br>
@@ -1096,7 +1101,7 @@ LowerCallResult(SDValue Chain, SDValue I<br>
int offset = ResultMemLocs[i].first;<br>
unsigned index = ResultMemLocs[i].second;<br>
SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);<br>
- SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };<br>
+ SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, dl, MVT::i32) };<br>
SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);<br>
InVals[index] = load;<br>
MemOpChains.push_back(load.getValue(1));<br>
@@ -1145,7 +1150,7 @@ XCoreTargetLowering::LowerCCCCallTo(SDVa<br>
// Get a count of how many bytes are to be pushed on the stack.<br>
unsigned NumBytes = RetCCInfo.getNextStackOffset();<br>
<br>
- Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,<br>
+ Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes, dl,<br>
getPointerTy(), true), dl);<br>
<br>
SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;<br>
@@ -1182,7 +1187,8 @@ XCoreTargetLowering::LowerCCCCallTo(SDVa<br>
<br>
MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,<br>
Chain, Arg,<br>
- DAG.getConstant(Offset/4, MVT::i32)));<br>
+ DAG.getConstant(Offset/4, dl,<br>
+ MVT::i32)));<br>
}<br>
}<br>
<br>
@@ -1233,8 +1239,9 @@ XCoreTargetLowering::LowerCCCCallTo(SDVa<br>
<br>
// Create the CALLSEQ_END node.<br>
Chain = DAG.getCALLSEQ_END(Chain,<br>
- DAG.getConstant(NumBytes, getPointerTy(), true),<br>
- DAG.getConstant(0, getPointerTy(), true),<br>
+ DAG.getConstant(NumBytes, dl, getPointerTy(),<br>
+ true),<br>
+ DAG.getConstant(0, dl, getPointerTy(), true),<br>
InFlag, dl);<br>
InFlag = Chain.getValue(1);<br>
<br>
@@ -1422,7 +1429,7 @@ XCoreTargetLowering::LowerCCCArguments(S<br>
SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);<br>
InVals.push_back(FIN);<br>
MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,<br>
- DAG.getConstant(Size, MVT::i32),<br>
+ DAG.getConstant(Size, dl, MVT::i32),<br>
Align, false, false, false,<br>
MachinePointerInfo(),<br>
MachinePointerInfo()));<br>
@@ -1487,7 +1494,7 @@ XCoreTargetLowering::LowerReturn(SDValue<br>
SmallVector<SDValue, 4> RetOps(1, Chain);<br>
<br>
// Return on XCore is always a "retsp 0"<br>
- RetOps.push_back(DAG.getConstant(0, MVT::i32));<br>
+ RetOps.push_back(DAG.getConstant(0, dl, MVT::i32));<br>
<br>
SmallVector<SDValue, 4> MemOpChains;<br>
// Handle return values that must be copied to memory.<br>
@@ -1671,9 +1678,9 @@ SDValue XCoreTargetLowering::PerformDAGC<br>
<br>
// fold (ladd 0, 0, x) -> 0, x & 1<br>
if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {<br>
- SDValue Carry = DAG.getConstant(0, VT);<br>
+ SDValue Carry = DAG.getConstant(0, dl, VT);<br>
SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,<br>
- DAG.getConstant(1, VT));<br>
+ DAG.getConstant(1, dl, VT));<br>
SDValue Ops[] = { Result, Carry };<br>
return DAG.getMergeValues(Ops, dl);<br>
}<br>
@@ -<a href="tel:1686" value="+491686" target="_blank">1686</a>,7 +1693,7 @@ SDValue XCoreTargetLowering::PerformDAGC<br>
VT.getSizeInBits() - 1);<br>
DAG.computeKnownBits(N2, KnownZero, KnownOne);<br>
if ((KnownZero & Mask) == Mask) {<br>
- SDValue Carry = DAG.getConstant(0, VT);<br>
+ SDValue Carry = DAG.getConstant(0, dl, VT);<br>
SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);<br>
SDValue Ops[] = { Result, Carry };<br>
return DAG.getMergeValues(Ops, dl);<br>
@@ -1711,7 +1718,7 @@ SDValue XCoreTargetLowering::PerformDAGC<br>
if ((KnownZero & Mask) == Mask) {<br>
SDValue Borrow = N2;<br>
SDValue Result = DAG.getNode(ISD::SUB, dl, VT,<br>
- DAG.getConstant(0, VT), N2);<br>
+ DAG.getConstant(0, dl, VT), N2);<br>
SDValue Ops[] = { Result, Borrow };<br>
return DAG.getMergeValues(Ops, dl);<br>
}<br>
@@ -1725,7 +1732,7 @@ SDValue XCoreTargetLowering::PerformDAGC<br>
VT.getSizeInBits() - 1);<br>
DAG.computeKnownBits(N2, KnownZero, KnownOne);<br>
if ((KnownZero & Mask) == Mask) {<br>
- SDValue Borrow = DAG.getConstant(0, VT);<br>
+ SDValue Borrow = DAG.getConstant(0, dl, VT);<br>
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);<br>
SDValue Ops[] = { Result, Borrow };<br>
return DAG.getMergeValues(Ops, dl);<br>
@@ -1791,13 +1798,13 @@ SDValue XCoreTargetLowering::PerformDAGC<br>
DAG.MaskedValueIsZero(Addend0, HighMask) &&<br>
DAG.MaskedValueIsZero(Addend1, HighMask)) {<br>
SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Mul0, DAG.getConstant(0, MVT::i32));<br>
+ Mul0, DAG.getConstant(0, dl, MVT::i32));<br>
SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Mul1, DAG.getConstant(0, MVT::i32));<br>
+ Mul1, DAG.getConstant(0, dl, MVT::i32));<br>
SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Addend0, DAG.getConstant(0, MVT::i32));<br>
+ Addend0, DAG.getConstant(0, dl, MVT::i32));<br>
SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,<br>
- Addend1, DAG.getConstant(0, MVT::i32));<br>
+ Addend1, DAG.getConstant(0, dl, MVT::i32));<br>
SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,<br>
DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,<br>
Addend0L, Addend1L);<br>
@@ -1837,7 +1844,7 @@ SDValue XCoreTargetLowering::PerformDAGC<br>
bool isTail = isInTailCallPosition(DAG, ST, Chain);<br>
return DAG.getMemmove(Chain, dl, ST->getBasePtr(),<br>
LD->getBasePtr(),<br>
- DAG.getConstant(StoreBits/8, MVT::i32),<br>
+ DAG.getConstant(StoreBits/8, dl, MVT::i32),<br>
Alignment, false, isTail, ST->getPointerInfo(),<br>
LD->getPointerInfo());<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=235977&r1=235976&r2=235977&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=235977&r1=235976&r2=235977&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue Apr 28 06:56:37 2015<br>
@@ -94,33 +94,34 @@ def XCoreMemBarrier : SDNode<"XCoreISD::<br>
def div4_xform : SDNodeXForm<imm, [{<br>
// Transformation function: imm/4<br>
assert(N->getZExtValue() % 4 == 0);<br>
- return getI32Imm(N->getZExtValue()/4);<br>
+ return getI32Imm(N->getZExtValue()/4, SDLoc(N));<br>
}]>;<br>
<br>
def msksize_xform : SDNodeXForm<imm, [{<br>
// Transformation function: get the size of a mask<br>
assert(isMask_32(N->getZExtValue()));<br>
// look for the first non-zero bit<br>
- return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()));<br>
+ return getI32Imm(32 - countLeadingZeros((uint32_t)N->getZExtValue()),<br>
+ SDLoc(N));<br>
}]>;<br>
<br>
def neg_xform : SDNodeXForm<imm, [{<br>
// Transformation function: -imm<br>
uint32_t value = N->getZExtValue();<br>
- return getI32Imm(-value);<br>
+ return getI32Imm(-value, SDLoc(N));<br>
}]>;<br>
<br>
def bpwsub_xform : SDNodeXForm<imm, [{<br>
// Transformation function: 32-imm<br>
uint32_t value = N->getZExtValue();<br>
- return getI32Imm(32-value);<br>
+ return getI32Imm(32 - value, SDLoc(N));<br>
}]>;<br>
<br>
def div4neg_xform : SDNodeXForm<imm, [{<br>
// Transformation function: -imm/4<br>
uint32_t value = N->getZExtValue();<br>
assert(-value % 4 == 0);<br>
- return getI32Imm(-value/4);<br>
+ return getI32Imm(-value/4, SDLoc(N));<br>
}]>;<br>
<br>
def immUs4Neg : PatLeaf<(imm), [{<br>
<br>
Added: llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll?rev=235977&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll?rev=235977&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll (added)<br>
+++ llvm/trunk/test/DebugInfo/AArch64/constant-dbgloc.ll Tue Apr 28 06:56:37 2015<br>
@@ -0,0 +1,37 @@<br>
+; RUN: llc -filetype=asm %s -o - | FileCheck %s<br>
+<br>
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+target triple = "aarch64--linux-gnueabihf"<br>
+<br>
+; int<br>
+; main(void)<br>
+; {<br>
+; return -1;<br>
+; }<br>
+<br>
+; CHECK: test.c:4:5<br>
+; CHECK: movn<br>
+<br>
+; Function Attrs: nounwind<br>
+define i32 @main() {<br>
+entry:<br>
+ %retval = alloca i32, align 4<br>
+ store i32 0, i32* %retval<br>
+ ret i32 -1, !dbg !11<br>
+}<br>
+<br>
+!<a href="http://llvm.dbg.cu" target="_blank">llvm.dbg.cu</a> = !{!0}<br>
+!llvm.module.flags = !{!8, !9}<br>
+<br>
+!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)<br>
+!1 = !MDFile(filename: "test.c", directory: "/home/user/clang/build")<br>
+!2 = !{}<br>
+!3 = !{!4}<br>
+!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)<br>
+!5 = !MDSubroutineType(types: !6)<br>
+!6 = !{!7}<br>
+!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)<br>
+!8 = !{i32 2, !"Dwarf Version", i32 4}<br>
+!9 = !{i32 2, !"Debug Info Version", i32 3}<br>
+!10 = !{i32 1, !"wchar_size", i32 4}<br>
+!11 = !MDLocation(line: 4, column: 5, scope: !4)<br>
<br>
Added: llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll?rev=235977&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll?rev=235977&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll (added)<br>
+++ llvm/trunk/test/DebugInfo/ARM/constant-dbgloc.ll Tue Apr 28 06:56:37 2015<br>
@@ -0,0 +1,37 @@<br>
+; RUN: llc -filetype=asm %s -o - | FileCheck %s<br>
+<br>
+target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"<br>
+target triple = "armv7--linux-gnueabihf"<br>
+<br>
+; int<br>
+; main(void)<br>
+; {<br>
+; return -1;<br>
+; }<br>
+<br>
+; CHECK: test.c:4:5<br>
+; CHECK: mvn<br>
+<br>
+; Function Attrs: nounwind<br>
+define i32 @main() {<br>
+entry:<br>
+ %retval = alloca i32, align 4<br>
+ store i32 0, i32* %retval<br>
+ ret i32 -1, !dbg !11<br>
+}<br>
+<br>
+!<a href="http://llvm.dbg.cu" target="_blank">llvm.dbg.cu</a> = !{!0}<br>
+!llvm.module.flags = !{!8, !9}<br>
+<br>
+!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)<br>
+!1 = !MDFile(filename: "test.c", directory: "/home/user/clang/build")<br>
+!2 = !{}<br>
+!3 = !{!4}<br>
+!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)<br>
+!5 = !MDSubroutineType(types: !6)<br>
+!6 = !{!7}<br>
+!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)<br>
+!8 = !{i32 2, !"Dwarf Version", i32 4}<br>
+!9 = !{i32 2, !"Debug Info Version", i32 3}<br>
+!10 = !{i32 1, !"wchar_size", i32 4}<br>
+!11 = !MDLocation(line: 4, column: 5, scope: !4)<br>
<br>
Added: llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll?rev=235977&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll?rev=235977&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll (added)<br>
+++ llvm/trunk/test/DebugInfo/constant-sdnodes-have-dbg-location.ll Tue Apr 28 06:56:37 2015<br>
@@ -0,0 +1,25 @@<br>
+; RUN: llc -debug < %s 2>&1 | FileCheck %s<br>
+<br>
+; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<-1>test.c:4:5<br>
+<br>
+define i32 @main() {<br>
+entry:<br>
+ %retval = alloca i32, align 4<br>
+ store i32 0, i32* %retval<br>
+ ret i32 -1, !dbg !10<br>
+}<br>
+<br>
+!<a href="http://llvm.dbg.cu" target="_blank">llvm.dbg.cu</a> = !{!0}<br>
+!llvm.module.flags = !{!8, !9}<br>
+<br>
+!0 = !MDCompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, subprograms: !3)<br>
+!1 = !MDFile(filename: "test.c", directory: "/home/user/clang-llvm/build")<br>
+!2 = !{}<br>
+!3 = !{!4}<br>
+!4 = !MDSubprogram(name: "main", scope: !1, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: false, function: i32 ()* @main, variables: !2)<br>
+!5 = !MDSubroutineType(types: !6)<br>
+!6 = !{!7}<br>
+!7 = !MDBasicType(name: "int", size: 32, align: 32, encoding: DW_ATE_signed)<br>
+!8 = !{i32 2, !"Dwarf Version", i32 4}<br>
+!9 = !{i32 2, !"Debug Info Version", i32 3}<br>
+!10 = !MDLocation(line: 4, column: 5, scope: !4)<br>
<br>
<br>
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</blockquote></div><br></div>
</blockquote></div><br></div>