<div dir="ltr">Looks like CHECK-DAG semantics are insufficient to test what I want. For e.g., here is a set of rules:<div><br></div><div>
<pre style="color:rgb(0,0,0);font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;word-spacing:0px">$ cat rules
; CHECK-LABEL: label1:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: ins
; CHECK-LABEL: label2:
; CHECK-DAG: fcvt
; CHECK-DAG: fcvt
; CHECK-DAG: ins</pre>
<pre style="color:rgb(0,0,0);font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;word-spacing:0px">$ cat output
label1:
fcvt
wrong
ins
label2:
fcvt
fcvt
fcvt
ins</pre>
<pre style="color:rgb(0,0,0);font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;word-spacing:0px"><pre style="color:rgb(0,0,0);font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;word-spacing:0px">$ FileCheck rules < output # FileCheck succeeds
$ </pre></pre>
<br></div><div>(a) One match can satisfy multiple CHECK-DAG directives (only one 'fcvt' in label1: block in output)</div><div>(b) Multiple matches for the same CHECK-DAG (three instances of 'fcvt' in label2: block)</div><div>(c) Cannot reject strings not present in CHECK-DAG directives ('wrong' in label1: block)</div><div><br></div><div>Using CHECK-DAG to harden against non-determinism in instruction scheduling wouldn't work. For instance, we cannot check that exactly conversions happen in a function.</div><div><br></div><div>For now, I'll change the FP16 test to check for conversion instructions with 'CHECK' (ala CHECK-LIBCALL in the same file). If I find a way to reliably check for extraneous loads and conversions later, I'll revisit this test.</div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Apr 18, 2015 at 1:02 PM, Michael Zolotukhin <span dir="ltr"><<a href="mailto:mzolotukhin@apple.com" target="_blank">mzolotukhin@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><br><div><blockquote type="cite"><div>On Apr 18, 2015, at 12:46 PM, Pirama Arumuga Nainar <<a href="mailto:pirama@google.com" target="_blank">pirama@google.com</a>> wrote:</div><br><div><p dir="ltr">Hi Michael,</p><p dir="ltr">The tests need to be more flexible. For some reason, I thought register allocation would be deterministic.</p><p dir="ltr">I'd still want to check the entire function so extraneous load/stores or conversions don't creep up. I'll make the tests check only the instructions and ignore the registers. It will be too much trouble introducing named variables to such a large test.</p></div></blockquote>I see, thanks!<br><blockquote type="cite"><div><p dir="ltr">Do you think the instruction scheduling is deterministic, and it's only the registers that can vary?</p></div></blockquote>In our case the scheduling was the same, but I’d prefer to have a test that doesn’t depend on it to avoid possible false failures in future (if that’s possible of course). Maybe we could use CHECK-DAG directive help here?</div><div><br></div><div>Thanks,</div><div>Michael<br><blockquote type="cite"><div><p dir="ltr">Thanks,<br>
Pirama</p>
<div class="gmail_quote">On Apr 18, 2015 12:29 PM, "Michael Zolotukhin" <<a href="mailto:mzolotukhin@apple.com" target="_blank">mzolotukhin@apple.com</a>> wrote:<br type="attribution"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi Pirama,<br>
<br>
Do we really need the tests to be so explicit?<br>
> +; CHECK-FP16-LABEL: test_fadd:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vadd.f32 s0, s2, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fadd:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vadd.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fadd(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fadd half %a, %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
E.g. do we really need to check register names, or they can be replaced with a regex? Or, even better, maybe it’s sufficient to just check that some instruction is present/absent in the output?<br>
<br>
In the current state the tests are very fragile, and we internally got a failure on this. The generated assembler was:<br>
test_fadd:<br>
.fnstart<br>
ldrh r2, [r0]<br>
ldrh r1, [r1]<br>
vmov s0, r1<br>
vmov s4, r2<br>
vcvtb.f32.f16 s0, s0<br>
vcvtb.f32.f16 s4, s4<br>
vadd.f32 s0, s4, s0<br>
vcvtb.f16.f32 s0, s0<br>
vmov r1, s0<br>
strh r1, [r0]<br>
bx lr<br>
(Note usage of register s4 instead of s2).<br>
<br>
It’s very hard to say whether it’s a correct behavior or not (but looks correct to me). Is it possible to make the test more versatile, and maybe add some comments to it?<br>
<br>
Thanks,<br>
Michael<br>
<br>
> On Apr 17, 2015, at 11:36 AM, Pirama Arumuga Nainar <<a href="mailto:pirama@google.com" target="_blank">pirama@google.com</a>> wrote:<br>
><br>
> Author: pirama<br>
> Date: Fri Apr 17 13:36:25 2015<br>
> New Revision: 235215<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=235215&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=235215&view=rev</a><br>
> Log:<br>
> Add support to promote f16 to f32<br>
><br>
> Summary:<br>
> This patch adds legalization support to operate on FP16 as a load/store type<br>
> and do operations on it as floats.<br>
><br>
> Tests for ARM are added to test/CodeGen/ARM/fp16-promote.ll<br>
><br>
> Reviewers: srhines, t.p.northover<br>
><br>
> Differential Revision: <a href="http://reviews.llvm.org/D8755" target="_blank">http://reviews.llvm.org/D8755</a><br>
><br>
> Added:<br>
> llvm/trunk/test/CodeGen/ARM/fp16-promote.ll<br>
> Modified:<br>
> llvm/trunk/include/llvm/Target/TargetLowering.h<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp<br>
> llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
> llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
><br>
> Modified: llvm/trunk/include/llvm/Target/TargetLowering.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/include/llvm/Target/TargetLowering.h (original)<br>
> +++ llvm/trunk/include/llvm/Target/TargetLowering.h Fri Apr 17 13:36:25 2015<br>
> @@ -100,7 +100,8 @@ public:<br>
> TypeExpandFloat, // Split this float into two of half the size.<br>
> TypeScalarizeVector, // Replace this one-element vector with its element.<br>
> TypeSplitVector, // Split this vector into two of half the size.<br>
> - TypeWidenVector // This vector should be widened into a larger vector.<br>
> + TypeWidenVector, // This vector should be widened into a larger vector.<br>
> + TypePromoteFloat // Replace this float with a larger one.<br>
> };<br>
><br>
> /// LegalizeKind holds the legalization kind that needs to happen to EVT<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Fri Apr 17 13:36:25 2015<br>
> @@ -307,6 +307,7 @@ namespace {<br>
> SDValue visitINSERT_SUBVECTOR(SDNode *N);<br>
> SDValue visitMLOAD(SDNode *N);<br>
> SDValue visitMSTORE(SDNode *N);<br>
> + SDValue visitFP_TO_FP16(SDNode *N);<br>
><br>
> SDValue XformToShuffleWithZero(SDNode *N);<br>
> SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS);<br>
> @@ -1380,6 +1381,7 @@ SDValue DAGCombiner::visit(SDNode *N) {<br>
> case ISD::INSERT_SUBVECTOR: return visitINSERT_SUBVECTOR(N);<br>
> case ISD::MLOAD: return visitMLOAD(N);<br>
> case ISD::MSTORE: return visitMSTORE(N);<br>
> + case ISD::FP_TO_FP16: return visitFP_TO_FP16(N);<br>
> }<br>
> return SDValue();<br>
> }<br>
> @@ -8161,6 +8163,11 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNo<br>
> if (isConstantFPBuildVectorOrConstantFP(N0))<br>
> return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0);<br>
><br>
> + // fold (fp_extend (fp16_to_fp op)) -> (fp16_to_fp op)<br>
> + if (N0.getOpcode() == ISD::FP16_TO_FP &&<br>
> + TLI.getOperationAction(ISD::FP16_TO_FP, VT) == TargetLowering::Legal)<br>
> + return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), VT, N0.getOperand(0));<br>
> +<br>
> // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the<br>
> // value of X.<br>
> if (N0.getOpcode() == ISD::FP_ROUND<br>
> @@ -12348,6 +12355,16 @@ SDValue DAGCombiner::visitINSERT_SUBVECT<br>
><br>
> return SDValue();<br>
> }<br>
> +<br>
> +SDValue DAGCombiner::visitFP_TO_FP16(SDNode *N) {<br>
> + SDValue N0 = N->getOperand(0);<br>
> +<br>
> + // fold (fp_to_fp16 (fp16_to_fp op)) -> op<br>
> + if (N0->getOpcode() == ISD::FP16_TO_FP)<br>
> + return N0->getOperand(0);<br>
> +<br>
> + return SDValue();<br>
> +}<br>
><br>
> /// Returns a vector_shuffle if it able to transform an AND to a vector_shuffle<br>
> /// with the destination vector and a zero vector.<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp Fri Apr 17 13:36:25 2015<br>
> @@ -1579,3 +1579,420 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_<br>
> return DAG.getTruncStore(Chain, SDLoc(N), Hi, Ptr,<br>
> ST->getMemoryVT(), ST->getMemOperand());<br>
> }<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Float Operand Promotion<br>
> +//===----------------------------------------------------------------------===//<br>
> +//<br>
> +<br>
> +static ISD::NodeType GetPromotionOpcode(EVT OpVT, EVT RetVT) {<br>
> + if (OpVT == MVT::f16) {<br>
> + return ISD::FP16_TO_FP;<br>
> + } else if (RetVT == MVT::f16) {<br>
> + return ISD::FP_TO_FP16;<br>
> + }<br>
> +<br>
> + report_fatal_error("Attempt at an invalid promotion-related conversion");<br>
> +}<br>
> +<br>
> +bool DAGTypeLegalizer::PromoteFloatOperand(SDNode *N, unsigned OpNo) {<br>
> + SDValue R = SDValue();<br>
> +<br>
> + // Nodes that use a promotion-requiring floating point operand, but doesn't<br>
> + // produce a promotion-requiring floating point result, need to be legalized<br>
> + // to use the promoted float operand. Nodes that produce at least one<br>
> + // promotion-requiring floating point result have their operands legalized as<br>
> + // a part of PromoteFloatResult.<br>
> + switch (N->getOpcode()) {<br>
> + default:<br>
> + llvm_unreachable("Do not know how to promote this operator's operand!");<br>
> +<br>
> + case ISD::BITCAST: R = PromoteFloatOp_BITCAST(N, OpNo); break;<br>
> + case ISD::FCOPYSIGN: R = PromoteFloatOp_FCOPYSIGN(N, OpNo); break;<br>
> + case ISD::FP_TO_SINT:<br>
> + case ISD::FP_TO_UINT: R = PromoteFloatOp_FP_TO_XINT(N, OpNo); break;<br>
> + case ISD::FP_EXTEND: R = PromoteFloatOp_FP_EXTEND(N, OpNo); break;<br>
> + case ISD::SELECT_CC: R = PromoteFloatOp_SELECT_CC(N, OpNo); break;<br>
> + case ISD::SETCC: R = PromoteFloatOp_SETCC(N, OpNo); break;<br>
> + case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;<br>
> + }<br>
> +<br>
> + if (R.getNode())<br>
> + ReplaceValueWith(SDValue(N, 0), R);<br>
> + return false;<br>
> +}<br>
> +<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo) {<br>
> + SDValue Op = N->getOperand(0);<br>
> + EVT OpVT = Op->getValueType(0);<br>
> +<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT IVT = EVT::getIntegerVT(*DAG.getContext(), OpVT.getSizeInBits());<br>
> + assert (IVT == VT && "Bitcast to type of different size");<br>
> +<br>
> + SDValue Promoted = GetPromotedFloat(N->getOperand(0));<br>
> + EVT PromotedVT = Promoted->getValueType(0);<br>
> +<br>
> + // Convert the promoted float value to the desired IVT.<br>
> + return DAG.getNode(GetPromotionOpcode(PromotedVT, OpVT), SDLoc(N), IVT,<br>
> + Promoted);<br>
> +}<br>
> +<br>
> +// Promote Operand 1 of FCOPYSIGN. Operand 0 ought to be handled by<br>
> +// PromoteFloatRes_FCOPYSIGN.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo) {<br>
> + assert (OpNo == 1 && "Only Operand 1 must need promotion here");<br>
> + SDValue Op1 = GetPromotedFloat(N->getOperand(1));<br>
> +<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),<br>
> + N->getOperand(0), Op1);<br>
> +}<br>
> +<br>
> +// Convert the promoted float value to the desired integer type<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo) {<br>
> + SDValue Op = GetPromotedFloat(N->getOperand(0));<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), Op);<br>
> +}<br>
> +<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo) {<br>
> + SDValue Op = GetPromotedFloat(N->getOperand(0));<br>
> + EVT VT = N->getValueType(0);<br>
> +<br>
> + // Desired VT is same as promoted type. Use promoted float directly.<br>
> + if (VT == Op->getValueType(0))<br>
> + return Op;<br>
> +<br>
> + // Else, extend the promoted float value to the desired VT.<br>
> + return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Op);<br>
> +}<br>
> +<br>
> +// Promote the float operands used for comparison. The true- and false-<br>
> +// operands have the same type as the result and are promoted, if needed, by<br>
> +// PromoteFloatRes_SELECT_CC<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo) {<br>
> + SDValue LHS = GetPromotedFloat(N->getOperand(0));<br>
> + SDValue RHS = GetPromotedFloat(N->getOperand(1));<br>
> +<br>
> + return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),<br>
> + LHS, RHS, N->getOperand(2), N->getOperand(3),<br>
> + N->getOperand(4));<br>
> +}<br>
> +<br>
> +// Construct a SETCC that compares the promoted values and sets the conditional<br>
> +// code.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + SDValue Op0 = GetPromotedFloat(N->getOperand(0));<br>
> + SDValue Op1 = GetPromotedFloat(N->getOperand(1));<br>
> + ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get();<br>
> +<br>
> + return DAG.getSetCC(SDLoc(N), NVT, Op0, Op1, CCCode);<br>
> +<br>
> +}<br>
> +<br>
> +// Lower the promoted Float down to the integer value of same size and construct<br>
> +// a STORE of the integer value.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatOp_STORE(SDNode *N, unsigned OpNo) {<br>
> + StoreSDNode *ST = cast<StoreSDNode>(N);<br>
> + SDValue Val = ST->getValue();<br>
> + SDLoc DL(N);<br>
> +<br>
> + SDValue Promoted = GetPromotedFloat(Val);<br>
> + EVT VT = ST->getOperand(1)->getValueType(0);<br>
> + EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());<br>
> +<br>
> + SDValue NewVal;<br>
> + NewVal = DAG.getNode(GetPromotionOpcode(Promoted.getValueType(), VT), DL,<br>
> + IVT, Promoted);<br>
> +<br>
> + return DAG.getStore(ST->getChain(), DL, NewVal, ST->getBasePtr(),<br>
> + ST->getMemOperand());<br>
> +}<br>
> +<br>
> +//===----------------------------------------------------------------------===//<br>
> +// Float Result Promotion<br>
> +//===----------------------------------------------------------------------===//<br>
> +<br>
> +void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {<br>
> + SDValue R = SDValue();<br>
> +<br>
> + switch (N->getOpcode()) {<br>
> + // These opcodes cannot appear if promotion of FP16 is done in the backend<br>
> + // instead of Clang<br>
> + case ISD::FP16_TO_FP:<br>
> + case ISD::FP_TO_FP16:<br>
> + default:<br>
> + llvm_unreachable("Do not know how to promote this operator's result!");<br>
> +<br>
> + case ISD::BITCAST: R = PromoteFloatRes_BITCAST(N); break;<br>
> + case ISD::ConstantFP: R = PromoteFloatRes_ConstantFP(N); break;<br>
> + case ISD::EXTRACT_VECTOR_ELT:<br>
> + R = PromoteFloatRes_EXTRACT_VECTOR_ELT(N); break;<br>
> + case ISD::FCOPYSIGN: R = PromoteFloatRes_FCOPYSIGN(N); break;<br>
> +<br>
> + // Unary FP Operations<br>
> + case ISD::FABS:<br>
> + case ISD::FCEIL:<br>
> + case ISD::FCOS:<br>
> + case ISD::FEXP:<br>
> + case ISD::FEXP2:<br>
> + case ISD::FFLOOR:<br>
> + case ISD::FLOG:<br>
> + case ISD::FLOG2:<br>
> + case ISD::FLOG10:<br>
> + case ISD::FNEARBYINT:<br>
> + case ISD::FNEG:<br>
> + case ISD::FRINT:<br>
> + case ISD::FROUND:<br>
> + case ISD::FSIN:<br>
> + case ISD::FSQRT:<br>
> + case ISD::FTRUNC: R = PromoteFloatRes_UnaryOp(N); break;<br>
> +<br>
> + // Binary FP Operations<br>
> + case ISD::FADD:<br>
> + case ISD::FDIV:<br>
> + case ISD::FMAXNUM:<br>
> + case ISD::FMINNUM:<br>
> + case ISD::FMUL:<br>
> + case ISD::FPOW:<br>
> + case ISD::FREM:<br>
> + case ISD::FSUB: R = PromoteFloatRes_BinOp(N); break;<br>
> +<br>
> + case ISD::FMA: // FMA is same as FMAD<br>
> + case ISD::FMAD: R = PromoteFloatRes_FMAD(N); break;<br>
> +<br>
> + case ISD::FPOWI: R = PromoteFloatRes_FPOWI(N); break;<br>
> +<br>
> + case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;<br>
> + case ISD::LOAD: R = PromoteFloatRes_LOAD(N); break;<br>
> + case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break;<br>
> + case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break;<br>
> +<br>
> + case ISD::SINT_TO_FP:<br>
> + case ISD::UINT_TO_FP: R = PromoteFloatRes_XINT_TO_FP(N); break;<br>
> + case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;<br>
> +<br>
> + }<br>
> +<br>
> + if (R.getNode())<br>
> + SetPromotedFloat(SDValue(N, ResNo), R);<br>
> +}<br>
> +<br>
> +// Bitcast from i16 to f16: convert the i16 to a f32 value instead.<br>
> +// At this point, it is not possible to determine if the bitcast value is<br>
> +// eventually stored to memory or promoted to f32 or promoted to a floating<br>
> +// point at a higher precision. Some of these cases are handled by FP_EXTEND,<br>
> +// STORE promotion handlers.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_BITCAST(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT,<br>
> + N->getOperand(0));<br>
> +}<br>
> +<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_ConstantFP(SDNode *N) {<br>
> + ConstantFPSDNode *CFPNode = cast<ConstantFPSDNode>(N);<br>
> + EVT VT = N->getValueType(0);<br>
> +<br>
> + // Get the (bit-cast) APInt of the APFloat and build an integer constant<br>
> + EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());<br>
> + SDValue C = DAG.getConstant(CFPNode->getValueAPF().bitcastToAPInt(),<br>
> + IVT);<br>
> +<br>
> + // Convert the Constant to the desired FP type<br>
> + // FIXME We might be able to do the conversion during compilation and get rid<br>
> + // of it from the object code<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, C);<br>
> +}<br>
> +<br>
> +// If the Index operand is a constant, try to redirect the extract operation to<br>
> +// the correct legalized vector. If not, bit-convert the input vector to<br>
> +// equivalent integer vector. Extract the element as an (bit-cast) integer<br>
> +// value and convert it to the promoted type.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) {<br>
> + SDLoc DL(N);<br>
> +<br>
> + // If the index is constant, try to extract the value from the legalized<br>
> + // vector type.<br>
> + if (isa<ConstantSDNode>(N->getOperand(1))) {<br>
> + SDValue Vec = N->getOperand(0);<br>
> + SDValue Idx = N->getOperand(1);<br>
> + EVT VecVT = Vec->getValueType(0);<br>
> + EVT EltVT = VecVT.getVectorElementType();<br>
> +<br>
> + uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();<br>
> +<br>
> + switch (getTypeAction(VecVT)) {<br>
> + default: break;<br>
> + case TargetLowering::TypeScalarizeVector: {<br>
> + SDValue Res = GetScalarizedVector(N->getOperand(0));<br>
> + ReplaceValueWith(SDValue(N, 0), Res);<br>
> + return SDValue();<br>
> + }<br>
> + case TargetLowering::TypeWidenVector: {<br>
> + Vec = GetWidenedVector(Vec);<br>
> + SDValue Res = DAG.getNode(N->getOpcode(), DL, EltVT, Vec, Idx);<br>
> + ReplaceValueWith(SDValue(N, 0), Res);<br>
> + return SDValue();<br>
> + }<br>
> + case TargetLowering::TypeSplitVector: {<br>
> + SDValue Lo, Hi;<br>
> + GetSplitVector(Vec, Lo, Hi);<br>
> +<br>
> + uint64_t LoElts = Lo.getValueType().getVectorNumElements();<br>
> + SDValue Res;<br>
> + if (IdxVal < LoElts)<br>
> + Res = DAG.getNode(N->getOpcode(), DL, EltVT, Lo, Idx);<br>
> + else<br>
> + Res = DAG.getNode(N->getOpcode(), DL, EltVT, Hi,<br>
> + DAG.getConstant(IdxVal - LoElts,<br>
> + Idx.getValueType()));<br>
> + ReplaceValueWith(SDValue(N, 0), Res);<br>
> + return SDValue();<br>
> + }<br>
> +<br>
> + }<br>
> + }<br>
> +<br>
> + // Bit-convert the input vector to the equivalent integer vector<br>
> + SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0));<br>
> + EVT IVT = NewOp.getValueType().getVectorElementType();<br>
> +<br>
> + // Extract the element as an (bit-cast) integer value<br>
> + SDValue NewVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IVT,<br>
> + NewOp, N->getOperand(1));<br>
> +<br>
> + // Convert the element to the desired FP type<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, NewVal);<br>
> +}<br>
> +<br>
> +// FCOPYSIGN(X, Y) returns the value of X with the sign of Y. If the result<br>
> +// needs promotion, so does the argument X. Note that Y, if needed, will be<br>
> +// handled during operand promotion.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_FCOPYSIGN(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + SDValue Op0 = GetPromotedFloat(N->getOperand(0));<br>
> +<br>
> + SDValue Op1 = N->getOperand(1);<br>
> +<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);<br>
> +}<br>
> +<br>
> +// Unary operation where the result and the operand have PromoteFloat type<br>
> +// action. Construct a new SDNode with the promoted float value of the old<br>
> +// operand.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryOp(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + SDValue Op = GetPromotedFloat(N->getOperand(0));<br>
> +<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op);<br>
> +}<br>
> +<br>
> +// Binary operations where the result and both operands have PromoteFloat type<br>
> +// action. Construct a new SDNode with the promoted float values of the old<br>
> +// operands.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_BinOp(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + SDValue Op0 = GetPromotedFloat(N->getOperand(0));<br>
> + SDValue Op1 = GetPromotedFloat(N->getOperand(1));<br>
> +<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);<br>
> +}<br>
> +<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_FMAD(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + SDValue Op0 = GetPromotedFloat(N->getOperand(0));<br>
> + SDValue Op1 = GetPromotedFloat(N->getOperand(1));<br>
> + SDValue Op2 = GetPromotedFloat(N->getOperand(2));<br>
> +<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, Op2);<br>
> +}<br>
> +<br>
> +// Promote the Float (first) operand and retain the Integer (second) operand<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_FPOWI(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + SDValue Op0 = GetPromotedFloat(N->getOperand(0));<br>
> + SDValue Op1 = N->getOperand(1);<br>
> +<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1);<br>
> +}<br>
> +<br>
> +// Explicit operation to reduce precision. Reduce the value to half precision<br>
> +// and promote it back to the legal type.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_FP_ROUND(SDNode *N) {<br>
> + SDLoc DL(N);<br>
> +<br>
> + SDValue Op = N->getOperand(0);<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT OpVT = Op->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));<br>
> + EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());<br>
> +<br>
> + // Round promoted float to desired precision<br>
> + SDValue Round = DAG.getNode(GetPromotionOpcode(OpVT, VT), DL, IVT, Op);<br>
> + // Promote it back to the legal output type<br>
> + return DAG.getNode(GetPromotionOpcode(VT, NVT), DL, NVT, Round);<br>
> +}<br>
> +<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) {<br>
> + LoadSDNode *L = cast<LoadSDNode>(N);<br>
> + EVT VT = N->getValueType(0);<br>
> +<br>
> + // Load the value as an integer value with the same number of bits<br>
> + EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());<br>
> + SDValue newL = DAG.getLoad(L->getAddressingMode(), L->getExtensionType(),<br>
> + IVT, SDLoc(N), L->getChain(), L->getBasePtr(),<br>
> + L->getOffset(), L->getPointerInfo(), IVT, L->isVolatile(),<br>
> + L->isNonTemporal(), false, L->getAlignment(),<br>
> + L->getAAInfo());<br>
> + // Legalize the chain result by replacing uses of the old value chain with the<br>
> + // new one<br>
> + ReplaceValueWith(SDValue(N, 1), newL.getValue(1));<br>
> +<br>
> + // Convert the integer value to the desired FP type<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, newL);<br>
> +}<br>
> +<br>
> +// Construct a new SELECT node with the promoted true- and false- values.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(SDNode *N) {<br>
> + SDValue TrueVal = GetPromotedFloat(N->getOperand(1));<br>
> + SDValue FalseVal = GetPromotedFloat(N->getOperand(2));<br>
> +<br>
> + return DAG.getNode(ISD::SELECT, SDLoc(N), TrueVal->getValueType(0),<br>
> + N->getOperand(0), TrueVal, FalseVal);<br>
> +}<br>
> +<br>
> +// Construct a new SELECT_CC node with the promoted true- and false- values.<br>
> +// The operands used for comparison are promoted by PromoteFloatOp_SELECT_CC.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT_CC(SDNode *N) {<br>
> + SDValue TrueVal = GetPromotedFloat(N->getOperand(2));<br>
> + SDValue FalseVal = GetPromotedFloat(N->getOperand(3));<br>
> +<br>
> + return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N->getValueType(0),<br>
> + N->getOperand(0), N->getOperand(1), TrueVal, FalseVal,<br>
> + N->getOperand(4));<br>
> +}<br>
> +<br>
> +// Construct a SDNode that transforms the SINT or UINT operand to the promoted<br>
> +// float type.<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_XINT_TO_FP(SDNode *N) {<br>
> + EVT VT = N->getValueType(0);<br>
> + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);<br>
> + return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, N->getOperand(0));<br>
> +}<br>
> +<br>
> +SDValue DAGTypeLegalizer::PromoteFloatRes_UNDEF(SDNode *N) {<br>
> + return DAG.getUNDEF(TLI.getTypeToTransformTo(*DAG.getContext(),<br>
> + N->getValueType(0)));<br>
> +}<br>
> +<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Fri Apr 17 13:36:25 2015<br>
> @@ -251,6 +251,16 @@ SDValue DAGTypeLegalizer::PromoteIntRes_<br>
> case TargetLowering::TypeSoftenFloat:<br>
> // Promote the integer operand by hand.<br>
> return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp));<br>
> + case TargetLowering::TypePromoteFloat: {<br>
> + // Convert the promoted float by hand.<br>
> + if (NOutVT.bitsEq(NInVT)) {<br>
> + SDValue PromotedOp = GetPromotedFloat(InOp);<br>
> + SDValue Trunc = DAG.getNode(ISD::FP_TO_FP16, dl, NOutVT, PromotedOp);<br>
> + return DAG.getNode(ISD::AssertZext, dl, NOutVT, Trunc,<br>
> + DAG.getValueType(OutVT));<br>
> + }<br>
> + break;<br>
> + }<br>
> case TargetLowering::TypeExpandInteger:<br>
> case TargetLowering::TypeExpandFloat:<br>
> break;<br>
> @@ -1845,7 +1855,11 @@ void DAGTypeLegalizer::ExpandIntRes_FP_T<br>
> SDValue &Hi) {<br>
> SDLoc dl(N);<br>
> EVT VT = N->getValueType(0);<br>
> +<br>
> SDValue Op = N->getOperand(0);<br>
> + if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)<br>
> + Op = GetPromotedFloat(Op);<br>
> +<br>
> RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);<br>
> assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");<br>
> SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, true/*irrelevant*/,<br>
> @@ -1857,7 +1871,11 @@ void DAGTypeLegalizer::ExpandIntRes_FP_T<br>
> SDValue &Hi) {<br>
> SDLoc dl(N);<br>
> EVT VT = N->getValueType(0);<br>
> +<br>
> SDValue Op = N->getOperand(0);<br>
> + if (getTypeAction(Op.getValueType()) == TargetLowering::TypePromoteFloat)<br>
> + Op = GetPromotedFloat(Op);<br>
> +<br>
> RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);<br>
> assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");<br>
> SplitInteger(TLI.makeLibCall(DAG, LC, VT, &Op, 1, false/*irrelevant*/,<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Fri Apr 17 13:36:25 2015<br>
> @@ -259,6 +259,10 @@ bool DAGTypeLegalizer::run() {<br>
> WidenVectorResult(N, i);<br>
> Changed = true;<br>
> goto NodeDone;<br>
> + case TargetLowering::TypePromoteFloat:<br>
> + PromoteFloatResult(N, i);<br>
> + Changed = true;<br>
> + goto NodeDone;<br>
> }<br>
> }<br>
><br>
> @@ -308,6 +312,10 @@ ScanOperands:<br>
> NeedsReanalyzing = WidenVectorOperand(N, i);<br>
> Changed = true;<br>
> break;<br>
> + case TargetLowering::TypePromoteFloat:<br>
> + NeedsReanalyzing = PromoteFloatOperand(N, i);<br>
> + Changed = true;<br>
> + break;<br>
> }<br>
> break;<br>
> }<br>
> @@ -753,6 +761,17 @@ void DAGTypeLegalizer::SetSoftenedFloat(<br>
> OpEntry = Result;<br>
> }<br>
><br>
> +void DAGTypeLegalizer::SetPromotedFloat(SDValue Op, SDValue Result) {<br>
> + assert(Result.getValueType() ==<br>
> + TLI.getTypeToTransformTo(*DAG.getContext(), Op.getValueType()) &&<br>
> + "Invalid type for promoted float");<br>
> + AnalyzeNewValue(Result);<br>
> +<br>
> + SDValue &OpEntry = PromotedFloats[Op];<br>
> + assert(!OpEntry.getNode() && "Node is already promoted!");<br>
> + OpEntry = Result;<br>
> +}<br>
> +<br>
> void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {<br>
> // Note that in some cases vector operation operands may be greater than<br>
> // the vector element type. For example BUILD_VECTOR of type <1 x i1> with<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)<br>
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Fri Apr 17 13:36:25 2015<br>
> @@ -93,6 +93,11 @@ private:<br>
> /// the same size, this map indicates the converted value to use.<br>
> SmallDenseMap<SDValue, SDValue, 8> SoftenedFloats;<br>
><br>
> + /// PromotedFloats - For floating point nodes that have a smaller precision<br>
> + /// than the smallest supported precision, this map indicates what promoted<br>
> + /// value to use.<br>
> + SmallDenseMap<SDValue, SDValue, 8> PromotedFloats;<br>
> +<br>
> /// ExpandedFloats - For float nodes that need to be expanded this map<br>
> /// indicates which operands are the expanded version of the input.<br>
> SmallDenseMap<SDValue, std::pair<SDValue, SDValue>, 8> ExpandedFloats;<br>
> @@ -499,6 +504,44 @@ private:<br>
> void FloatExpandSetCCOperands(SDValue &NewLHS, SDValue &NewRHS,<br>
> ISD::CondCode &CCCode, SDLoc dl);<br>
><br>
> +<br>
> + //===--------------------------------------------------------------------===//<br>
> + // Float promotion support: LegalizeFloatTypes.cpp<br>
> + //===--------------------------------------------------------------------===//<br>
> +<br>
> + SDValue GetPromotedFloat(SDValue Op) {<br>
> + SDValue &PromotedOp = PromotedFloats[Op];<br>
> + RemapValue(PromotedOp);<br>
> + assert(PromotedOp.getNode() && "Operand wasn't promoted?");<br>
> + return PromotedOp;<br>
> + }<br>
> + void SetPromotedFloat(SDValue Op, SDValue Result);<br>
> +<br>
> + void PromoteFloatResult(SDNode *N, unsigned ResNo);<br>
> + SDValue PromoteFloatRes_BITCAST(SDNode *N);<br>
> + SDValue PromoteFloatRes_BinOp(SDNode *N);<br>
> + SDValue PromoteFloatRes_ConstantFP(SDNode *N);<br>
> + SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);<br>
> + SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N);<br>
> + SDValue PromoteFloatRes_FMAD(SDNode *N);<br>
> + SDValue PromoteFloatRes_FPOWI(SDNode *N);<br>
> + SDValue PromoteFloatRes_FP_ROUND(SDNode *N);<br>
> + SDValue PromoteFloatRes_LOAD(SDNode *N);<br>
> + SDValue PromoteFloatRes_SELECT(SDNode *N);<br>
> + SDValue PromoteFloatRes_SELECT_CC(SDNode *N);<br>
> + SDValue PromoteFloatRes_UnaryOp(SDNode *N);<br>
> + SDValue PromoteFloatRes_UNDEF(SDNode *N);<br>
> + SDValue PromoteFloatRes_XINT_TO_FP(SDNode *N);<br>
> +<br>
> + bool PromoteFloatOperand(SDNode *N, unsigned ResNo);<br>
> + SDValue PromoteFloatOp_BITCAST(SDNode *N, unsigned OpNo);<br>
> + SDValue PromoteFloatOp_FCOPYSIGN(SDNode *N, unsigned OpNo);<br>
> + SDValue PromoteFloatOp_FP_EXTEND(SDNode *N, unsigned OpNo);<br>
> + SDValue PromoteFloatOp_FP_TO_XINT(SDNode *N, unsigned OpNo);<br>
> + SDValue PromoteFloatOp_STORE(SDNode *N, unsigned OpNo);<br>
> + SDValue PromoteFloatOp_SELECT_CC(SDNode *N, unsigned OpNo);<br>
> + SDValue PromoteFloatOp_SETCC(SDNode *N, unsigned OpNo);<br>
> +<br>
> //===--------------------------------------------------------------------===//<br>
> // Scalarization Support: LegalizeVectorTypes.cpp<br>
> //===--------------------------------------------------------------------===//<br>
><br>
> Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=235215&r1=235214&r2=235215&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=235215&r1=235214&r2=235215&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)<br>
> +++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Fri Apr 17 13:36:25 2015<br>
> @@ -1256,10 +1256,19 @@ void TargetLoweringBase::computeRegister<br>
> }<br>
><br>
> if (!isTypeLegal(MVT::f16)) {<br>
> - NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];<br>
> - RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];<br>
> - TransformToType[MVT::f16] = MVT::i16;<br>
> - ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);<br>
> + // If the target has native f32 support, promote f16 operations to f32. If<br>
> + // f32 is not supported, generate soft float library calls.<br>
> + if (isTypeLegal(MVT::f32)) {<br>
> + NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];<br>
> + RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];<br>
> + TransformToType[MVT::f16] = MVT::f32;<br>
> + ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);<br>
> + } else {<br>
> + NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];<br>
> + RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];<br>
> + TransformToType[MVT::f16] = MVT::i16;<br>
> + ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);<br>
> + }<br>
> }<br>
><br>
> // Loop over all of the vector value types to see which need transformations.<br>
><br>
> Added: llvm/trunk/test/CodeGen/ARM/fp16-promote.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-promote.ll?rev=235215&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp16-promote.ll?rev=235215&view=auto</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/ARM/fp16-promote.ll (added)<br>
> +++ llvm/trunk/test/CodeGen/ARM/fp16-promote.ll Fri Apr 17 13:36:25 2015<br>
> @@ -0,0 +1,1287 @@<br>
> +; RUN: llc -asm-verbose=false < %s -mattr=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 -check-prefix=CHECK-ALL<br>
> +; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=CHECK-LIBCALL -check-prefix=CHECK-ALL<br>
> +<br>
> +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32"<br>
> +target triple = "armv7-eabihf"<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fadd:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vadd.f32 s0, s2, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fadd:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vadd.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fadd(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fadd half %a, %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fsub:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vsub.f32 s0, s2, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fsub:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vsub.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fsub(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fsub half %a, %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fmul:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vmul.f32 s0, s2, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fmul<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vmul.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fmul(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fmul half %a, %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fdiv:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vdiv.f32 s0, s2, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fdiv<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vdiv.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fdiv(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fdiv half %a, %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_frem:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r1]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s2, r0<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s2<br>
> +; CHECK-FP16-NEXT: bl fmodf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_frem<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl fmodf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_frem(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = frem half %a, %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-ALL-LABEL: test_load_store:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: ldrh r0, [r0]<br>
> +; CHECK-ALL-NEXT: strh r0, [r1]<br>
> +; CHECK-ALL-NEXT: bx lr<br>
> +define void @test_load_store(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + store half %a, half* %q<br>
> + ret void<br>
> +}<br>
> +<br>
> +; Testing only successfull compilation of function calls. In ARM ABI, half<br>
> +; args and returns are handled as f32.<br>
> +<br>
> +declare half @test_callee(half %a, half %b) #0<br>
> +<br>
> +; CHECK-ALL-LABEL: test_call:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: push {r11, lr}<br>
> +; CHECK-ALL-NEXT: bl test_callee<br>
> +; CHECK-ALL-NEXT: pop {r11, pc}<br>
> +define half @test_call(half %a, half %b) #0 {<br>
> + %r = call half @test_callee(half %a, half %b)<br>
> + ret half %r<br>
> +}<br>
> +<br>
> +; CHECK-ALL-LABEL: test_call_flipped:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: push {r11, lr}<br>
> +; CHECK-ALL-NEXT: mov r2, r0<br>
> +; CHECK-ALL-NEXT: mov r0, r1<br>
> +; CHECK-ALL-NEXT: mov r1, r2<br>
> +; CHECK-ALL-NEXT: bl test_callee<br>
> +; CHECK-ALL-NEXT: pop {r11, pc}<br>
> +define half @test_call_flipped(half %a, half %b) #0 {<br>
> + %r = call half @test_callee(half %b, half %a)<br>
> + ret half %r<br>
> +}<br>
> +<br>
> +; CHECK-ALL-LABEL: test_tailcall_flipped:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: mov r2, r0<br>
> +; CHECK-ALL-NEXT: mov r0, r1<br>
> +; CHECK-ALL-NEXT: mov r1, r2<br>
> +; CHECK-ALL-NEXT: b test_callee<br>
> +define half @test_tailcall_flipped(half %a, half %b) #0 {<br>
> + %r = tail call half @test_callee(half %b, half %a)<br>
> + ret half %r<br>
> +}<br>
> +<br>
> +; Optimizer picks %p or %q based on %c and only loads that value<br>
> +; No conversion is needed<br>
> +; CHECK-BOTH-LABEL: test_select:<br>
> +; CHECK-BOTH-NEXT: .fnstart<br>
> +; CHECK-BOTH-NEXT: cmp r2, #0<br>
> +; CHECK-BOTH-NEXT: movne r1, r0<br>
> +; CHECK-BOTH-NEXT: ldrh r1, [r1]<br>
> +; CHECK-BOTH-NEXT: strh r1, [r0]<br>
> +; CHECK-BOTH-NEXT: bx lr<br>
> +define void @test_select(half* %p, half* %q, i1 zeroext %c) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = select i1 %c, half %a, half %b<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; Test only two variants of fcmp. These get translated to f32 vcmpe<br>
> +; instructions anyway.<br>
> +; CHECK-FP16-LABEL: test_fcmp_une:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: mov r0, #0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vcmpe.f32 s2, s0<br>
> +; CHECK-FP16-NEXT: vmrs APSR_nzcv, fpscr<br>
> +; CHECK-FP16-NEXT: movwne r0, #1<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fcmp_une:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vcmpe.f32<br>
> +; CHECK-LIBCALL: movwne<br>
> +define i1 @test_fcmp_une(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fcmp une half %a, %b<br>
> + ret i1 %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fcmp_ueq:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vmov s2, r2<br>
> +; CHECK-FP16-NEXT: mov r0, #0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vcmpe.f32 s2, s0<br>
> +; CHECK-FP16-NEXT: vmrs APSR_nzcv, fpscr<br>
> +; CHECK-FP16-NEXT: movweq r0, #1<br>
> +; CHECK-FP16-NEXT: movwvs r0, #1<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fcmp_ueq:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vcmpe.f32<br>
> +; CHECK-LIBCALL: movweq<br>
> +define i1 @test_fcmp_ueq(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = fcmp ueq half %a, %b<br>
> + ret i1 %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_br_cc:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r0<br>
> +; CHECK-FP16-NEXT: mov r0, #0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vcmpe.f32 s2, s0<br>
> +; CHECK-FP16-NEXT: vmrs APSR_nzcv, fpscr<br>
> +; CHECK-FP16-NEXT: strmi r0, [r3]<br>
> +; CHECK-FP16-NEXT: strpl r0, [r2]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_br_cc:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vcmpe.f32<br>
> +; CHECK-LIBCALL: strmi<br>
> +; CHECK-LIBCALL: strpl<br>
> +define void @test_br_cc(half* %p, half* %q, i32* %p1, i32* %p2) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %c = fcmp uge half %a, %b<br>
> + br i1 %c, label %then, label %else<br>
> +then:<br>
> + store i32 0, i32* %p1<br>
> + ret void<br>
> +else:<br>
> + store i32 0, i32* %p2<br>
> + ret void<br>
> +}<br>
> +<br>
> +declare i1 @test_dummy(half* %p) #0<br>
> +; CHECK-FP16-LABEL: test_phi:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: vpush {d8, d9}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s18, s0<br>
> +; CHECK-FP16-NEXT: [[LOOP:.LBB[1-9_]+]]:<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov.f32 s16, s18<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: mov r0, r4<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s18, s0<br>
> +; CHECK-FP16-NEXT: bl test_dummy<br>
> +; CHECK-FP16-NEXT: tst r0, #1<br>
> +; CHECK-FP16-NEXT: bne [[LOOP]]<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s16<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-LIBCALL-LABEL: test_phi:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: [[LOOP:.LBB[1-9_]+]]:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl test_dummy<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_phi(half* %p) #0 {<br>
> +entry:<br>
> + %a = load half, half* %p<br>
> + br label %loop<br>
> +loop:<br>
> + %r = phi half [%a, %entry], [%b, %loop]<br>
> + %b = load half, half* %p<br>
> + %c = call i1 @test_dummy(half* %p)<br>
> + br i1 %c, label %loop, label %return<br>
> +return:<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fptosi_i32:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvt.s32.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bx<br>
> +; CHECK-LIBCALL-LABEL: test_fptosi_i32:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vcvt.s32.f32<br>
> +define i32 @test_fptosi_i32(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = fptosi half %a to i32<br>
> + ret i32 %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fptosi_i64:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r11, lr}<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: __aeabi_f2lz<br>
> +; CHECK-FP16-NEXT: pop {r11, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_fptosi_i64:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __aeabi_f2lz<br>
> +define i64 @test_fptosi_i64(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = fptosi half %a to i64<br>
> + ret i64 %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fptoui_i32:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvt.u32.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bx<br>
> +; CHECK-LIBCALL-LABEL: test_fptoui_i32:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vcvt.u32.f32<br>
> +define i32 @test_fptoui_i32(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = fptoui half %a to i32<br>
> + ret i32 %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fptoui_i64:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r11, lr}<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: __aeabi_f2ulz<br>
> +; CHECK-FP16-NEXT: pop {r11, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_fptoui_i64:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __aeabi_f2ulz<br>
> +define i64 @test_fptoui_i64(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = fptoui half %a to i64<br>
> + ret i64 %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_sitofp_i32:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvt.f32.s32 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r1]<br>
> +; CHECK-FP16-NEXT: bx<br>
> +; CHECK-LIBCALL-LABEL: test_sitofp_i32:<br>
> +; CHECK-LIBCALL: vcvt.f32.s32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_sitofp_i32(i32 %a, half* %p) #0 {<br>
> + %r = sitofp i32 %a to half<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_uitofp_i32:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvt.f32.u32 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r1]<br>
> +; CHECK-FP16-NEXT: bx<br>
> +; CHECK-LIBCALL-LABEL: test_uitofp_i32:<br>
> +; CHECK-LIBCALL: vcvt.f32.u32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_uitofp_i32(i32 %a, half* %p) #0 {<br>
> + %r = uitofp i32 %a to half<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_sitofp_i64:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r2<br>
> +; CHECK-FP16-NEXT: bl __aeabi_l2f<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_sitofp_i64:<br>
> +; CHECK-LIBCALL: bl __aeabi_l2f<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_sitofp_i64(i64 %a, half* %p) #0 {<br>
> + %r = sitofp i64 %a to half<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_uitofp_i64:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r2<br>
> +; CHECK-FP16-NEXT: bl __aeabi_ul2f<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_uitofp_i64:<br>
> +; CHECK-LIBCALL: bl __aeabi_ul2f<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_uitofp_i64(i64 %a, half* %p) #0 {<br>
> + %r = uitofp i64 %a to half<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fptrunc_float:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r1]<br>
> +; CHECK-FP16-NEXT: bx<br>
> +; CHECK-LIBCALL-LABEL: test_fptrunc_float:<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fptrunc_float(float %f, half* %p) #0 {<br>
> + %a = fptrunc float %f to half<br>
> + store half %a, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fptrunc_double:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r2<br>
> +; CHECK-FP16-NEXT: bl __aeabi_d2h<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_fptrunc_double:<br>
> +; CHECK-LIBCALL: bl __aeabi_d2h<br>
> +define void @test_fptrunc_double(double %d, half* %p) #0 {<br>
> + %a = fptrunc double %d to half<br>
> + store half %a, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fpextend_float:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fpextend_float:<br>
> +; CHECK-LIBCALL: b __gnu_h2f_ieee<br>
> +define float @test_fpextend_float(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = fpext half %a to float<br>
> + ret float %r<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fpextend_double:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvt.f64.f32 d16, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, r1, d16<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fpextend_double:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vcvt.f64.f32<br>
> +define double @test_fpextend_double(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = fpext half %a to double<br>
> + ret double %r<br>
> +}<br>
> +<br>
> +; CHECK-BOTH-LABEL: test_bitcast_halftoi16:<br>
> +; CHECK-BOTH-NEXT: .fnstart<br>
> +; CHECK-BOTH-NEXT: ldrh r0, [r0]<br>
> +; CHECK-BOTH-NEXT: bx lr<br>
> +define i16 @test_bitcast_halftoi16(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = bitcast half %a to i16<br>
> + ret i16 %r<br>
> +}<br>
> +<br>
> +; CHECK-BOTH-LABEL: test_bitcast_i16tohalf:<br>
> +; CHECK-BOTH-NEXT: .fnstart<br>
> +; CHECK-BOTH-NEXT: strh r0, [r1]<br>
> +; CHECK-BOTH-NEXT: bx lr<br>
> +define void @test_bitcast_i16tohalf(i16 %a, half* %p) #0 {<br>
> + %r = bitcast i16 %a to half<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +declare half @llvm.sqrt.f16(half %a) #0<br>
> +declare half @llvm.powi.f16(half %a, i32 %b) #0<br>
> +declare half @llvm.sin.f16(half %a) #0<br>
> +declare half @llvm.cos.f16(half %a) #0<br>
> +declare half @llvm.pow.f16(half %a, half %b) #0<br>
> +declare half @llvm.exp.f16(half %a) #0<br>
> +declare half @llvm.exp2.f16(half %a) #0<br>
> +declare half @llvm.log.f16(half %a) #0<br>
> +declare half @llvm.log10.f16(half %a) #0<br>
> +declare half @llvm.log2.f16(half %a) #0<br>
> +declare half @llvm.fma.f16(half %a, half %b, half %c) #0<br>
> +declare half @llvm.fabs.f16(half %a) #0<br>
> +declare half @llvm.minnum.f16(half %a, half %b) #0<br>
> +declare half @llvm.maxnum.f16(half %a, half %b) #0<br>
> +declare half @llvm.copysign.f16(half %a, half %b) #0<br>
> +declare half @llvm.floor.f16(half %a) #0<br>
> +declare half @llvm.ceil.f16(half %a) #0<br>
> +declare half @llvm.trunc.f16(half %a) #0<br>
> +declare half @llvm.rint.f16(half %a) #0<br>
> +declare half @llvm.nearbyint.f16(half %a) #0<br>
> +declare half @llvm.round.f16(half %a) #0<br>
> +declare half @llvm.fmuladd.f16(half %a, half %b, half %c) #0<br>
> +<br>
> +; CHECK-FP16-LABEL: test_sqrt:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vsqrt.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_sqrt:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vsqrt.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_sqrt(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.sqrt.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fpowi:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl __powisf2<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_fpowi:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __powisf2<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fpowi(half* %p, i32 %b) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.powi.f16(half %a, i32 %b)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_sin:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl sinf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_sin:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl sinf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_sin(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.sin.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_cos:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl cosf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_cos:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl cosf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_cos(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.cos.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_pow:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r1]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s2, r0<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s2<br>
> +; CHECK-FP16-NEXT: bl powf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_pow:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl powf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_pow(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = call half @llvm.pow.f16(half %a, half %b)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_exp:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl expf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_exp:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl expf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_exp(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.exp.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_exp2:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl exp2f<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_exp2:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl exp2f<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_exp2(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.exp2.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_log:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl logf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_log:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl logf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_log(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.log.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_log10:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl log10f<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_log10:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl log10f<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_log10(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.log10.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_log2:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl log2f<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_log2:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl log2f<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_log2(half* %p) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.log2.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fma:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r2]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s2, r1<br>
> +; CHECK-FP16-NEXT: vmov s4, r0<br>
> +; CHECK-FP16-NEXT: vmov s0, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s4, s4<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s2<br>
> +; CHECK-FP16-NEXT: vmov r2, s4<br>
> +; CHECK-FP16-NEXT: bl fmaf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_fma:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl fmaf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fma(half* %p, half* %q, half* %r) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %c = load half, half* %r, align 2<br>
> + %v = call half @llvm.fma.f16(half %a, half %b, half %c)<br>
> + store half %v, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fabs:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r0]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vabs.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fabs:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bfc<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fabs(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.fabs.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_minnum:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r1]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s2, r0<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s2<br>
> +; CHECK-FP16-NEXT: bl fminf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_minnum:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl fminf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_minnum(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = call half @llvm.minnum.f16(half %a, half %b)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_maxnum:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r1]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s2, r0<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s2<br>
> +; CHECK-FP16-NEXT: bl fmaxf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_maxnum:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl fmaxf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_maxnum(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = call half @llvm.maxnum.f16(half %a, half %b)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_copysign:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r0]<br>
> +; CHECK-FP16-NEXT: vmov.i32 d2, #0x80000000<br>
> +; CHECK-FP16-NEXT: vmov s0, r2<br>
> +; CHECK-FP16-NEXT: vmov s2, r1<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vbsl d2, d1, d0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s4<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_copysign:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vbsl<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_copysign(half* %p, half* %q) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %r = call half @llvm.copysign.f16(half %a, half %b)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_floor:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl floorf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_floor:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl floorf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_floor(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.floor.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_ceil:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl ceilf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_ceil:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl ceilf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_ceil(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.ceil.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_trunc:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl truncf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_trunc:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl truncf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_trunc(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.trunc.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_rint:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl rintf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_rint:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl rintf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_rint(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.rint.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_nearbyint:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl nearbyintf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_nearbyint:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl nearbyintf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_nearbyint(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.nearbyint.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_round:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: push {r4, lr}<br>
> +; CHECK-FP16-NEXT: mov r4, r0<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: bl roundf<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r0, s0<br>
> +; CHECK-FP16-NEXT: strh r0, [r4]<br>
> +; CHECK-FP16-NEXT: pop {r4, pc}<br>
> +; CHECK-LIBCALL-LABEL: test_round:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl roundf<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_round(half* %p) {<br>
> + %a = load half, half* %p, align 2<br>
> + %r = call half @llvm.round.f16(half %a)<br>
> + store half %r, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_fmuladd:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldrh r2, [r2]<br>
> +; CHECK-FP16-NEXT: ldrh r3, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r1, [r1]<br>
> +; CHECK-FP16-NEXT: vmov s0, r1<br>
> +; CHECK-FP16-NEXT: vmov s2, r3<br>
> +; CHECK-FP16-NEXT: vmov s4, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s2, s2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s4, s4<br>
> +; CHECK-FP16-NEXT: vmla.f32 s4, s2, s0<br>
> +; CHECK-FP16-NEXT: vcvtb.f16.f32 s0, s4<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: strh r1, [r0]<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_fmuladd:<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL: vmla.f32<br>
> +; CHECK-LIBCALL: bl __gnu_f2h_ieee<br>
> +define void @test_fmuladd(half* %p, half* %q, half* %r) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load half, half* %q, align 2<br>
> + %c = load half, half* %r, align 2<br>
> + %v = call half @llvm.fmuladd.f16(half %a, half %b, half %c)<br>
> + store half %v, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; f16 vectors are not legal in the backend. Vector elements are not assigned<br>
> +; to the register, but are stored in the stack instead. Hence insertelement<br>
> +; and extractelement have these extra loads and stores.<br>
> +<br>
> +; CHECK-ALL-LABEL: test_insertelement:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: sub sp, sp, #8<br>
> +; CHECK-ALL-NEXT: ldrh r3, [r1, #6]<br>
> +; CHECK-ALL-NEXT: strh r3, [sp, #6]<br>
> +; CHECK-ALL-NEXT: ldrh r3, [r1, #4]<br>
> +; CHECK-ALL-NEXT: strh r3, [sp, #4]<br>
> +; CHECK-ALL-NEXT: ldrh r3, [r1, #2]<br>
> +; CHECK-ALL-NEXT: strh r3, [sp, #2]<br>
> +; CHECK-ALL-NEXT: ldrh r3, [r1]<br>
> +; CHECK-ALL-NEXT: strh r3, [sp]<br>
> +; CHECK-ALL-NEXT: mov r3, sp<br>
> +; CHECK-ALL-NEXT: ldrh r0, [r0]<br>
> +; CHECK-ALL-NEXT: add r2, r3, r2, lsl #1<br>
> +; CHECK-ALL-NEXT: strh r0, [r2]<br>
> +; CHECK-ALL-NEXT: ldrh r0, [sp, #6]<br>
> +; CHECK-ALL-NEXT: strh r0, [r1, #6]<br>
> +; CHECK-ALL-NEXT: ldrh r0, [sp, #4]<br>
> +; CHECK-ALL-NEXT: strh r0, [r1, #4]<br>
> +; CHECK-ALL-NEXT: ldrh r0, [sp, #2]<br>
> +; CHECK-ALL-NEXT: strh r0, [r1, #2]<br>
> +; CHECK-ALL-NEXT: ldrh r0, [sp]<br>
> +; CHECK-ALL-NEXT: strh r0, [r1]<br>
> +; CHECK-ALL-NEXT: add sp, sp, #8<br>
> +; CHECK-ALL-NEXT: bx lr<br>
> +define void @test_insertelement(half* %p, <4 x half>* %q, i32 %i) #0 {<br>
> + %a = load half, half* %p, align 2<br>
> + %b = load <4 x half>, <4 x half>* %q, align 8<br>
> + %c = insertelement <4 x half> %b, half %a, i32 %i<br>
> + store <4 x half> %c, <4 x half>* %q<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-ALL-LABEL: test_extractelement:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: sub sp, sp, #8<br>
> +; CHECK-ALL-NEXT: ldrh r12, [r1, #2]<br>
> +; CHECK-ALL-NEXT: ldrh r3, [r1]<br>
> +; CHECK-ALL-NEXT: orr r3, r3, r12, lsl #16<br>
> +; CHECK-ALL-NEXT: str r3, [sp]<br>
> +; CHECK-ALL-NEXT: ldrh r3, [r1, #6]<br>
> +; CHECK-ALL-NEXT: ldrh r1, [r1, #4]<br>
> +; CHECK-ALL-NEXT: orr r1, r1, r3, lsl #16<br>
> +; CHECK-ALL-NEXT: str r1, [sp, #4]<br>
> +; CHECK-ALL-NEXT: mov r1, sp<br>
> +; CHECK-ALL-NEXT: add r1, r1, r2, lsl #1<br>
> +; CHECK-ALL-NEXT: ldrh r1, [r1]<br>
> +; CHECK-ALL-NEXT: strh r1, [r0]<br>
> +; CHECK-ALL-NEXT: add sp, sp, #8<br>
> +; CHECK-ALL-NEXT: bx lr<br>
> +define void @test_extractelement(half* %p, <4 x half>* %q, i32 %i) #0 {<br>
> + %a = load <4 x half>, <4 x half>* %q, align 8<br>
> + %b = extractelement <4 x half> %a, i32 %i<br>
> + store half %b, half* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; test struct operations<br>
> +<br>
> +%struct.dummy = type { i32, half }<br>
> +<br>
> +; CHECK-ALL-LABEL: test_insertvalue:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: ldr r2, [r0]<br>
> +; CHECK-ALL-NEXT: ldrh r1, [r1]<br>
> +; CHECK-ALL-NEXT: strh r1, [r0, #4]<br>
> +; CHECK-ALL-NEXT: str r2, [r0]<br>
> +; CHECK-ALL-NEXT: bx lr<br>
> +define void @test_insertvalue(%struct.dummy* %p, half* %q) {<br>
> + %a = load %struct.dummy, %struct.dummy* %p<br>
> + %b = load half, half* %q<br>
> + %c = insertvalue %struct.dummy %a, half %b, 1<br>
> + store %struct.dummy %c, %struct.dummy* %p<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-ALL-LABEL: test_extractvalue:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: ldrh r0, [r0, #4]<br>
> +; CHECK-ALL-NEXT: strh r0, [r1]<br>
> +; CHECK-ALL-NEXT: bx lr<br>
> +define void @test_extractvalue(%struct.dummy* %p, half* %q) {<br>
> + %a = load %struct.dummy, %struct.dummy* %p<br>
> + %b = extractvalue %struct.dummy %a, 1<br>
> + store half %b, half* %q<br>
> + ret void<br>
> +}<br>
> +<br>
> +; CHECK-FP16-LABEL: test_struct_return:<br>
> +; CHECK-FP16-NEXT: .fnstart<br>
> +; CHECK-FP16-NEXT: ldr r2, [r0]<br>
> +; CHECK-FP16-NEXT: ldrh r0, [r0, #4]<br>
> +; CHECK-FP16-NEXT: vmov s0, r0<br>
> +; CHECK-FP16-NEXT: mov r0, r2<br>
> +; CHECK-FP16-NEXT: vcvtb.f32.f16 s0, s0<br>
> +; CHECK-FP16-NEXT: vmov r1, s0<br>
> +; CHECK-FP16-NEXT: bx lr<br>
> +; CHECK-LIBCALL-LABEL: test_struct_return:<br>
> +; CHECK-LIBCALL-NEXT: .fnstart<br>
> +; CHECK-LIBCALL-NEXT: push {r4, lr}<br>
> +; CHECK-LIBCALL-NEXT: ldr r4, [r0]<br>
> +; CHECK-LIBCALL-NEXT: ldrh r0, [r0, #4]<br>
> +; CHECK-LIBCALL-NEXT: bl __gnu_h2f_ieee<br>
> +; CHECK-LIBCALL-NEXT: mov r1, r0<br>
> +; CHECK-LIBCALL-NEXT: mov r0, r4<br>
> +; CHECK-LIBCALL-NEXT: pop {r4, pc}<br>
> +define %struct.dummy @test_struct_return(%struct.dummy* %p) {<br>
> + %a = load %struct.dummy, %struct.dummy* %p<br>
> + ret %struct.dummy %a<br>
> +}<br>
> +<br>
> +; CHECK-ALL-LABEL: test_struct_arg:<br>
> +; CHECK-ALL-NEXT: .fnstart<br>
> +; CHECK-ALL-NEXT: mov r0, r1<br>
> +; CHECK-ALL-NEXT: bx lr<br>
> +define half @test_struct_arg(%struct.dummy %p) {<br>
> + %a = extractvalue %struct.dummy %p, 1<br>
> + ret half %a<br>
> +}<br>
> +<br>
> +attributes #0 = { nounwind }<br>
><br>
><br>
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<br>
</blockquote></div>
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