<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Sure!<div class=""><div style="margin: 0px; font-size: 11px; font-family: Menlo;" class="">Committed revision 233936.</div><div style="margin: 0px; font-size: 11px; font-family: Menlo;" class=""><br class=""></div><div style=""><blockquote type="cite" class=""><div class="">On Apr 2, 2015, at 11:18 AM, Eric Christopher <<a href="mailto:echristo@gmail.com" class="">echristo@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Put a comment up there by the AddedComplexity?<br class=""><br class="">-eric<br class=""></div><br class=""><div class="gmail_quote">On Mon, Mar 30, 2015 at 5:39 PM Quentin Colombet <<a href="mailto:qcolombet@apple.com" class="">qcolombet@apple.com</a>> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: qcolombet<br class="">
Date: Mon Mar 30 19:31:13 2015<br class="">
New Revision: 233653<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=233653&view=rev" target="_blank" class="">http://llvm.org/viewvc/llvm-<u class=""></u>project?rev=233653&view=rev</a><br class="">
Log:<br class="">
[AArch64] Fix poor codegen for add immediate.<br class="">
We used to match the register variant before the immediate when the register<br class="">
argument could be implicitly zero-extended.<br class="">
<br class="">
Modified:<br class="">
llvm/trunk/lib/Target/AArch64/<u class=""></u>AArch64InstrFormats.td<br class="">
llvm/trunk/test/CodeGen/<u class=""></u>AArch64/addsub.ll<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/<u class=""></u>AArch64InstrFormats.td<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=233653&r1=233652&r2=233653&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-<u class=""></u>project/llvm/trunk/lib/Target/<u class=""></u>AArch64/AArch64InstrFormats.<u class=""></u>td?rev=233653&r1=233652&r2=<u class=""></u>233653&view=diff</a><br class="">
==============================<u class=""></u>==============================<u class=""></u>==================<br class="">
--- llvm/trunk/lib/Target/AArch64/<u class=""></u>AArch64InstrFormats.td (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/<u class=""></u>AArch64InstrFormats.td Mon Mar 30 19:31:13 2015<br class="">
@@ -1637,10 +1637,12 @@ multiclass AddSub<bit isSub, string mnem<br class="">
SDPatternOperator OpNode = null_frag> {<br class="">
let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {<br class="">
// Add/Subtract immediate<br class="">
+ let AddedComplexity = 6 in<br class="">
def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,<br class="">
mnemonic, OpNode> {<br class="">
let Inst{31} = 0;<br class="">
}<br class="">
+ let AddedComplexity = 6 in<br class="">
def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,<br class="">
mnemonic, OpNode> {<br class="">
let Inst{31} = 1;<br class="">
<br class="">
Modified: llvm/trunk/test/CodeGen/<u class=""></u>AArch64/addsub.ll<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/addsub.ll?rev=233653&r1=233652&r2=233653&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-<u class=""></u>project/llvm/trunk/test/<u class=""></u>CodeGen/AArch64/addsub.ll?rev=<u class=""></u>233653&r1=233652&r2=233653&<u class=""></u>view=diff</a><br class="">
==============================<u class=""></u>==============================<u class=""></u>==================<br class="">
--- llvm/trunk/test/CodeGen/<u class=""></u>AArch64/addsub.ll (original)<br class="">
+++ llvm/trunk/test/CodeGen/<u class=""></u>AArch64/addsub.ll Mon Mar 30 19:31:13 2015<br class="">
@@ -24,6 +24,34 @@ define void @add_small() {<br class="">
ret void<br class="">
}<br class="">
<br class="">
+; Make sure we grab the imm variant when the register operand<br class="">
+; can be implicitly zero-extend.<br class="">
+; We used to generate something horrible like this:<br class="">
+; wA = ldrb<br class="">
+; xB = ldimm 12<br class="">
+; xC = add xB, wA, uxtb<br class="">
+; whereas this can be achieved with:<br class="">
+; wA = ldrb<br class="">
+; xC = add xA, #12 ; <- xA implicitly zero extend wA.<br class="">
+define void @add_small_imm(i8* %p, i64* %q, i32 %b, i32* %addr) {<br class="">
+; CHECK-LABEL: add_small_imm:<br class="">
+entry:<br class="">
+<br class="">
+; CHECK: ldrb w[[LOAD32:[0-9]+]], [x0]<br class="">
+ %t = load i8, i8* %p<br class="">
+ %promoted = zext i8 %t to i64<br class="">
+ %zextt = zext i8 %t to i32<br class="">
+ %add = add nuw i32 %zextt, %b<br class="">
+<br class="">
+; CHECK: add [[ADD2:x[0-9]+]], x[[LOAD32]], #12<br class="">
+ %add2 = add nuw i64 %promoted, 12<br class="">
+ store i32 %add, i32* %addr<br class="">
+<br class="">
+; CHECK: str [[ADD2]], [x1]<br class="">
+ store i64 %add2, i64* %q<br class="">
+ ret void<br class="">
+}<br class="">
+<br class="">
; Add 12-bit immediates, shifted left by 12 bits<br class="">
define void @add_med() {<br class="">
; CHECK-LABEL: add_med:<br class="">
<br class="">
<br class="">
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</blockquote></div>
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