<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><div class="">Because currently it does happen. The patch that fixes it (<a href="http://reviews.llvm.org/D6946" class="">http://reviews.llvm.org/D6946</a>) is complicated and not accepted yet...</div><div class=""><br class=""></div><div class="">- Matthias</div><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 26, 2015, at 2:18 PM, Sean Silva <<a href="mailto:chisophugis@gmail.com" class="">chisophugis@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">If it should not happen, why not just assert?<div class=""><br class=""></div><div class="">-- Sean Silva</div></div><div class="gmail_extra"><br class=""><div class="gmail_quote">On Wed, Feb 25, 2015 at 10:03 AM, Matthias Braun <span dir="ltr" class=""><<a href="mailto:matze@braunis.de" target="_blank" class="">matze@braunis.de</a>></span> wrote:<br class=""><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br class="">
Date: Wed Feb 25 12:03:50 2015<br class="">
New Revision: 230517<br class="">
<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=230517&view=rev" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=230517&view=rev</a><br class="">
Log:<br class="">
AArch64: Add debug message for large shift constants.<br class="">
<br class="">
As requested in code review.<br class="">
<br class="">
Modified:<br class="">
llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp<br class="">
<br class="">
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp<br class="">
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=230517&r1=230516&r2=230517&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp?rev=230517&r1=230516&r2=230517&view=diff</a><br class="">
==============================================================================<br class="">
--- llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp (original)<br class="">
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp Wed Feb 25 12:03:50 2015<br class="">
@@ -1399,8 +1399,11 @@ static bool isBitfieldExtractOpFromAnd(S<br class="">
<br class="">
// Bail out on large immediates. This happens when no proper<br class="">
// combining/constant folding was performed.<br class="">
- if (!BiggerPattern && (Srl_imm <= 0 || Srl_imm >= VT.getSizeInBits()))<br class="">
+ if (!BiggerPattern && (Srl_imm <= 0 || Srl_imm >= VT.getSizeInBits())) {<br class="">
+ DEBUG((dbgs() << N<br class="">
+ << ": Found large shift immediate, this should not happen\n"));<br class="">
return false;<br class="">
+ }<br class="">
<br class="">
LSB = Srl_imm;<br class="">
MSB = Srl_imm + (VT == MVT::i32 ? countTrailingOnes<uint32_t>(And_imm)<br class="">
@@ -1506,8 +1509,11 @@ static bool isBitfieldExtractOpFromShr(S<br class="">
<br class="">
// Missing combines/constant folding may have left us with strange<br class="">
// constants.<br class="">
- if (Shl_imm >= VT.getSizeInBits())<br class="">
+ if (Shl_imm >= VT.getSizeInBits()) {<br class="">
+ DEBUG((dbgs() << N<br class="">
+ << ": Found large shift immediate, this should not happen\n"));<br class="">
return false;<br class="">
+ }<br class="">
<br class="">
uint64_t Srl_imm = 0;<br class="">
if (!isIntImmediate(N->getOperand(1), Srl_imm))<br class="">
<br class="">
<br class="">
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</blockquote></div><br class=""></div>
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