<div dir="ltr">Hi Elena,<br><br><div>This patch and many others in the file don't have Predicates that stop the instructions from being generated.</div><div><div><br></div></div><div>Example from your testcase:</div><div><div>dzur:~/tmp> ~/builds/build-llvm/Debug+Asserts/bin/llc avx512-round.ll  -mcpu=corei7-avx -filetype=asm -o - | grep vrndscaless</div></div><div><br></div><div>I'm in the process of trying to fix it with testcase, but here's a patch that fixes (at least some of it) for this set of instructions.</div><div><br></div><div>I've gone ahead and reverted the patch in r229942 , could you please audit the file to make sure all of the patterns have predicates?</div><div><br></div><div>Thanks!</div><div><br></div><div>-eric </div><div><br></div><br><div class="gmail_quote">On Thu Feb 19 2015 at 2:52:24 AM Elena Demikhovsky <<a href="mailto:elena.demikhovsky@intel.com">elena.demikhovsky@intel.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: delena<br>
Date: Thu Feb 19 04:48:04 2015<br>
New Revision: 229837<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=229837&view=rev" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project?rev=229837&view=rev</a><br>
Log:<br>
AVX-512: Full implementation for VRNDSCALESS/SD instructions and intrinsics.<br>
<br>
<br>
Modified:<br>
    llvm/trunk/include/llvm/IR/<u></u>IntrinsicsX86.td<br>
    llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.cpp<br>
    llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.h<br>
    llvm/trunk/lib/Target/X86/<u></u>X86InstrAVX512.td<br>
    llvm/trunk/lib/Target/X86/<u></u>X86InstrFragmentsSIMD.td<br>
    llvm/trunk/lib/Target/X86/<u></u>X86IntrinsicsInfo.h<br>
    llvm/trunk/test/CodeGen/X86/<u></u>avx512-intrinsics.ll<br>
    llvm/trunk/test/CodeGen/X86/<u></u>avx512-round.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/<u></u>IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/include/<u></u>llvm/IR/IntrinsicsX86.td?rev=<u></u>229837&r1=229836&r2=229837&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/include/llvm/IR/<u></u>IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/<u></u>IntrinsicsX86.td Thu Feb 19 04:48:04 2015<br>
@@ -3193,12 +3193,14 @@ let TargetPrefix = "x86" in {  // All in<br>
           Intrinsic<[llvm_v8f64_ty], [llvm_v8f64_ty, llvm_v8f64_ty,<br>
                      llvm_v8f64_ty, llvm_i8_ty, llvm_i32_ty], [IntrNoMem]>;<br>
<br>
-  def int_x86_avx512_rndscale_ss        : GCCBuiltin<"__builtin_ia32_<u></u>rndscaless">,<br>
-              Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty,<br>
-                         llvm_i32_ty], [IntrNoMem]>;<br>
-  def int_x86_avx512_rndscale_sd        : GCCBuiltin<"__builtin_ia32_<u></u>rndscalesd">,<br>
-              Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty,<br>
-                         llvm_i32_ty], [IntrNoMem]>;<br>
+  def int_x86_avx512_mask_rndscale_<u></u>ss : GCCBuiltin<"__builtin_ia32_<u></u>rndscaless_mask">,<br>
+          Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty,<br>
+                                     llvm_i8_ty, llvm_i32_ty, llvm_i32_ty],<br>
+                                     [IntrNoMem]>;<br>
+  def int_x86_avx512_mask_rndscale_<u></u>sd : GCCBuiltin<"__builtin_ia32_<u></u>rndscalesd_mask">,<br>
+          Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_v2f64_ty, llvm_v2f64_ty,<br>
+                                      llvm_i8_ty, llvm_i32_ty, llvm_i32_ty],<br>
+                                     [IntrNoMem]>;<br>
   def int_x86_avx512_sqrt_ss        : GCCBuiltin<"__builtin_ia32_<u></u>sqrtrndss">,<br>
               Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty],<br>
                         [IntrNoMem]>;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>X86/X86ISelLowering.cpp?rev=<u></u>229837&r1=229836&r2=229837&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.cpp Thu Feb 19 04:48:04 2015<br>
@@ -17523,9 +17523,20 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
       SDValue Src2 = Op.getOperand(2);<br>
       SDValue Src0 = Op.getOperand(3);<br>
       SDValue Mask = Op.getOperand(4);<br>
-      SDValue RoundingMode = Op.getOperand(5);<br>
+      // There are 2 kinds of intrinsics in this group:<br>
+      // (1) With supress-all-exceptions (sae) - 6 operands<br>
+      // (2) With rounding mode and sae - 7 operands.<br>
+      if (Op.getNumOperands() == 6) {<br>
+        SDValue Sae  = Op.getOperand(5);<br>
+        return getScalarMaskingNode(DAG.<u></u>getNode(IntrData->Opc0, dl, VT, Src1, Src2,<br>
+                                                Sae),<br>
+                                    Mask, Src0, Subtarget, DAG);<br>
+      }<br>
+      assert(Op.getNumOperands() == 7 && "Unexpected intrinsic form");<br>
+      SDValue RoundingMode  = Op.getOperand(5);<br>
+      SDValue Sae  = Op.getOperand(6);<br>
       return getScalarMaskingNode(DAG.<u></u>getNode(IntrData->Opc0, dl, VT, Src1, Src2,<br>
-                                              RoundingMode),<br>
+                                              RoundingMode, Sae),<br>
                                   Mask, Src0, Subtarget, DAG);<br>
     }<br>
     case INTR_TYPE_2OP_MASK: {<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>X86/X86ISelLowering.h?rev=<u></u>229837&r1=229836&r2=229837&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.h (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86ISelLowering.h Thu Feb 19 04:48:04 2015<br>
@@ -393,7 +393,8 @@ namespace llvm {<br>
       FMSUB_RND,<br>
       FNMSUB_RND,<br>
       FMADDSUB_RND,<br>
-      FMSUBADD_RND,<br>
+      FMSUBADD_RND,<br>
+      RNDSCALE,<br>
<br>
       // Compress and expand<br>
       COMPRESS,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86InstrAVX512.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>X86/X86InstrAVX512.td?rev=<u></u>229837&r1=229836&r2=229837&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86InstrAVX512.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86InstrAVX512.td Thu Feb 19 04:48:04 2015<br>
@@ -86,6 +86,8 @@ class X86VectorVTInfo<int numelts, Value<br>
                      !if (!eq (EltTypeName, "f64"), SSEPackedDouble,<br>
                      SSEPackedInt));<br>
<br>
+  RegisterClass FRC = !if (!eq (EltTypeName, "f32"), FR32X, FR64X);<br>
+<br>
   // A vector type of the same width with element type i32.  This is used to<br>
   // create the canonical constant zero node ImmAllZerosV.<br>
   ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");<br>
@@ -4637,7 +4639,6 @@ let ExeDomain = d in {<br>
 } // ExeDomain<br>
 }<br>
<br>
-<br>
 defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,<br>
                                 loadv16f32, SSEPackedSingle>, EVEX_V512,<br>
                                 EVEX_CD8<32, CD8VF>;<br>
@@ -4657,52 +4658,69 @@ def : Pat<(v8f64 (int_x86_avx512_mask_rn<br>
                   FROUND_CURRENT)),<br>
                    (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;<br>
<br>
-multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,<br>
-                     Operand x86memop, RegisterClass RC, Domain d> {<br>
-let ExeDomain = d in {<br>
-  def r : AVX512AIi8<opc, MRMSrcReg,<br>
-                    (outs RC:$dst), (ins RC:$src1, RC:$src2, i32u8imm:$src3),<br>
-                    !strconcat(OpcodeStr,<br>
-                    "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
-                    []>, EVEX_4V;<br>
-<br>
-  def m : AVX512AIi8<opc, MRMSrcMem,<br>
-                    (outs RC:$dst), (ins RC:$src1, x86memop:$src2,  i32u8imm:$src3),<br>
-                    !strconcat(OpcodeStr,<br>
-                    "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
-                    []>, EVEX_4V;<br>
-} // ExeDomain<br>
-}<br>
+multiclass<br>
+avx512_rndscale_scalar<bits<<u></u>8> opc, string OpcodeStr, X86VectorVTInfo _> {<br>
<br>
-defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,<br>
-                                SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;<br>
+  let ExeDomain = _.ExeDomain in {<br>
+  defm r : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),<br>
+                           (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,<br>
+                           "$src3, $src2, $src1", "$src1, $src2, $src3",<br>
+                           (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),<br>
+                            (i32 imm:$src3), (i32 FROUND_CURRENT)))>;<br>
<br>
-defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,<br>
-                                SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;<br>
+  defm rb : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),<br>
+                         (ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,<br>
+                         "$src3, $src2, $src1", "$src1, $src2, $src3",<br>
+                         (_.VT (X86RndScale (_.VT _.RC:$src1), (_.VT _.RC:$src2),<br>
+                         (i32 imm:$src3), (i32 FROUND_NO_EXC))), "{sae}">, EVEX_B;<br>
<br>
-let Predicates = [HasAVX512] in {<br>
-  def : Pat<(ffloor FR32X:$src),<br>
-            (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;<br>
-  def : Pat<(f64 (ffloor FR64X:$src)),<br>
-            (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;<br>
-  def : Pat<(f32 (fnearbyint FR32X:$src)),<br>
-            (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;<br>
-  def : Pat<(f64 (fnearbyint FR64X:$src)),<br>
-            (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;<br>
-  def : Pat<(f32 (fceil FR32X:$src)),<br>
-            (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;<br>
-  def : Pat<(f64 (fceil FR64X:$src)),<br>
-            (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;<br>
-  def : Pat<(f32 (frint FR32X:$src)),<br>
-            (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;<br>
-  def : Pat<(f64 (frint FR64X:$src)),<br>
-            (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;<br>
-  def : Pat<(f32 (ftrunc FR32X:$src)),<br>
-            (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;<br>
-  def : Pat<(f64 (ftrunc FR64X:$src)),<br>
-            (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;<br>
+  let mayLoad = 1 in<br>
+  defm m : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),<br>
+                         (ins _.RC:$src1, _.MemOp:$src2, i32u8imm:$src3), OpcodeStr,<br>
+                         "$src3, $src2, $src1", "$src1, $src2, $src3",<br>
+                         (_.VT (X86RndScale (_.VT _.RC:$src1),<br>
+                          (_.VT (scalar_to_vector (_.ScalarLdFrag addr:$src2))),<br>
+                          (i32 imm:$src3), (i32 FROUND_CURRENT)))>;<br>
+  }<br>
+  def : Pat<(ffloor _.FRC:$src), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),<br>
+             (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x1))), _.FRC)>;<br>
+  def : Pat<(fceil _.FRC:$src), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),<br>
+             (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x2))), _.FRC)>;<br>
+  def : Pat<(ftrunc _.FRC:$src), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),<br>
+             (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x3))), _.FRC)>;<br>
+  def : Pat<(frint _.FRC:$src), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),<br>
+             (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0x4))), _.FRC)>;<br>
+  def : Pat<(fnearbyint _.FRC:$src), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##r) (_.VT (IMPLICIT_DEF)),<br>
+             (_.VT (COPY_TO_REGCLASS _.FRC:$src, _.RC)), (i32 0xc))), _.FRC)>;<br>
+<br>
+  def : Pat<(ffloor (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),<br>
+             addr:$src, (i32 0x1))), _.FRC)>;<br>
+  def : Pat<(fceil (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),<br>
+             addr:$src, (i32 0x2))), _.FRC)>;<br>
+  def : Pat<(ftrunc (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),<br>
+             addr:$src, (i32 0x3))), _.FRC)>;<br>
+  def : Pat<(frint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),<br>
+             addr:$src, (i32 0x4))), _.FRC)>;<br>
+  def : Pat<(fnearbyint (_.ScalarLdFrag addr:$src)), (COPY_TO_REGCLASS<br>
+             (_.VT (!cast<Instruction>(NAME##m) (_.VT (IMPLICIT_DEF)),<br>
+             addr:$src, (i32 0xc))), _.FRC)>;<br>
 }<br>
<br>
+defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", f32x_info>,<br>
+                                AVX512AIi8Base, EVEX_4V, EVEX_CD8<32, CD8VT1>;<br>
+<br>
+defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", f64x_info>, VEX_W,<br>
+                                AVX512AIi8Base, EVEX_4V, EVEX_CD8<64, CD8VT1>;<br>
+<br>
 def : Pat<(v16f32 (ffloor VR512:$src)),<br>
           (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;<br>
 def : Pat<(v16f32 (fnearbyint VR512:$src)),<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86InstrFragmentsSIMD.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>X86/X86InstrFragmentsSIMD.td?<u></u>rev=229837&r1=229836&r2=<u></u>229837&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86InstrFragmentsSIMD.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86InstrFragmentsSIMD.td Thu Feb 19 04:48:04 2015<br>
@@ -223,6 +223,8 @@ def STDFp1SrcRm : SDTypeProfile<1, 2, [S<br>
                            SDTCisVec<0>, SDTCisInt<2>]>;<br>
 def STDFp2SrcRm : SDTypeProfile<1, 3, [SDTCisSameAs<0,1>,<br>
                            SDTCisVec<0>, SDTCisInt<3>]>;<br>
+def STDFp3SrcRm : SDTypeProfile<1, 4, [SDTCisSameAs<0,1>,<br>
+                           SDTCisVec<0>, SDTCisInt<3>, SDTCisInt<4>]>;<br>
<br>
 def X86PAlignr : SDNode<"X86ISD::PALIGNR", SDTShuff3OpI>;<br>
 def X86VAlign  : SDNode<"X86ISD::VALIGN", SDTShuff3OpI>;<br>
@@ -299,6 +301,7 @@ def X86exp2      : SDNode<"X86ISD::EXP2"<br>
<br>
 def X86rsqrt28s  : SDNode<"X86ISD::RSQRT28",  STDFp2SrcRm>;<br>
 def X86rcp28s    : SDNode<"X86ISD::RCP28",    STDFp2SrcRm>;<br>
+def X86RndScale  : SDNode<"X86ISD::RNDSCALE", STDFp3SrcRm>;<br>
<br>
 def SDT_PCMPISTRI : SDTypeProfile<2, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,<br>
                                          SDTCisVT<2, v16i8>, SDTCisVT<3, v16i8>,<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86IntrinsicsInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>X86/X86IntrinsicsInfo.h?rev=<u></u>229837&r1=229836&r2=229837&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86IntrinsicsInfo.h (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86IntrinsicsInfo.h Thu Feb 19 04:48:04 2015<br>
@@ -378,6 +378,10 @@ static const IntrinsicData  IntrinsicsWi<br>
   X86_INTRINSIC_DATA(avx512_<u></u>mask_psrli_q,       VSHIFT_MASK, X86ISD::VSRLI, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>mask_psrlv_d,       INTR_TYPE_2OP_MASK, ISD::SRL, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>mask_psrlv_q,       INTR_TYPE_2OP_MASK, ISD::SRL, 0),<br>
+  X86_INTRINSIC_DATA(avx512_<u></u>mask_rndscale_sd,   INTR_TYPE_SCALAR_MASK_RM,<br>
+                     X86ISD::RNDSCALE, 0),<br>
+  X86_INTRINSIC_DATA(avx512_<u></u>mask_rndscale_ss,   INTR_TYPE_SCALAR_MASK_RM,<br>
+                     X86ISD::RNDSCALE, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>mask_sub_pd_512, INTR_TYPE_2OP_MASK, ISD::FSUB,<br>
                      X86ISD::FSUB_RND),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>mask_sub_ps_512, INTR_TYPE_2OP_MASK, ISD::FSUB,<br>
@@ -396,8 +400,8 @@ static const IntrinsicData  IntrinsicsWi<br>
   X86_INTRINSIC_DATA(avx512_<u></u>mask_ucmp_w_512,    CMP_MASK_CC,  X86ISD::CMPMU, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>rcp28_pd,   INTR_TYPE_1OP_MASK_RM,X86ISD::<u></u>RCP28, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>rcp28_ps,   INTR_TYPE_1OP_MASK_RM,X86ISD::<u></u>RCP28, 0),<br>
-  X86_INTRINSIC_DATA(avx512_<u></u>rcp28_sd,   INTR_TYPE_SCALAR_MASK_RM,<u></u>X86ISD::RCP28, 0),<br>
-  X86_INTRINSIC_DATA(avx512_<u></u>rcp28_ss,   INTR_TYPE_SCALAR_MASK_RM,<u></u>X86ISD::RCP28, 0),<br>
+  X86_INTRINSIC_DATA(avx512_<u></u>rcp28_sd,   INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28, 0),<br>
+  X86_INTRINSIC_DATA(avx512_<u></u>rcp28_ss,   INTR_TYPE_SCALAR_MASK_RM, X86ISD::RCP28, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>rsqrt28_pd, INTR_TYPE_1OP_MASK_RM,X86ISD::<u></u>RSQRT28, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>rsqrt28_ps, INTR_TYPE_1OP_MASK_RM,X86ISD::<u></u>RSQRT28, 0),<br>
   X86_INTRINSIC_DATA(avx512_<u></u>rsqrt28_sd, INTR_TYPE_SCALAR_MASK_RM,<u></u>X86ISD::RSQRT28, 0),<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<u></u>avx512-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/test/<u></u>CodeGen/X86/avx512-intrinsics.<u></u>ll?rev=229837&r1=229836&r2=<u></u>229837&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/test/CodeGen/X86/<u></u>avx512-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<u></u>avx512-intrinsics.ll Thu Feb 19 04:48:04 2015<br>
@@ -68,6 +68,14 @@ define <8 x double> @test7(<8 x double><br>
   ret <8 x double>%res<br>
 }<br>
<br>
+declare <2 x double> @<a href="http://llvm.x86.avx512.mask.rndscale.sd" target="_blank">llvm.x86.avx512.mask.<u></u>rndscale.sd</a>(<2 x double>, <2 x double>, <2 x double>, i8, i32, i32)<br>
+<br>
+define <2 x double> @test_rndsc_sd(<2 x double> %a, <2 x double> %b, <2 x double> %c) {<br>
+; CHECK: vrndscalesd $11, %xmm{{.*}} {%k1} ## encoding: [0x62,0xf3,0xfd,0x09,0x0b,<u></u>0xd1,0x0b]<br>
+  %res = call <2 x double> @<a href="http://llvm.x86.avx512.mask.rndscale.sd" target="_blank">llvm.x86.avx512.mask.<u></u>rndscale.sd</a>(<2 x double> %a, <2 x double> %b, <2 x double> %c, i8 5, i32 11, i32 4)<br>
+  ret <2 x double>%res<br>
+}<br>
+<br>
 declare <16 x float> @llvm.x86.avx512.mask.<u></u>rndscale.ps.512(<16 x float>, i32, <16 x float>, i16, i32)<br>
<br>
 define <16 x float> @test8(<16 x float> %a) {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/<u></u>avx512-round.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-round.ll?rev=229837&r1=229836&r2=229837&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/test/<u></u>CodeGen/X86/avx512-round.ll?<u></u>rev=229837&r1=229836&r2=<u></u>229837&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/test/CodeGen/X86/<u></u>avx512-round.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/<u></u>avx512-round.ll Thu Feb 19 04:48:04 2015<br>
@@ -79,3 +79,28 @@ define <8 x double> @nearbyint_v8f64(<8<br>
   ret <8 x double> %res<br>
 }<br>
 declare <8 x double> @llvm.nearbyint.v8f64(<8 x double> %p)<br>
+<br>
+define double @nearbyint_f64(double %a) {<br>
+; CHECK-LABEL: nearbyint_f64<br>
+; CHECK: vrndscalesd $12, {{.*}}encoding: [0x62,0xf3,0xfd,0x08,0x0b,<u></u>0xc0,0x0c]<br>
+  %res = call double @llvm.nearbyint.f64(double %a)<br>
+  ret double %res<br>
+}<br>
+declare double @llvm.nearbyint.f64(double %p)<br>
+<br>
+define float @floor_f32(float %a) {<br>
+; CHECK-LABEL: floor_f32<br>
+; CHECK: vrndscaless $1, {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,<u></u>0xc0,0x01]<br>
+  %res = call float @llvm.floor.f32(float %a)<br>
+  ret float %res<br>
+}<br>
+declare float @llvm.floor.f32(float %p)<br>
+<br>
+define float @floor_f32m(float* %aptr) {<br>
+; CHECK-LABEL: floor_f32m<br>
+; CHECK: vrndscaless $1, (%rdi), {{.*}}encoding: [0x62,0xf3,0x7d,0x08,0x0a,<u></u>0x07,0x01]<br>
+  %a = load float* %aptr, align 4<br>
+  %res = call float @llvm.floor.f32(float %a)<br>
+  ret float %res<br>
+}<br>
+<br>
<br>
<br>
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</blockquote></div></div>