<div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span><br>
>   mov r0, #~0xffffff00<br>
> The problem is that I've added a spurious range check on the immediate<br>
> operand to ensure that it lies between INT32_MIN and UINT32_MAX. While<br>
> this range check is correct in theory, it causes problems because the<br>
> operand is stored in an int64_t (by MC). So valid 32-bit constants like<br>
> \#~0xffffff00 become out of range. The solution is to simply remove this<br>
> range check. It is not possible to validate the range of the immediate<br>
> operand with the current setup because: 1) The operand is stored in an<br>
> int64_t by MC, 2) The immediate can be of the forms #imm, #-imm, #~imm<br>
> or even #((~imm)) etc. So we just chop the value to 32 bits and use it.<br>
<br>
</span>In all these cases, "imm" is a 32-bit constant, so the upper 32 bits<br>
are either all ones or all zeros, no?  Perhaps that would be useful as<br>
a limited form of check.<br></blockquote><div><br></div><div>Nice catch! :)</div><div><br></div><div>I'll add that in. Can't see any fault in that argument.</div><div><br></div><div>Thanks!</div><div><br></div><div>- Asiri</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<span><font color="#888888"><br>
-Ahmed<br>
</font></span><div><div><br>
> Also noted that the original range check was note tested by any of the<br>
> unit tests. I've added a new test to cover #~imm kind of operands.<br>
><br>
> Change-Id: I411e90d84312a2eff01b732bb238af536c4a7599<br>
><br>
> Modified:<br>
>     llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
>     llvm/trunk/test/MC/ARM/basic-arm-instructions.s<br>
><br>
> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=228920&r1=228919&r2=228920&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=228920&r1=228919&r2=228920&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)<br>
> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Feb 12 07:37:28 2015<br>
> @@ -4424,11 +4424,6 @@ ARMAsmParser::parseModImm(OperandVector<br>
>    if (CE) {<br>
>      // Immediate must fit within 32-bits<br>
>      Imm1 = CE->getValue();<br>
> -    if (Imm1 < INT32_MIN || Imm1 > UINT32_MAX) {<br>
> -      Error(Sx1, "immediate operand must be representable with 32 bits");<br>
> -      return MatchOperand_ParseFail;<br>
> -    }<br>
> -<br>
>      int Enc = ARM_AM::getSOImmVal(Imm1);<br>
>      if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {<br>
>        // We have a match!<br>
><br>
> Modified: llvm/trunk/test/MC/ARM/basic-arm-instructions.s<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=228920&r1=228919&r2=228920&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/basic-arm-instructions.s?rev=228920&r1=228919&r2=228920&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/MC/ARM/basic-arm-instructions.s (original)<br>
> +++ llvm/trunk/test/MC/ARM/basic-arm-instructions.s Thu Feb 12 07:37:28 2015<br>
> @@ -1509,6 +1509,7 @@ Lforward:<br>
>          mvn r3, $7<br>
>          mvn r3, 7<br>
>          mvn r3, -7<br>
> +        mvn r7, #~0xffffff00<br>
>          mvn r4, #0xff0<br>
>          mvn r5, #0xff0000<br>
>         mvn r7, #(0xff << 16)<br>
> @@ -1526,6 +1527,7 @@ Lforward:<br>
>  @ CHECK: mvn   r3, #7                  @ encoding: [0x07,0x30,0xe0,0xe3]<br>
>  @ CHECK: mvn   r3, #7                  @ encoding: [0x07,0x30,0xe0,0xe3]<br>
>  @ CHECK: mov   r3, #6                  @ encoding: [0x06,0x30,0xa0,0xe3]<br>
> +@ CHECK: mvn    r7, #255                @ encoding: [0xff,0x70,0xe0,0xe3]<br>
>  @ CHECK: mvn   r4, #4080               @ encoding: [0xff,0x4e,0xe0,0xe3]<br>
>  @ CHECK: mvn   r5, #16711680           @ encoding: [0xff,0x58,0xe0,0xe3]<br>
>  @ CHECK: mvn   r7, #16711680           @ encoding: [0xff,0x78,0xe0,0xe3]<br>
><br>
><br>
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</div></div></blockquote></div><br></div></div>