<font face="Default Sans Serif,Verdana,Arial,Helvetica,sans-serif" size="2"><br><br><font color="#990099">-----Forwarded by Olivier H Sallenave/Watson/IBM on 02/09/2015 03:33PM -----</font><div style="padding-left:5px;"><div style="padding-right:0px;padding-left:5px;border-left:solid black 2px;">To: Olivier H Sallenave/Watson/IBM@IBMUS, hfinkel@anl.gov<br>From: Olivier H Sallenave/Watson/IBM@IBMUS<br>Date: 02/09/2015 11:12AM<br>Subject: [PATCH] Tune TTI getMaxInterleaveFactor for POWER8<br><br><i>(See attached file: D7503.19581.patch)</i><br><br><div><font face="Courier New,Courier,monospace" size="3">Hi hfinkel,<br><br>For the P8, VSU instructions have a 6-cycle latency and there are two VSU units, so unroll by 12x for latency hiding.<br><br><a href="http://reviews.llvm.org/D7503">http://reviews.llvm.org/D7503</a><br><br>Files:<br>  lib/Target/PowerPC/PPCTargetTransformInfo.cpp<br><br>Index: lib/Target/PowerPC/PPCTargetTransformInfo.cpp<br>===================================================================<br>--- lib/Target/PowerPC/PPCTargetTransformInfo.cpp<br>+++ lib/Target/PowerPC/PPCTargetTransformInfo.cpp<br>@@ -226,6 +226,11 @@<br>   if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)<br>     return 1;<br><br>+  // For the P8, VSU instructions have a 6-cycle latency and there are two VSU<br>+  // units, so unroll by 12x for latency hiding.<br>+  if (Directive == PPC::DIR_PWR8)<br>+    return 12;<br>+<br>   // For most things, modern systems have two execution units (and<br>   // out-of-order execution).<br>   return 2;<br><br>EMAIL PREFERENCES<br>  <a href="http://reviews.llvm.org/settings/panel/emailpreferences/">http://reviews.llvm.org/settings/panel/emailpreferences/</a><br></font></div></div></div></font>