<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Feb 6, 2015 at 3:15 PM, Ahmed Bougacha <span dir="ltr"><<a href="mailto:ahmed.bougacha@gmail.com" target="_blank">ahmed.bougacha@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ab<br>
Date: Fri Feb  6 17:15:39 2015<br>
New Revision: 228463<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=228463&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=228463&view=rev</a><br>
Log:<br>
[AArch64] Use the source location of the IR branch when creating Bcc<br>
from a conditional branch fed by an add/sub/mul-with-overflow node.<br>
<br>
We previously used the SDLoc of the overflow node, for no good reason.<br>
In some cases, this led to the Bcc and B terminators having different<br>
source orders, and DBG_VALUEs being inserted between them.<br>
<br>
The real issue is with the code that can't handle DBG_VALUEs between<br>
terminators: the few places affected by this will be fixed soon.<br>
In the meantime, fixing the SDLoc is a positive change no matter what.<br>
<br>
No tests, as I have no idea how to get .loc emitted for branches?<br></blockquote><div><br>.loc should be emitted for any instruction with a debug location (clang does omit debug locations on various branches from the frontend, but you can add them in by hand or find a case where clang doesn't omit them... ).<br> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
rdar://19347133<br>
<br>
Modified:<br>
    llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=228463&r1=228462&r2=228463&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=228463&r1=228462&r2=228463&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Feb  6 17:15:39 2015<br>
@@ -3263,8 +3263,8 @@ SDValue AArch64TargetLowering::LowerBR_C<br>
       OFCC = getInvertedCondCode(OFCC);<br>
     SDValue CCVal = DAG.getConstant(OFCC, MVT::i32);<br>
<br>
-    return DAG.getNode(AArch64ISD::BRCOND, SDLoc(LHS), MVT::Other, Chain, Dest,<br>
-                       CCVal, Overflow);<br>
+    return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,<br>
+                       Overflow);<br>
   }<br>
<br>
   if (LHS.getValueType().isInteger()) {<br>
<br>
<br>
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</blockquote></div><br></div></div>