<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">holy flashback, batman!<div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Feb 5, 2015, at 1:37 AM, Chandler Carruth <<a href="mailto:chandlerc@google.com" class="">chandlerc@google.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">Thread necromancy time!<div class="gmail_extra"><br class=""><div class="gmail_quote">On Fri, Nov 22, 2013 at 11:57 AM, Jim Grosbach<span class="Apple-converted-space"> </span><span dir="ltr" class=""><<a href="mailto:grosbach@apple.com" target="_blank" class="">grosbach@apple.com</a>></span><span class="Apple-converted-space"> </span>wrote:<br class=""><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;">Author: grosbach<br class="">Date: Fri Nov 22 13:57:47 2013<br class="">New Revision: 195496<br class=""><br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=195496&view=rev" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=195496&view=rev</a><br class="">Log:<br class="">X86: Perform integer comparisons at i32 or larger.<br class=""><br class="">Utilizing the 8 and 16 bit comparison instructions, even when an input can<br class="">be folded into the comparison instruction itself, is typically not worth it.<br class="">There are too many partial register stalls as a result, leading to significant<br class="">slowdowns. By always performing comparisons on at least 32-bit<br class="">registers, performance of the calculation chain leading to the<br class="">comparison improves. Continue to use the smaller comparisons when<br class="">minimizing size, as that allows better folding of loads into the<br class="">comparison instructions.<br class=""></blockquote><div class=""><br class=""></div><div class="">So, there was a bunch of debate as to whether this was actually causing stalls, or the stalls came from some other artifact of bzip2 and this just perturbed the code enough to hide them, etc.</div><div class=""><br class=""></div><div class="">Check out<span class="Apple-converted-space"> </span><a href="http://llvm.org/PR22473" class="">http://llvm.org/PR22473</a><span class="Apple-converted-space"> </span>-- I'm increasingly thinking that we may have been chasing ghosts on this one Jim. If the problem persists after Quentin's work to improve bzip2, I think we need a might more precise fix. This hammer seems too big and to be squashing lots of other things.</div><div class=""><br class=""></div><div class="">What do you think about potentially reversing course here? Are there benchmarks you can run internally to see if backing this out causes any significant regressions these days?</div></div></div></div></div></blockquote><div><br class=""></div><div>This is reasonable to me. This PR combined with our previous discussions has convinced me there’s something more subtle going on in bzip2. As long as folks are willing to pursue that and not regress our perf there, I don’t mind backing this out.</div><div><br class=""></div><div>I’ll try to reproduce and see if there’s any regression to worry about.</div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><div class="gmail_extra"><div class="gmail_quote"><div class=""> </div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;"><br class=""><a href="rdar://15386341" class="">rdar://15386341</a><br class=""><br class="">Removed:<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/X86/2007-10-17-IllegalAsm.ll<br class="">Modified:<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/X86/3addr-16bit.ll<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/X86/codegen-prepare-extload.ll<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/X86/ctpop-combine.ll<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/X86/memcmp.ll<br class=""> <span class="Apple-converted-space"> </span>llvm/trunk/test/CodeGen/X86/shrink-compare.ll<br class=""><br class="">Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=195496&r1=195495&r2=195496&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=195496&r1=195495&r2=195496&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br class="">+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Nov 22 13:57:47 2013<br class="">@@ -3419,6 +3419,24 @@ bool X86::isCalleePop(CallingConv::ID Ca<br class=""> }<br class=""> }<br class=""><br class="">+/// \brief Return true if the condition is an unsigned comparison operation.<br class="">+static bool isX86CCUnsigned(unsigned X86CC) {<br class="">+ switch (X86CC) {<br class="">+ default: llvm_unreachable("Invalid integer condition!");<br class="">+ case X86::COND_E: return true;<br class="">+ case X86::COND_G: return false;<br class="">+ case X86::COND_GE: return false;<br class="">+ case X86::COND_L: return false;<br class="">+ case X86::COND_LE: return false;<br class="">+ case X86::COND_NE: return true;<br class="">+ case X86::COND_B: return true;<br class="">+ case X86::COND_A: return true;<br class="">+ case X86::COND_BE: return true;<br class="">+ case X86::COND_AE: return true;<br class="">+ }<br class="">+ llvm_unreachable("covered switch fell through?!");<br class="">+}<br class="">+<br class=""> /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86<br class=""> /// specific condition code, returning the condition code and the LHS/RHS of the<br class=""> /// comparison to make.<br class="">@@ -9662,6 +9680,17 @@ SDValue X86TargetLowering::EmitCmp(SDVal<br class=""> SDLoc dl(Op0);<br class=""> if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||<br class=""> <span class="Apple-converted-space"> </span>Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {<br class="">+ // Do the comparison at i32 if it's smaller. This avoids subregister<br class="">+ // aliasing issues. Keep the smaller reference if we're optimizing for<br class="">+ // size, however, as that'll allow better folding of memory operations.<br class="">+ if (Op0.getValueType() != MVT::i32 && Op0.getValueType() != MVT::i64 &&<br class="">+ !DAG.getMachineFunction().getFunction()->getAttributes().hasAttribute(<br class="">+ AttributeSet::FunctionIndex, Attribute::MinSize)) {<br class="">+ unsigned ExtendOp =<br class="">+ isX86CCUnsigned(X86CC) ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND;<br class="">+ Op0 = DAG.getNode(ExtendOp, dl, MVT::i32, Op0);<br class="">+ Op1 = DAG.getNode(ExtendOp, dl, MVT::i32, Op1);<br class="">+ }<br class=""> // Use SUB instead of CMP to enable CSE between SUB and CMP.<br class=""> SDVTList VTs = DAG.getVTList(Op0.getValueType(), MVT::i32);<br class=""> SDValue Sub = DAG.getNode(X86ISD::SUB, dl, VTs,<br class=""><br class="">Removed: llvm/trunk/test/CodeGen/X86/2007-10-17-IllegalAsm.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-10-17-IllegalAsm.ll?rev=195495&view=auto" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-10-17-IllegalAsm.ll?rev=195495&view=auto</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/2007-10-17-IllegalAsm.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/2007-10-17-IllegalAsm.ll (removed)<br class="">@@ -1,87 +0,0 @@<br class="">-; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep addb | not grep x<br class="">-; RUN: llc < %s -mtriple=x86_64-linux-gnu | grep cmpb | not grep x<br class="">-; PR1734<br class="">-<br class="">-target triple = "x86_64-unknown-linux-gnu"<br class="">- %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }<br class="">- %struct.eh_status = type opaque<br class="">- %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** }<br class="">- %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* }<br class="">- %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, %struct.tree_node*, i8, i8, i8 }<br class="">- %struct.initial_value_struct = type opaque<br class="">- %struct.lang_decl = type opaque<br class="">- %struct.language_function = type opaque<br class="">- %struct.location_t = type { i8*, i32 }<br class="">- %struct.machine_function = type { %struct.stack_local_entry*, i8*, %struct.rtx_def*, i32, i32, i32, i32, i32 }<br class="">- %struct.rtunion = type { i8* }<br class="">- %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] }<br class="">- %struct.rtx_def = type { i16, i8, i8, %struct.u }<br class="">- %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* }<br class="">- %struct.stack_local_entry = type opaque<br class="">- %struct.temp_slot = type opaque<br class="">- %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %union.tree_ann_d*, i8, i8, i8, i8, i8 }<br class="">- %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* }<br class="">- %struct.tree_decl_u1 = type { i64 }<br class="">- %struct.tree_decl_u2 = type { %struct.function* }<br class="">- %struct.tree_node = type { %struct.tree_decl }<br class="">- %struct.u = type { [1 x %struct.rtunion] }<br class="">- %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* }<br class="">- %struct.varasm_status = type opaque<br class="">- %struct.varray_data = type { [1 x i64] }<br class="">- %struct.varray_head_tag = type { i64, i64, i32, i8*, %struct.varray_data }<br class="">- %union.tree_ann_d = type opaque<br class="">-<br class="">-define void @layout_type(%struct.tree_node* %type) {<br class="">-entry:<br class="">- %tmp32 = load i32* null, align 8 ; <i32> [#uses=3]<br class="">- %tmp3435 = trunc i32 %tmp32 to i8 ; <i8> [#uses=1]<br class="">- %tmp53 = icmp eq %struct.tree_node* null, null ; <i1> [#uses=1]<br class="">- br i1 %tmp53, label %cond_next57, label %UnifiedReturnBlock<br class="">-<br class="">-cond_next57: ; preds = %entry<br class="">- %tmp65 = and i32 %tmp32, 255 ; <i32> [#uses=1]<br class="">- switch i32 %tmp65, label %UnifiedReturnBlock [<br class="">- i32 6, label %bb140<br class="">- i32 7, label %bb140<br class="">- i32 8, label %bb140<br class="">- i32 13, label %bb478<br class="">- ]<br class="">-<br class="">-bb140: ; preds = %cond_next57, %cond_next57, %cond_next57<br class="">- %tmp219 = load i32* null, align 8 ; <i32> [#uses=1]<br class="">- %tmp221222 = trunc i32 %tmp219 to i8 ; <i8> [#uses=1]<br class="">- %tmp223 = icmp eq i8 %tmp221222, 24 ; <i1> [#uses=1]<br class="">- br i1 %tmp223, label %cond_true226, label %cond_next340<br class="">-<br class="">-cond_true226: ; preds = %bb140<br class="">- switch i8 %tmp3435, label %cond_true288 [<br class="">- i8 6, label %cond_next340<br class="">- i8 9, label %cond_next340<br class="">- i8 7, label %cond_next340<br class="">- i8 8, label %cond_next340<br class="">- i8 10, label %cond_next340<br class="">- ]<br class="">-<br class="">-cond_true288: ; preds = %cond_true226<br class="">- unreachable<br class="">-<br class="">-cond_next340: ; preds = %cond_true226, %cond_true226, %cond_true226, %cond_true226, %cond_true226, %bb140<br class="">- ret void<br class="">-<br class="">-bb478: ; preds = %cond_next57<br class="">- br i1 false, label %cond_next500, label %cond_true497<br class="">-<br class="">-cond_true497: ; preds = %bb478<br class="">- unreachable<br class="">-<br class="">-cond_next500: ; preds = %bb478<br class="">- %tmp513 = load i32* null, align 8 ; <i32> [#uses=1]<br class="">- %tmp545 = and i32 %tmp513, 8192 ; <i32> [#uses=1]<br class="">- %tmp547 = and i32 %tmp32, -8193 ; <i32> [#uses=1]<br class="">- %tmp548 = or i32 %tmp547, %tmp545 ; <i32> [#uses=1]<br class="">- store i32 %tmp548, i32* null, align 8<br class="">- ret void<br class="">-<br class="">-UnifiedReturnBlock: ; preds = %cond_next57, %entry<br class="">- ret void<br class="">-}<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/3addr-16bit.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/3addr-16bit.ll?rev=195496&r1=195495&r2=195496&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/3addr-16bit.ll?rev=195496&r1=195495&r2=195496&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/3addr-16bit.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/3addr-16bit.ll Fri Nov 22 13:57:47 2013<br class="">@@ -34,7 +34,7 @@ entry:<br class=""><br class=""> ; 64BIT-LABEL: t2:<br class=""> ; 64BIT-NOT: movw %si, %ax<br class="">-; 64BIT: decl %eax<br class="">+; 64BIT: leal -1(%rsi), %eax<br class=""> ; 64BIT: movzwl %ax<br class=""> %0 = icmp eq i16 %k, %c ; <i1> [#uses=1]<br class=""> %1 = add i16 %k, -1 ; <i16> [#uses=3]<br class="">@@ -59,7 +59,7 @@ entry:<br class=""><br class=""> ; 64BIT-LABEL: t3:<br class=""> ; 64BIT-NOT: movw %si, %ax<br class="">-; 64BIT: addl $2, %eax<br class="">+; 64BIT: leal 2(%rsi), %eax<br class=""> %0 = add i16 %k, 2 ; <i16> [#uses=3]<br class=""> %1 = icmp eq i16 %k, %c ; <i1> [#uses=1]<br class=""> br i1 %1, label %bb, label %bb1<br class="">@@ -82,7 +82,7 @@ entry:<br class=""><br class=""> ; 64BIT-LABEL: t4:<br class=""> ; 64BIT-NOT: movw %si, %ax<br class="">-; 64BIT: addl %edi, %eax<br class="">+; 64BIT: leal (%rsi,%rdi), %eax<br class=""> %0 = add i16 %k, %c ; <i16> [#uses=3]<br class=""> %1 = icmp eq i16 %k, %c ; <i1> [#uses=1]<br class=""> br i1 %1, label %bb, label %bb1<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/codegen-prepare-extload.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/codegen-prepare-extload.ll?rev=195496&r1=195495&r2=195496&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/codegen-prepare-extload.ll?rev=195496&r1=195495&r2=195496&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/codegen-prepare-extload.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/codegen-prepare-extload.ll Fri Nov 22 13:57:47 2013<br class="">@@ -5,7 +5,7 @@<br class=""> ; CodeGenPrepare should move the zext into the block with the load<br class=""> ; so that SelectionDAG can select it with the load.<br class=""><br class="">-; CHECK: movzbl ({{%rdi|%rcx}}), %eax<br class="">+; CHECK: movsbl ({{%rdi|%rcx}}), %eax<br class=""><br class=""> define void @foo(i8* %p, i32* %q) {<br class=""> entry:<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/ctpop-combine.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=195496&r1=195495&r2=195496&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=195496&r1=195495&r2=195496&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/ctpop-combine.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/ctpop-combine.ll Fri Nov 22 13:57:47 2013<br class="">@@ -35,6 +35,6 @@ define i32 @test3(i64 %x) nounwind readn<br class=""> %conv = zext i1 %cmp to i32<br class=""> ret i32 %conv<br class=""> ; CHECK-LABEL: test3:<br class="">-; CHECK: cmpb $2<br class="">+; CHECK: cmpl $2<br class=""> ; CHECK: ret<br class=""> }<br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/memcmp.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memcmp.ll?rev=195496&r1=195495&r2=195496&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/memcmp.ll?rev=195496&r1=195495&r2=195496&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/memcmp.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/memcmp.ll Fri Nov 22 13:57:47 2013<br class="">@@ -22,8 +22,9 @@ bb:<br class=""> return: ; preds = %entry<br class=""> ret void<br class=""> ; CHECK-LABEL: memcmp2:<br class="">-; CHECK: movw ([[A0:%rdi|%rcx]]), %ax<br class="">-; CHECK: cmpw ([[A1:%rsi|%rdx]]), %ax<br class="">+; CHECK: movzwl<br class="">+; CHECK-NEXT: movzwl<br class="">+; CHECK-NEXT: cmpl<br class=""> ; NOBUILTIN-LABEL: memcmp2:<br class=""> ; NOBUILTIN: callq<br class=""> }<br class="">@@ -41,7 +42,8 @@ bb:<br class=""> return: ; preds = %entry<br class=""> ret void<br class=""> ; CHECK-LABEL: memcmp2a:<br class="">-; CHECK: cmpw $28527, ([[A0]])<br class="">+; CHECK: movzwl<br class="">+; CHECK-NEXT: cmpl $28527,<br class=""> }<br class=""><br class=""><br class="">@@ -58,8 +60,8 @@ bb:<br class=""> return: ; preds = %entry<br class=""> ret void<br class=""> ; CHECK-LABEL: memcmp4:<br class="">-; CHECK: movl ([[A0]]), %eax<br class="">-; CHECK: cmpl ([[A1]]), %eax<br class="">+; CHECK: movl<br class="">+; CHECK-NEXT: cmpl<br class=""> }<br class=""><br class=""> define void @memcmp4a(i8* %X, i32* nocapture %P) nounwind {<br class="">@@ -75,7 +77,7 @@ bb:<br class=""> return: ; preds = %entry<br class=""> ret void<br class=""> ; CHECK-LABEL: memcmp4a:<br class="">-; CHECK: cmpl $1869573999, ([[A0]])<br class="">+; CHECK: cmpl $1869573999,<br class=""> }<br class=""><br class=""> define void @memcmp8(i8* %X, i8* %Y, i32* nocapture %P) nounwind {<br class="">@@ -91,8 +93,8 @@ bb:<br class=""> return: ; preds = %entry<br class=""> ret void<br class=""> ; CHECK-LABEL: memcmp8:<br class="">-; CHECK: movq ([[A0]]), %rax<br class="">-; CHECK: cmpq ([[A1]]), %rax<br class="">+; CHECK: movq<br class="">+; CHECK: cmpq<br class=""> }<br class=""><br class=""> define void @memcmp8a(i8* %X, i32* nocapture %P) nounwind {<br class="">@@ -108,7 +110,7 @@ bb:<br class=""> return: ; preds = %entry<br class=""> ret void<br class=""> ; CHECK-LABEL: memcmp8a:<br class="">-; CHECK: movabsq $8029759185026510694, %rax<br class="">-; CHECK: cmpq %rax, ([[A0]])<br class="">+; CHECK: movabsq $8029759185026510694,<br class="">+; CHECK: cmpq<br class=""> }<br class=""><br class=""><br class="">Modified: llvm/trunk/test/CodeGen/X86/shrink-compare.ll<br class="">URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink-compare.ll?rev=195496&r1=195495&r2=195496&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/shrink-compare.ll?rev=195496&r1=195495&r2=195496&view=diff</a><br class="">==============================================================================<br class="">--- llvm/trunk/test/CodeGen/X86/shrink-compare.ll (original)<br class="">+++ llvm/trunk/test/CodeGen/X86/shrink-compare.ll Fri Nov 22 13:57:47 2013<br class="">@@ -2,7 +2,7 @@<br class=""><br class=""> declare void @bar()<br class=""><br class="">-define void @test1(i32* nocapture %X) nounwind {<br class="">+define void @test1(i32* nocapture %X) nounwind minsize {<br class=""> entry:<br class=""> %tmp1 = load i32* %X, align 4<br class=""> %and = and i32 %tmp1, 255<br class="">@@ -19,7 +19,7 @@ if.end:<br class=""> ; CHECK: cmpb $47, (%{{rdi|rcx}})<br class=""> }<br class=""><br class="">-define void @test2(i32 %X) nounwind {<br class="">+define void @test2(i32 %X) nounwind minsize {<br class=""> entry:<br class=""> %and = and i32 %X, 255<br class=""> %cmp = icmp eq i32 %and, 47<br class="">@@ -35,7 +35,7 @@ if.end:<br class=""> ; CHECK: cmpb $47, %{{dil|cl}}<br class=""> }<br class=""><br class="">-define void @test3(i32 %X) nounwind {<br class="">+define void @test3(i32 %X) nounwind minsize {<br class=""> entry:<br class=""> %and = and i32 %X, 255<br class=""> %cmp = icmp eq i32 %and, 255<br class="">@@ -70,7 +70,7 @@ lor.end:<br class=""> @x = global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4<br class=""><br class=""> ; PR16551<br class="">-define void @test5(i32 %X) nounwind {<br class="">+define void @test5(i32 %X) nounwind minsize {<br class=""> entry:<br class=""> %bf.load = load i56* bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @x to i56*), align 4<br class=""> %bf.lshr = lshr i56 %bf.load, 32<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a><br class=""><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank" class="">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></blockquote></div></div></div></div></blockquote></div><br class=""></div></body></html>