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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Hi James,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Separately, Geoff ran into the same problem. He found that the problem occurs during sorting in AArch64A57FPLoadBalancing::colorChainSet(…). He will upload his patch for review.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>I didn’t see the need for the uniqueness property of the set for AllChains, but changing from std::set to std::vector (or SetVector) may be just hiding the problem. Geoff’s patch should address this.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Thanks,<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'>Sanjin<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D'><o:p> </o:p></span></p><p class=MsoNormal><b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'>From:</span></b><span style='font-size:10.0pt;font-family:"Tahoma","sans-serif"'> James Molloy [mailto:james@jamesmolloy.co.uk] <br><b>Sent:</b> Wednesday, January 28, 2015 12:01 PM<br><b>To:</b> reviews+D7231+public+a4fec8073b04be0b@reviews.llvm.org; ssijaric@codeaurora.org; james.molloy@arm.com; liujiangning1@gmail.com; t.p.northover@gmail.com<br><b>Cc:</b> llvm-commits@cs.uiuc.edu; kanheim@a-bix.com<br><b>Subject:</b> Re: [PATCH] [AArch64] Fix non-determinism in A57 FP Load Balancing<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Hi Sanjin,<br><br>Are you sure we don't need the uniqueness property of a set any more?<br><br>If not, SetVector seems like the right solution. <br><br>James<o:p></o:p></p><div><p class=MsoNormal>On Wed, 28 Jan 2015 at 18:48, Sanjin Sijaric <<a href="mailto:ssijaric@codeaurora.org">ssijaric@codeaurora.org</a>> wrote:<o:p></o:p></p><p class=MsoNormal>Hi jmolloy, Jiangning, t.p.northover,<br><br>Change the type of AllChains from std::set<unique_ptr<Chain>> to std::vector<unique_ptr<Chain>>, as traversing pointers contained in std::set doesn't guarantee a well-defined order. We have observed differences in register assignment in .s files produced with the exact same build. I don't see that duplicate entries can be added to AllChains, so it should be safe to replace std::set with std::vector. This way, traversal of AllChains will be well defined.<br><br>Example debug output with -debug-only=aarch64-a57-fp-load-balancing resulting in different traversal:<br><br>Compile #1:<br><br> colorChainSet(): #sets=4<br> - Parity=2, Color=Odd<br> - colorChain({%S19<def> = FMULSrr -> %S19<def> = FMULSrr}, Odd)<br> - Scavenged register: S3<br> - Destination register not changed.<br> - Parity=1, Color=Odd<br> - {%S18<def> = FMULSrr -> %S18<def> = FMULSrr} - not worthwhile changing; color remains Even<br> - colorChain({%S18<def> = FMULSrr -> %S18<def> = FMULSrr}, Even)<br> - Scavenged register: S2<br> - Destination register not changed.<br> - Parity=2, Color=Odd<br> - colorChain({%S6<def> = FMULSrr -> %S6<def> = FMULSrr (kill @ %S18<def> = FMULSrr)}, Odd)<br> - Scavenged register: S3<br> - Kill instruction seen.<br> - Parity=1, Color=Odd<br> - colorChain({%S16<def> = FMULSrr -> %S16<def> = FMULSrr (kill @ %S19<def> = FMULSrr)}, Odd)<br> - Scavenged register: S5<br> - Kill instruction seen.<br><br>Compile #2:<br><br> colorChainSet(): #sets=4<br> - Parity=2, Color=Odd<br> - colorChain({%S19<def> = FMULSrr -> %S19<def> = FMULSrr}, Odd)<br> - Scavenged register: S3<br> - Destination register not changed.<br> - Parity=1, Color=Odd<br> - {%S18<def> = FMULSrr -> %S18<def> = FMULSrr} - not worthwhile changing; color remains Even<br> - colorChain({%S18<def> = FMULSrr -> %S18<def> = FMULSrr}, Even)<br> - Scavenged register: S2<br> - Destination register not changed.<br> - Parity=2, Color=Odd<br> - colorChain({%S16<def> = FMULSrr -> %S16<def> = FMULSrr (kill @ %S19<def> = FMULSrr)}, Odd)<br> - Scavenged register: S3<br> - Kill instruction seen.<br> - Parity=1, Color=Odd<br> - colorChain({%S6<def> = FMULSrr -> %S6<def> = FMULSrr (kill @ %S18<def> = FMULSrr)}, Odd)<br> - Scavenged register: S5<br> - Kill instruction seen.<br><br>Cannot have a reproducible test case for this.<br><br><a href="http://reviews.llvm.org/D7231" target="_blank">http://reviews.llvm.org/D7231</a><br><br>Files:<br> lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp<br><br>Index: lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp<br>===================================================================<br>--- lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp<br>+++ lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp<br>@@ -137,7 +137,7 @@<br> int scavengeRegister(Chain *G, Color C, MachineBasicBlock &MBB);<br> void scanInstruction(MachineInstr *MI, unsigned Idx,<br> std::map<unsigned, Chain*> &Active,<br>- std::set<std::unique_ptr<Chain>> &AllChains);<br>+ std::vector<std::unique_ptr<Chain>> &AllChains);<br> void maybeKillChain(MachineOperand &MO, unsigned Idx,<br> std::map<unsigned, Chain*> &RegChains);<br> Color getColor(unsigned Register);<br>@@ -320,7 +320,7 @@<br> // been killed yet. This is keyed by register - all chains can only have one<br> // "link" register between each inst in the chain.<br> std::map<unsigned, Chain*> ActiveChains;<br>- std::set<std::unique_ptr<Chain>> AllChains;<br>+ std::vector<std::unique_ptr<Chain>> AllChains;<br> unsigned Idx = 0;<br> for (auto &MI : MBB)<br> scanInstruction(&MI, Idx++, ActiveChains, AllChains);<br>@@ -583,7 +583,7 @@<br> void AArch64A57FPLoadBalancing::<br> scanInstruction(MachineInstr *MI, unsigned Idx,<br> std::map<unsigned, Chain*> &ActiveChains,<br>- std::set<std::unique_ptr<Chain>> &AllChains) {<br>+ std::vector<std::unique_ptr<Chain>> &AllChains) {<br> // Inspect "MI", updating ActiveChains and AllChains.<br><br> if (isMul(MI)) {<br>@@ -602,7 +602,7 @@<br><br> auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));<br> ActiveChains[DestReg] = G.get();<br>- AllChains.insert(std::move(G));<br>+ AllChains.push_back(std::move(G));<br><br> } else if (isMla(MI)) {<br><br>@@ -646,7 +646,7 @@<br> << TRI->getName(DestReg) << "\n");<br> auto G = llvm::make_unique<Chain>(MI, Idx, getColor(DestReg));<br> ActiveChains[DestReg] = G.get();<br>- AllChains.insert(std::move(G));<br>+ AllChains.push_back(std::move(G));<br><br> } else {<br><br>EMAIL PREFERENCES<br> <a href="http://reviews.llvm.org/settings/panel/emailpreferences/" target="_blank">http://reviews.llvm.org/settings/panel/emailpreferences/</a><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><o:p></o:p></p></div></div></body></html>