<div dir="ltr">Sorry, I had to revert this commit in r227248. It caused the following failure:<div><br></div><div><div>$ cat a.cc</div><div>#include <emmintrin.h></div><div>#include <stdio.h></div><div><br></div><div>typedef unsigned short U2;</div><div>typedef unsigned int U4;</div><div><br></div><div>typedef U4 V2x32 __attribute__((__vector_size__(8)));</div><div>typedef U2 V4x16 __attribute__((__vector_size__(8)));</div><div><br></div><div>int main() {</div><div> V4x16 a = {0, 1, 2, 3};</div><div> V4x16 b = {100, 101, 102, 103};</div><div> V2x32 c = _mm_madd_pi16(a, b);</div><div><br></div><div> printf("%d %d\n", c[0], c[1]);</div><div> return 0;</div><div>}</div><div><br></div><div><div>$ ./bin/clang++ a.cc && ./a.out</div><div>101 0</div></div></div><div><br></div><div>(expected result is 101 513)</div><div><br></div><div>This caused test failures in MSan test suite:</div><div><a href="http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/15572/steps/run%20msan%20unit%20tests/logs/stdio">http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux/builds/15572/steps/run%20msan%20unit%20tests/logs/stdio</a><br></div><div><br></div><div><br></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Jan 23, 2015 at 2:44 PM, Bruno Cardoso Lopes <span dir="ltr"><<a href="mailto:bruno.cardoso@gmail.com" target="_blank">bruno.cardoso@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: bruno<br>
Date: Fri Jan 23 16:44:16 2015<br>
New Revision: 226953<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=226953&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=226953&view=rev</a><br>
Log:<br>
[x86] Combine x86mmx/i64 to v2i64 conversion to use scalar_to_vector<br>
<br>
Handle the poor codegen for i64/x86xmm->v2i64 (%mm -> %xmm) moves. Instead of<br>
using stack store/load pair to do the job, use scalar_to_vector directly, which<br>
in the MMX case can use movq2dq. This was the current behavior prior to<br>
improvements for vector legalization of extloads in r213897.<br>
<br>
This commit fixes the regression and as a side-effect also remove some<br>
unnecessary shuffles.<br>
<br>
In the new attached testcase, we go from:<br>
<br>
pshufw $-18, (%rdi), %mm0<br>
movq %mm0, -8(%rsp)<br>
movq -8(%rsp), %xmm0<br>
pshufd $-44, %xmm0, %xmm0<br>
movd %xmm0, %eax<br>
...<br>
<br>
To:<br>
<br>
pshufw $-18, (%rdi), %mm0<br>
movq2dq %mm0, %xmm0<br>
movd %xmm0, %eax<br>
...<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D7126" target="_blank">http://reviews.llvm.org/D7126</a><br>
rdar://problem/19413324<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/mmx-movq2dq.ll<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll<br>
llvm/trunk/test/CodeGen/X86/lower-bitcast.ll<br>
llvm/trunk/test/CodeGen/X86/widen_load-2.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=226953&r1=226952&r2=226953&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=226953&r1=226952&r2=226953&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jan 23 16:44:16 2015<br>
@@ -24757,6 +24757,8 @@ static SDValue PerformLOADCombine(SDNode<br>
LoadSDNode *Ld = cast<LoadSDNode>(N);<br>
EVT RegVT = Ld->getValueType(0);<br>
EVT MemVT = Ld->getMemoryVT();<br>
+ SDValue Ptr = Ld->getBasePtr();<br>
+ SDValue Chain = Ld->getChain();<br>
SDLoc dl(Ld);<br>
const TargetLowering &TLI = DAG.getTargetLoweringInfo();<br>
<br>
@@ -24795,6 +24797,33 @@ static SDValue PerformLOADCombine(SDNode<br>
return DCI.CombineTo(N, NewVec, TF, true);<br>
}<br>
<br>
+ // Conversion from x86mmx/i64 to v2i64 types is often done via stack<br>
+ // store/load. Under certain conditions we can bypass the memory access and<br>
+ // combine this load to use a scalar_to_vector instead. This leads to<br>
+ // a reduction in the stack use, redundant emission of shuffles and create<br>
+ // isel matching candidates for movq2dq instructions.<br>
+ if (RegVT == MVT::v2i64 && Subtarget->hasSSE2() && Ext == ISD::EXTLOAD &&<br>
+ !Ld->isVolatile() && ISD::isNON_TRUNCStore(Chain.getNode())) {<br>
+<br>
+ // If this load is directly stored, get the original source value.<br>
+ StoreSDNode *PrevST = cast<StoreSDNode>(Chain);<br>
+ EVT SrcTy = PrevST->getValue().getValueType();<br>
+ if (PrevST->getBasePtr() != Ptr ||<br>
+ !(SrcTy == MVT::i64 || SrcTy == MVT::x86mmx))<br>
+ return SDValue();<br>
+ SDValue SrcVal = Chain.getOperand(1);<br>
+<br>
+ // On 32bit systems, we can't save 64bit integers, use f64 instead.<br>
+ bool Usef64 = TLI.isTypeLegal(MVT::f64) && !Subtarget->is64Bit();<br>
+ if (Usef64)<br>
+ SrcVal = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SrcVal);<br>
+ SrcVal = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, Usef64 ? MVT::v2f64 : RegVT,<br>
+ SrcVal);<br>
+<br>
+ return DCI.CombineTo(N, Usef64 ?<br>
+ DAG.getNode(ISD::BITCAST, dl, RegVT, SrcVal) : SrcVal, Chain);<br>
+ }<br>
+<br>
return SDValue();<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll?rev=226953&r1=226952&r2=226953&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll?rev=226953&r1=226952&r2=226953&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/2012-01-18-vbitcast.ll Fri Jan 23 16:44:16 2015<br>
@@ -1,14 +1,15 @@<br>
; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-pc-win32 | FileCheck %s<br>
<br>
-;CHECK-LABEL: vcast:<br>
+; CHECK-LABEL: vcast:<br>
define <2 x i32> @vcast(<2 x float> %a, <2 x float> %b) {<br>
-;CHECK: pmovzxdq<br>
-;CHECK: pmovzxdq<br>
+; CHECK-NOT: pmovzxdq<br>
+; CHECK-NOT: pmovzxdq<br>
+; CHECK: movdqa (%{{.*}}), %[[R0:xmm[0-9]+]]<br>
%af = bitcast <2 x float> %a to <2 x i32><br>
%bf = bitcast <2 x float> %b to <2 x i32><br>
+; CHECK-NEXT: psubq (%{{.*}}), %[[R0]]<br>
%x = sub <2 x i32> %af, %bf<br>
-;CHECK: psubq<br>
+; CHECK: ret<br>
ret <2 x i32> %x<br>
-;CHECK: ret<br>
}<br>
<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/lower-bitcast.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lower-bitcast.ll?rev=226953&r1=226952&r2=226953&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lower-bitcast.ll?rev=226953&r1=226952&r2=226953&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/lower-bitcast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/lower-bitcast.ll Fri Jan 23 16:44:16 2015<br>
@@ -68,12 +68,13 @@ define i64 @test4(i64 %A) {<br>
%2 = bitcast <2 x i32> %add to i64<br>
ret i64 %2<br>
}<br>
-; FIXME: At the moment we still produce the sequence pshufd+paddd+pshufd.<br>
+; FIXME: At the moment we still produce the sequence paddd+pshufd.<br>
; Ideally, we should fold that sequence into a single paddd. This is fixed with<br>
; the widening legalization.<br>
;<br>
; CHECK-LABEL: test4<br>
-; CHECK: pshufd<br>
+; CHECK: movd<br>
+; CHECK-NOT: pshufd<br>
; CHECK-NEXT: paddd<br>
; CHECK-NEXT: pshufd<br>
; CHECK: ret<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/mmx-movq2dq.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-movq2dq.ll?rev=226953&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-movq2dq.ll?rev=226953&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/mmx-movq2dq.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/mmx-movq2dq.ll Fri Jan 23 16:44:16 2015<br>
@@ -0,0 +1,29 @@<br>
+; RUN: llc < %s -march=x86 -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-32<br>
+; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s -check-prefix=X86-64<br>
+<br>
+; X86-32-LABEL: test0<br>
+; X86-64-LABEL: test0<br>
+define i32 @test0(<1 x i64>* %v4) {<br>
+ %v5 = load <1 x i64>* %v4, align 8<br>
+ %v12 = bitcast <1 x i64> %v5 to <4 x i16><br>
+ %v13 = bitcast <4 x i16> %v12 to x86_mmx<br>
+ ; X86-32: pshufw $238<br>
+ ; X86-32-NOT: movq<br>
+ ; X86-32-NOT: movsd<br>
+ ; X86-32: movq2dq<br>
+ ; X86-64: pshufw $238<br>
+ ; X86-64-NOT: movq<br>
+ ; X86-64-NOT: pshufd<br>
+ ; X86-64: movq2dq<br>
+ ; X86-64-NEXT: movd<br>
+ %v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)<br>
+ %v15 = bitcast x86_mmx %v14 to <4 x i16><br>
+ %v16 = bitcast <4 x i16> %v15 to <1 x i64><br>
+ %v17 = extractelement <1 x i64> %v16, i32 0<br>
+ %v18 = bitcast i64 %v17 to <2 x i32><br>
+ %v19 = extractelement <2 x i32> %v18, i32 0<br>
+ %v20 = add i32 %v19, 32<br>
+ ret i32 %v20<br>
+}<br>
+<br>
+declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/widen_load-2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-2.ll?rev=226953&r1=226952&r2=226953&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-2.ll?rev=226953&r1=226952&r2=226953&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/widen_load-2.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/widen_load-2.ll Fri Jan 23 16:44:16 2015<br>
@@ -78,8 +78,7 @@ define void @add3i16(%i16vec3* nocapture<br>
; CHECK-NEXT: paddd %[[R0]], %[[R1]]<br>
; CHECK-NEXT: pextrw $4, %[[R1]], 4(%{{.*}})<br>
; CHECK-NEXT: pshufb {{.*}}, %[[R1]]<br>
-; CHECK-NEXT: pmovzxdq %[[R1]], %[[R0]]<br>
-; CHECK-NEXT: movd %[[R0]], (%{{.*}})<br>
+; CHECK-NEXT: movd %[[R1]], (%{{.*}})<br>
%a = load %i16vec3* %ap, align 16<br>
%b = load %i16vec3* %bp, align 16<br>
%x = add %i16vec3 %a, %b<br>
<br>
<br>
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</blockquote></div><br><br clear="all"><div><br></div>-- <br><div class="gmail_signature"><div dir="ltr">Alexey Samsonov<br><a href="mailto:vonosmas@gmail.com" target="_blank">vonosmas@gmail.com</a></div></div>
</div>