<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Dec 23, 2014 at 12:02 PM, Colin LeMahieu <span dir="ltr"><<a href="mailto:colinl@codeaurora.org" target="_blank">colinl@codeaurora.org</a>></span> wrote:<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: colinl<br>
Date: Tue Dec 23 14:02:16 2014<br>
New Revision: 224786<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=224786&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=224786&view=rev</a><br>
Log:<br>
[Hexagon] Reapplying 224775 load words.<br></blockquote><div><br>When resubmitting a patch it's helpful to include the original commit message in full and an explanation of how the reason for the revert was addressed in the patch. (& possibly how the test coverage has been improved to cover the reason for the revert and any similar cases, etc)<br> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp<br>
llvm/trunk/test/CodeGen/Hexagon/cext-check.ll<br>
llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp Tue Dec 23 14:02:16 2014<br>
@@ -141,7 +141,7 @@ bool HexagonExpandPredSpillCode::runOnMa<br>
"Not a Frame Pointer, Nor a Spill Slot");<br>
assert(MI->getOperand(2).isImm() && "Not an offset");<br>
int Offset = MI->getOperand(2).getImm();<br>
- if (!TII->isValidOffset(Hexagon::LDriw, Offset)) {<br>
+ if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {<br>
if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) {<br>
BuildMI(*MBB, MII, MI->getDebugLoc(),<br>
TII->get(Hexagon::CONST32_Int_Real),<br>
@@ -150,7 +150,7 @@ bool HexagonExpandPredSpillCode::runOnMa<br>
HEXAGON_RESERVED_REG_1)<br>
.addReg(FP)<br>
.addReg(HEXAGON_RESERVED_REG_1);<br>
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),<br>
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),<br>
HEXAGON_RESERVED_REG_2)<br>
.addReg(HEXAGON_RESERVED_REG_1)<br>
.addImm(0);<br>
@@ -159,7 +159,7 @@ bool HexagonExpandPredSpillCode::runOnMa<br>
} else {<br>
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri),<br>
HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);<br>
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),<br>
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),<br>
HEXAGON_RESERVED_REG_2)<br>
.addReg(HEXAGON_RESERVED_REG_1)<br>
.addImm(0);<br>
@@ -167,7 +167,7 @@ bool HexagonExpandPredSpillCode::runOnMa<br>
DstReg).addReg(HEXAGON_RESERVED_REG_2);<br>
}<br>
} else {<br>
- BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw),<br>
+ BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::L2_loadri_io),<br>
HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset);<br>
BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::C2_tfrrp),<br>
DstReg).addReg(HEXAGON_RESERVED_REG_2);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp Tue Dec 23 14:02:16 2014<br>
@@ -405,7 +405,7 @@ SDNode *HexagonDAGToDAGISel::SelectBaseO<br>
TargAddr);<br>
// Figure out base + offset opcode<br>
if (LoadedVT == MVT::i64) Opcode = Hexagon::LDrid_indexed;<br>
- else if (LoadedVT == MVT::i32) Opcode = Hexagon::LDriw_indexed;<br>
+ else if (LoadedVT == MVT::i32) Opcode = Hexagon::L2_loadri_io;<br>
else if (LoadedVT == MVT::i16) Opcode = Hexagon::L2_loadrh_io;<br>
else if (LoadedVT == MVT::i8) Opcode = Hexagon::L2_loadrb_io;<br>
else llvm_unreachable("unknown memory type");<br>
@@ -602,7 +602,7 @@ SDNode *HexagonDAGToDAGISel::SelectIndex<br>
if (TII->isValidAutoIncImm(LoadedVT, Val))<br>
Opcode = Hexagon::POST_LDriw;<br>
else<br>
- Opcode = Hexagon::LDriw;<br>
+ Opcode = Hexagon::L2_loadri_io;<br>
} else if (LoadedVT == MVT::i16) {<br>
if (TII->isValidAutoIncImm(LoadedVT, Val))<br>
Opcode = zextval ? Hexagon::POST_LDriuh : Hexagon::POST_LDrih;<br>
@@ -865,7 +865,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(S<br>
<br>
SDValue Chain = LD->getChain();<br>
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);<br>
- OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,<br>
+ OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,<br>
MVT::Other,<br>
LD->getBasePtr(), TargetConst0,<br>
Chain), 0);<br>
@@ -891,7 +891,7 @@ SDNode *HexagonDAGToDAGISel::SelectMul(S<br>
<br>
SDValue Chain = LD->getChain();<br>
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);<br>
- OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,<br>
+ OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,<br>
MVT::Other,<br>
LD->getBasePtr(), TargetConst0,<br>
Chain), 0);<br>
@@ -1045,7 +1045,7 @@ SDNode *HexagonDAGToDAGISel::SelectTrunc<br>
<br>
SDValue Chain = LD->getChain();<br>
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);<br>
- OP0 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,<br>
+ OP0 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,<br>
MVT::Other,<br>
LD->getBasePtr(),<br>
TargetConst0, Chain), 0);<br>
@@ -1070,7 +1070,7 @@ SDNode *HexagonDAGToDAGISel::SelectTrunc<br>
<br>
SDValue Chain = LD->getChain();<br>
SDValue TargetConst0 = CurDAG->getTargetConstant(0, MVT::i32);<br>
- OP1 = SDValue (CurDAG->getMachineNode(Hexagon::LDriw, dl, MVT::i32,<br>
+ OP1 = SDValue(CurDAG->getMachineNode(Hexagon::L2_loadri_io, dl, MVT::i32,<br>
MVT::Other,<br>
LD->getBasePtr(),<br>
TargetConst0, Chain), 0);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Tue Dec 23 14:02:16 2014<br>
@@ -203,6 +203,7 @@ class InstHexagon<dag outs, dag ins, str<br>
<br>
// LD Instruction Class in V2/V3/V4.<br>
// Definition of the instruction class NOT CHANGED.<br>
+let mayLoad = 1 in<br>
class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],<br>
string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01><br>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Tue Dec 23 14:02:16 2014<br>
@@ -78,7 +78,7 @@ unsigned HexagonInstrInfo::isLoadFromSta<br>
<br>
switch (MI->getOpcode()) {<br>
default: break;<br>
- case Hexagon::LDriw:<br>
+ case Hexagon::L2_loadri_io:<br>
case Hexagon::LDrid:<br>
case Hexagon::L2_loadrh_io:<br>
case Hexagon::L2_loadrb_io:<br>
@@ -533,7 +533,7 @@ loadRegFromStackSlot(MachineBasicBlock &<br>
MFI.getObjectSize(FI),<br>
Align);<br>
if (RC == &Hexagon::IntRegsRegClass) {<br>
- BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)<br>
+ BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)<br>
.addFrameIndex(FI).addImm(0).addMemOperand(MMO);<br>
} else if (RC == &Hexagon::DoubleRegsRegClass) {<br>
BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)<br>
@@ -674,8 +674,7 @@ bool HexagonInstrInfo::isPredicable(Mach<br>
case Hexagon::LDrid_indexed:<br>
return isShiftedUInt<6,3>(MI->getOperand(2).getImm());<br>
<br>
- case Hexagon::LDriw:<br>
- case Hexagon::LDriw_indexed:<br>
+ case Hexagon::L2_loadri_io:<br>
return isShiftedUInt<6,2>(MI->getOperand(2).getImm());<br>
<br>
case Hexagon::L2_loadrh_io:<br>
@@ -1103,8 +1102,7 @@ isValidOffset(const int Opcode, const in<br>
<br>
switch(Opcode) {<br>
<br>
- case Hexagon::LDriw:<br>
- case Hexagon::LDriw_indexed:<br>
+ case Hexagon::L2_loadri_io:<br>
case Hexagon::LDriw_f:<br>
case Hexagon::STriw_indexed:<br>
case Hexagon::STriw:<br>
@@ -1352,10 +1350,8 @@ isConditionalLoad (const MachineInstr* M<br>
case Hexagon::LDrid_cNotPt :<br>
case Hexagon::LDrid_indexed_cPt :<br>
case Hexagon::LDrid_indexed_cNotPt :<br>
- case Hexagon::LDriw_cPt :<br>
- case Hexagon::LDriw_cNotPt :<br>
- case Hexagon::LDriw_indexed_cPt :<br>
- case Hexagon::LDriw_indexed_cNotPt :<br>
+ case Hexagon::L2_ploadrit_io:<br>
+ case Hexagon::L2_ploadrif_io:<br>
case Hexagon::L2_ploadrht_io:<br>
case Hexagon::L2_ploadrhf_io:<br>
case Hexagon::L2_ploadrbt_io:<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Tue Dec 23 14:02:16 2014<br>
@@ -1552,6 +1552,9 @@ let accessSize = HalfWordAccess, opExten<br>
defm loadruh: LD_Idxd <"memuh", "LDriuh", IntRegs, s11_1Ext, u6_1Ext, 0b1011>;<br>
}<br>
<br>
+let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in<br>
+defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;<br>
+<br>
///<br>
// Load -- MEMri operand<br>
multiclass LD_MEMri_Pbase<string mnemonic, RegisterClass RC,<br>
@@ -1592,9 +1595,6 @@ multiclass LD_MEMri<string mnemonic, str<br>
}<br>
<br>
let addrMode = BaseImmOffset, isMEMri = "true" in {<br>
- let accessSize = WordAccess in<br>
- defm LDriw: LD_MEMri < "memw", "LDriw", IntRegs, 13, 8>, AddrModeRel;<br>
-<br>
let accessSize = DoubleWordAccess in<br>
defm LDrid: LD_MEMri < "memd", "LDrid", DoubleRegs, 14, 9>, AddrModeRel;<br>
}<br>
@@ -1612,7 +1612,7 @@ def : Pat < (i32 (zextloadi16 ADDRriS11_<br>
(L2_loadruh_io AddrFI:$addr, 0) >;<br>
<br>
def : Pat < (i32 (load ADDRriS11_2:$addr)),<br>
- (LDriw ADDRriS11_2:$addr) >;<br>
+ (L2_loadri_io AddrFI:$addr, 0) >;<br>
<br>
def : Pat < (i64 (load ADDRriS11_3:$addr)),<br>
(LDrid ADDRriS11_3:$addr) >;<br>
@@ -1659,10 +1659,6 @@ multiclass LD_Idxd2<string mnemonic, str<br>
}<br>
<br>
let addrMode = BaseImmOffset in {<br>
- let accessSize = WordAccess in<br>
- defm LDriw_indexed: LD_Idxd2 <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext,<br>
- 13, 8>, AddrModeRel;<br>
-<br>
let accessSize = DoubleWordAccess in<br>
defm LDrid_indexed: LD_Idxd2 <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext,<br>
14, 9>, AddrModeRel;<br>
@@ -1682,7 +1678,7 @@ def : Pat < (i32 (zextloadi16 (add IntRe<br>
(L2_loadruh_io IntRegs:$src1, s11_1ExtPred:$offset) >;<br>
<br>
def : Pat < (i32 (load (add IntRegs:$src1, s11_2ExtPred:$offset))),<br>
- (LDriw_indexed IntRegs:$src1, s11_2ExtPred:$offset) >;<br>
+ (L2_loadri_io IntRegs:$src1, s11_2ExtPred:$offset) >;<br>
<br>
def : Pat < (i64 (load (add IntRegs:$src1, s11_3ExtPred:$offset))),<br>
(LDrid_indexed IntRegs:$src1, s11_3ExtPred:$offset) >;<br>
@@ -3661,10 +3657,10 @@ def : Pat<(atomic_load_16 (add (i32 IntR<br>
(i32 (L2_loadruh_io (i32 IntRegs:$src1), s11_1ImmPred:$offset))>;<br>
<br>
def : Pat<(atomic_load_32 ADDRriS11_2:$src1),<br>
- (i32 (LDriw ADDRriS11_2:$src1))>;<br>
+ (i32 (L2_loadri_io AddrFI:$src1, 0))>;<br>
<br>
def : Pat<(atomic_load_32 (add (i32 IntRegs:$src1), s11_2ImmPred:$offset)),<br>
- (i32 (LDriw_indexed (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;<br>
+ (i32 (L2_loadri_io (i32 IntRegs:$src1), s11_2ImmPred:$offset))>;<br>
<br>
// 64 bit atomic load<br>
def : Pat<(atomic_load_64 ADDRriS11_3:$src1),<br>
@@ -4028,7 +4024,7 @@ def: Pat <(i64 (sextloadi16 ADDRriS11_1<br>
// Convert sign-extended load back to load and sign extend.<br>
// i32 -> i64<br>
def: Pat <(i64 (sextloadi32 ADDRriS11_2:$src1)),<br>
- (i64 (A2_sxtw (LDriw ADDRriS11_2:$src1)))>;<br>
+ (i64 (A2_sxtw (L2_loadri_io AddrFI:$src1, 0)))>;<br>
<br>
<br>
// Zero extends.<br>
@@ -4084,18 +4080,18 @@ def: Pat <(i64 (zextloadi16 (add (i32 I<br>
<br>
// i32 -> i64<br>
def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),<br>
- (i64 (A2_combinew (A2_tfrsi 0), (LDriw ADDRriS11_2:$src1)))>,<br>
+ (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,<br>
Requires<[NoV4T]>;<br>
<br>
let AddedComplexity = 100 in<br>
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),<br>
- (i64 (A2_combinew (A2_tfrsi 0), (LDriw_indexed IntRegs:$src1,<br>
+ (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,<br>
s11_2ExtPred:$offset)))>,<br>
Requires<[NoV4T]>;<br>
<br>
let AddedComplexity = 10 in<br>
def: Pat <(i32 (zextloadi1 ADDRriS11_0:$src1)),<br>
- (i32 (LDriw ADDRriS11_0:$src1))>;<br>
+ (i32 (L2_loadri_io AddrFI:$src1, 0))>;<br>
<br>
// Map from Rs = Pd to Pd = mux(Pd, #1, #0)<br>
def : Pat <(i32 (zext (i1 PredRegs:$src1))),<br>
@@ -4116,14 +4112,14 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleR<br>
(i64 (zextloadi32 (i32 (add IntRegs:$src2,<br>
s11_2ExtPred:$offset2)))))),<br>
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),<br>
- (LDriw_indexed IntRegs:$src2,<br>
+ (L2_loadri_io IntRegs:$src2,<br>
s11_2ExtPred:$offset2)))>;<br>
<br>
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),<br>
(i32 32))),<br>
(i64 (zextloadi32 ADDRriS11_2:$srcLow)))),<br>
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),<br>
- (LDriw ADDRriS11_2:$srcLow)))>;<br>
+ (L2_loadri_io AddrFI:$srcLow, 0)))>;<br>
<br>
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),<br>
(i32 32))),<br>
@@ -4137,14 +4133,14 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleR<br>
(i64 (zextloadi32 (i32 (add IntRegs:$src2,<br>
s11_2ExtPred:$offset2)))))),<br>
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),<br>
- (LDriw_indexed IntRegs:$src2,<br>
+ (L2_loadri_io IntRegs:$src2,<br>
s11_2ExtPred:$offset2)))>;<br>
<br>
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),<br>
(i32 32))),<br>
(i64 (zextloadi32 ADDRriS11_2:$srcLow)))),<br>
(i64 (A2_combinew (EXTRACT_SUBREG (i64 DoubleRegs:$srcHigh), subreg_loreg),<br>
- (LDriw ADDRriS11_2:$srcLow)))>;<br>
+ (L2_loadri_io AddrFI:$srcLow, 0)))>;<br>
<br>
def: Pat<(i64 (or (i64 (shl (i64 DoubleRegs:$srcHigh),<br>
(i32 32))),<br>
@@ -4155,7 +4151,7 @@ def: Pat<(i64 (or (i64 (shl (i64 DoubleR<br>
// Any extended 64-bit load.<br>
// anyext i32 -> i64<br>
def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),<br>
- (i64 (A2_combinew (A2_tfrsi 0), (LDriw ADDRriS11_2:$src1)))>,<br>
+ (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io AddrFI:$src1, 0)))>,<br>
Requires<[NoV4T]>;<br>
<br>
// When there is an offset we should prefer the pattern below over the pattern above.<br>
@@ -4170,7 +4166,7 @@ def: Pat <(i64 (extloadi32 ADDRriS11_2:<br>
// ********************************************<br>
let AddedComplexity = 100 in<br>
def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),<br>
- (i64 (A2_combinew (A2_tfrsi 0), (LDriw_indexed IntRegs:$src1,<br>
+ (i64 (A2_combinew (A2_tfrsi 0), (L2_loadri_io IntRegs:$src1,<br>
s11_2ExtPred:$offset)))>,<br>
Requires<[NoV4T]>;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfoV4.td Tue Dec 23 14:02:16 2014<br>
@@ -460,23 +460,23 @@ def: Pat <(i64 (extloadi16 (add (i32 In<br>
<br>
// zext i32->i64<br>
def: Pat <(i64 (zextloadi32 ADDRriS11_2:$src1)),<br>
- (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,<br>
+ (i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 100 in<br>
def: Pat <(i64 (zextloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),<br>
- (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,<br>
+ (i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1,<br>
s11_2ExtPred:$offset)))>,<br>
Requires<[HasV4T]>;<br>
<br>
// anyext i32->i64<br>
def: Pat <(i64 (extloadi32 ADDRriS11_2:$src1)),<br>
- (i64 (COMBINE_Ir_V4 0, (LDriw ADDRriS11_2:$src1)))>,<br>
+ (i64 (COMBINE_Ir_V4 0, (L2_loadri_io AddrFI:$src1, 0)))>,<br>
Requires<[HasV4T]>;<br>
<br>
let AddedComplexity = 100 in<br>
def: Pat <(i64 (extloadi32 (i32 (add IntRegs:$src1, s11_2ExtPred:$offset)))),<br>
- (i64 (COMBINE_Ir_V4 0, (LDriw_indexed IntRegs:$src1,<br>
+ (i64 (COMBINE_Ir_V4 0, (L2_loadri_io IntRegs:$src1,<br>
s11_2ExtPred:$offset)))>,<br>
Requires<[HasV4T]>;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.cpp Tue Dec 23 14:02:16 2014<br>
@@ -159,7 +159,7 @@ void HexagonRegisterInfo::eliminateFrame<br>
//<br>
// r0 = add(r30, #10000)<br>
// r0 = memw(r0)<br>
- if ( (MI.getOpcode() == Hexagon::LDriw) ||<br>
+ if ( (MI.getOpcode() == Hexagon::L2_loadri_io) ||<br>
(MI.getOpcode() == Hexagon::LDrid) ||<br>
(MI.getOpcode() == Hexagon::L2_loadrh_io) ||<br>
(MI.getOpcode() == Hexagon::L2_loadruh_io) ||<br>
<br>
Modified: llvm/trunk/test/CodeGen/Hexagon/cext-check.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-check.ll?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/cext-check.ll?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Hexagon/cext-check.ll (original)<br>
+++ llvm/trunk/test/CodeGen/Hexagon/cext-check.ll Tue Dec 23 14:02:16 2014<br>
@@ -2,9 +2,9 @@<br>
; Check that we constant extended instructions only when necessary.<br>
<br>
define i32 @cext_test1(i32* %a) nounwind {<br>
-; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+##8000)<br>
+; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##8000)<br>
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300000)<br>
-; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}+##4092)<br>
+; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}##4092)<br>
; CHECK-NOT: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}##300)<br>
entry:<br>
%0 = load i32* %a, align 4<br>
<br>
Modified: llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=224786&r1=224785&r2=224786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt?rev=224786&r1=224785&r2=224786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt (original)<br>
+++ llvm/trunk/test/MC/Disassembler/Hexagon/ld.txt Tue Dec 23 14:02:16 2014<br>
@@ -38,3 +38,15 @@<br>
0x03 0x40 0x45 0x85 0xb1 0xda 0x75 0x47<br>
# CHECK: p3 = r5<br>
# CHECK-NEXT: if (!p3.new) r17 = memuh(r21 + #42)<br>
+0xb1 0xc2 0x95 0x91<br>
+# CHECK: r17 = memw(r21 + #84)<br>
+0xb1 0xda 0x95 0x41<br>
+# CHECK: if (p3) r17 = memw(r21 + #84)<br>
+0xb1 0xda 0x95 0x45<br>
+# CHECK: if (!p3) r17 = memw(r21 + #84)<br>
+0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x43<br>
+# CHECK: p3 = r5<br>
+# CHECK-NEXT: if (p3.new) r17 = memw(r21 + #84)<br>
+0x03 0x40 0x45 0x85 0xb1 0xda 0x95 0x47<br>
+# CHECK: p3 = r5<br>
+# CHECK-NEXT: if (!p3.new) r17 = memw(r21 + #84)<br>
<br>
<br>
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</blockquote></div></div></div>