<div dir="ltr">Oh yeah i should have mentioned that in the commit message. I removed it because ADCX has a pattern which will infer hasSideEffects = 0. ADOX doesn't have a pattern so tablgen will think it has side effects. Actually I probably should have removed the mayLoad from ADCX as well for a similar reason.<div><br></div><div>Thanks for noticing.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Dec 18, 2014 at 12:06 PM, Ahmed Bougacha <span dir="ltr"><<a href="mailto:ahmed.bougacha@gmail.com" target="_blank">ahmed.bougacha@gmail.com</a>></span> wrote:<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On Wed, Dec 17, 2014 at 9:02 PM, Craig Topper <<a href="mailto:craig.topper@gmail.com">craig.topper@gmail.com</a>> wrote:<br>
> Author: ctopper<br>
> Date: Wed Dec 17 23:02:08 2014<br>
> New Revision: 224495<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=224495&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=224495&view=rev</a><br>
> Log:<br>
> [X86] Remove unnecessary 'In64BitMode' predicate for instructions that already indicate use of REX.W.<br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86InstrArithmetic.td<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=224495&r1=224494&r2=224495&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrArithmetic.td?rev=224495&r1=224494&r2=224495&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td Wed Dec 17 23:02:08 2014<br>
> @@ -1355,19 +1355,19 @@ let Predicates = [HasBMI2] in {<br>
> //===----------------------------------------------------------------------===//<br>
> // ADCX Instruction<br>
> //<br>
> -let hasSideEffects = 0, Defs = [EFLAGS], Uses = [EFLAGS],<br>
> +let Predicates = [HasADX], Defs = [EFLAGS], Uses = [EFLAGS],<br>
<br>
</span>The hasSideEffects flag disappeared here but not for ADOX, was it intended?<br>
<span class="HOEnZb"><font color="#888888"><br>
-Ahmed<br>
</font></span><div class="HOEnZb"><div class="h5"><br>
> Constraints = "$src0 = $dst", AddedComplexity = 10 in {<br>
> let SchedRW = [WriteALU] in {<br>
> def ADCX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst),<br>
> (ins GR32:$src0, GR32:$src), "adcx{l}\t{$src, $dst|$dst, $src}",<br>
> [(set GR32:$dst, EFLAGS,<br>
> (X86adc_flag GR32:$src0, GR32:$src, EFLAGS))],<br>
> - IIC_BIN_CARRY_NONMEM>, T8PD, Requires<[HasADX]>;<br>
> + IIC_BIN_CARRY_NONMEM>, T8PD;<br>
> def ADCX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst),<br>
> (ins GR64:$src0, GR64:$src), "adcx{q}\t{$src, $dst|$dst, $src}",<br>
> [(set GR64:$dst, EFLAGS,<br>
> (X86adc_flag GR64:$src0, GR64:$src, EFLAGS))],<br>
> - IIC_BIN_CARRY_NONMEM>, T8PD, Requires<[HasADX, In64BitMode]>;<br>
> + IIC_BIN_CARRY_NONMEM>, T8PD;<br>
> } // SchedRW<br>
><br>
> let mayLoad = 1, SchedRW = [WriteALULd] in {<br>
> @@ -1375,37 +1375,34 @@ let hasSideEffects = 0, Defs = [EFLAGS],<br>
> (ins GR32:$src0, i32mem:$src), "adcx{l}\t{$src, $dst|$dst, $src}",<br>
> [(set GR32:$dst, EFLAGS,<br>
> (X86adc_flag GR32:$src0, (loadi32 addr:$src), EFLAGS))],<br>
> - IIC_BIN_CARRY_MEM>, T8PD, Requires<[HasADX]>;<br>
> + IIC_BIN_CARRY_MEM>, T8PD;<br>
><br>
> def ADCX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst),<br>
> (ins GR64:$src0, i64mem:$src), "adcx{q}\t{$src, $dst|$dst, $src}",<br>
> [(set GR64:$dst, EFLAGS,<br>
> (X86adc_flag GR64:$src0, (loadi64 addr:$src), EFLAGS))],<br>
> - IIC_BIN_CARRY_MEM>, T8PD, Requires<[HasADX, In64BitMode]>;<br>
> + IIC_BIN_CARRY_MEM>, T8PD;<br>
> }<br>
> }<br>
><br>
> //===----------------------------------------------------------------------===//<br>
> // ADOX Instruction<br>
> //<br>
> -let hasSideEffects = 0, Defs = [EFLAGS], Uses = [EFLAGS] in {<br>
> +let Predicates = [HasADX], hasSideEffects = 0, Defs = [EFLAGS],<br>
> + Uses = [EFLAGS] in {<br>
> let SchedRW = [WriteALU] in {<br>
> def ADOX32rr : I<0xF6, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),<br>
> - "adox{l}\t{$src, $dst|$dst, $src}",<br>
> - [], IIC_BIN_NONMEM>, T8XS, Requires<[HasADX]>;<br>
> + "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS;<br>
><br>
> def ADOX64rr : RI<0xF6, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),<br>
> - "adox{q}\t{$src, $dst|$dst, $src}",<br>
> - [], IIC_BIN_NONMEM>, T8XS, Requires<[HasADX, In64BitMode]>;<br>
> + "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_NONMEM>, T8XS;<br>
> } // SchedRW<br>
><br>
> let mayLoad = 1, SchedRW = [WriteALULd] in {<br>
> def ADOX32rm : I<0xF6, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),<br>
> - "adox{l}\t{$src, $dst|$dst, $src}",<br>
> - [], IIC_BIN_MEM>, T8XS, Requires<[HasADX]>;<br>
> + "adox{l}\t{$src, $dst|$dst, $src}", [], IIC_BIN_MEM>, T8XS;<br>
><br>
> def ADOX64rm : RI<0xF6, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),<br>
> - "adox{q}\t{$src, $dst|$dst, $src}",<br>
> - [], IIC_BIN_MEM>, T8XS, Requires<[HasADX, In64BitMode]>;<br>
> + "adox{q}\t{$src, $dst|$dst, $src}", [], IIC_BIN_MEM>, T8XS;<br>
> }<br>
> }<br>
><br>
><br>
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</div></div></blockquote></div><br clear="all"><div><br></div>-- <br><div class="gmail_signature">~Craig</div>
</div>