<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">2014-12-12 15:51 GMT+03:00 Robert Khasanov <span dir="ltr"><<a href="mailto:rob.khasanov@gmail.com" target="_blank">rob.khasanov@gmail.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div dir="ltr">Hi Adam,<br><div class="gmail_extra"><br><div class="gmail_quote"><div><div class="h5">2014-12-10 9:38 GMT+03:00 Adam Nemet <span dir="ltr"><<a href="mailto:anemet@apple.com" target="_blank">anemet@apple.com</a>></span>:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Hi Robert,<br>
<div><div><br>
> On Dec 9, 2014, at 10:45 AM, Robert Khasanov <<a href="mailto:rob.khasanov@gmail.com" target="_blank">rob.khasanov@gmail.com</a>> wrote:<br>
><br>
> Author: rkhasanov<br>
> Date: Tue Dec 9 12:45:30 2014<br>
> New Revision: 223804<br>
><br>
> URL: <a href="http://llvm.org/viewvc/llvm-project?rev=223804&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=223804&view=rev</a><br>
> Log:<br>
> [AVX512] Added lowering for VBROADCASTSS/SD instructions.<br>
> Lowering patterns were written through avx512_broadcast_pat multiclass as pattern generates VBROADCAST and COPY_TO_REGCLASS nodes.<br>
> Added lowering tests.<br>
><br>
><br>
> Modified:<br>
> llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
> llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=223804&r1=223803&r2=223804&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=223804&r1=223803&r2=223804&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Dec 9 12:45:30 2014<br>
> @@ -651,6 +651,44 @@ let ExeDomain = SSEPackedDouble in {<br>
> avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;<br>
> }<br>
><br>
> +// SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar<br>
> +// representations of source<br>
> +multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,<br>
> + X86VectorVTInfo _, RegisterClass SrcRC_v,<br>
> + RegisterClass SrcRC_s> {<br>
> + def : Pat<(_.VT (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src))),<br>
<br>
</div></div>You should able to fold the cast into X86VTVectorInfo.<br>
<span><br></span></blockquote></div></div><div>Yes, you are right. I'll fix it.</div><span class=""><div><br></div></span></div></div></div></blockquote><div>Fixed at rev 224122.<br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div dir="ltr"><div class="gmail_extra"><div class="gmail_quote"><span class=""><div></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><span>
> + (!cast<Instruction>(InstName##"r")<br>
> + (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;<br>
> +<br>
> + let AddedComplexity = 30 in {<br>
> + def : Pat<(_.VT (vselect _.KRCWM:$mask,<br>
> + (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),<br>
> + _.RC:$src0)),<br>
> + (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,<br>
> + (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;<br>
> +<br>
> + def : Pat<(_.VT(vselect _.KRCWM:$mask,<br>
> + (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),<br>
> + _.ImmAllZerosV)),<br>
> + (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,<br>
> + (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;<br>
> + }<br>
> +}<br>
<br>
</span>How do these relate to the ISel pattern in the instruction definition?<br>
<br></blockquote></span><div>ISel pattern in the instruction definition create broadcast instructions with 128-bit arguments. avx512_broadcast_pat introduces patterns with scalar argument (patterns were introduced in the same way as in AVX/AVX2). Later we can canonize broadcast instructions before ISel phase and eliminate these additional patterns on ISel.</div><div><br></div><div>Thanks,</div><div>Robert</div><div><div class="h5"><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
Thanks,<br>
Adam<br>
<div><div><br>
> +<br>
> +defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,<br>
> + VR128X, FR32X>;<br>
> +defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,<br>
> + VR128X, FR64X>;<br>
> +<br>
> +let Predicates = [HasVLX] in {<br>
> + defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,<br>
> + v8f32x_info, VR128X, FR32X>;<br>
> + defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,<br>
> + v4f32x_info, VR128X, FR32X>;<br>
> + defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,<br>
> + v4f64x_info, VR128X, FR64X>;<br>
> +}<br>
> +<br>
> def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),<br>
> (VBROADCASTSSZm addr:$src)>;<br>
> def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),<br>
><br>
> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=223804&r1=223803&r2=223804&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=223804&r1=223803&r2=223804&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Dec 9 12:45:30 2014<br>
> @@ -659,6 +659,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br>
> { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },<br>
> { X86::VPABSDZrr, X86::VPABSDZrm, 0 },<br>
> { X86::VPABSQZrr, X86::VPABSQZrm, 0 },<br>
> + { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },<br>
> // AVX-512 foldable instructions (256-bit versions)<br>
> { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },<br>
> { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },<br>
> @@ -670,6 +672,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br>
> { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },<br>
> { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },<br>
> { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },<br>
> + { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },<br>
> // AVX-512 foldable instructions (256-bit versions)<br>
> { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },<br>
> { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },<br>
> @@ -681,6 +685,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br>
> { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },<br>
> { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },<br>
> { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },<br>
> + { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },<br>
><br>
> // AES foldable instructions<br>
> { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },<br>
> @@ -1321,6 +1326,13 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br>
> { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },<br>
> { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },<br>
> { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },<br>
> + { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },<br>
> +<br>
> + // AVX-512{F,VL} foldable instructions<br>
> + { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },<br>
><br>
> // AES foldable instructions<br>
> { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },<br>
> @@ -1501,7 +1513,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br>
> { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },<br>
> { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },<br>
> { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },<br>
> - { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }<br>
> + { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },<br>
> + { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },<br>
> + { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE }<br>
> };<br>
><br>
> for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {<br>
><br>
> Modified: llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br>
> URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll?rev=223804&r1=223803&r2=223804&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll?rev=223804&r1=223803&r2=223804&view=diff</a><br>
> ==============================================================================<br>
> --- llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll (original)<br>
> +++ llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll Tue Dec 9 12:45:30 2014<br>
> @@ -20,6 +20,14 @@ define <8 x i64> @_inreg8xi64(i64 %a)<br>
> ret <8 x i64> %c<br>
> }<br>
><br>
> +;CHECK-LABEL: _ss16xfloat_v4<br>
> +;CHECK: vbroadcastss %xmm0, %zmm0<br>
> +;CHECK: ret<br>
> +define <16 x float> @_ss16xfloat_v4(<4 x float> %a) {<br>
> + %b = shufflevector <4 x float> %a, <4 x float> undef, <16 x i32> zeroinitializer<br>
> + ret <16 x float> %b<br>
> +}<br>
> +<br>
> define <16 x float> @_inreg16xfloat(float %a) {<br>
> ; CHECK-LABEL: _inreg16xfloat:<br>
> ; CHECK: ## BB#0:<br>
> @@ -30,6 +38,62 @@ define <16 x float> @_inreg16xfloat(fl<br>
> ret <16 x float> %c<br>
> }<br>
><br>
> +;CHECK-LABEL: _ss16xfloat_mask:<br>
> +;CHECK: vbroadcastss %xmm0, %zmm1 {%k1}<br>
> +;CHECK: ret<br>
> +define <16 x float> @_ss16xfloat_mask(float %a, <16 x float> %i, <16 x i32> %mask1) {<br>
> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <16 x float> undef, float %a, i32 0<br>
> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br>
> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> %i<br>
> + ret <16 x float> %r<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _ss16xfloat_maskz:<br>
> +;CHECK: vbroadcastss %xmm0, %zmm0 {%k1} {z}<br>
> +;CHECK: ret<br>
> +define <16 x float> @_ss16xfloat_maskz(float %a, <16 x i32> %mask1) {<br>
> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <16 x float> undef, float %a, i32 0<br>
> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br>
> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> zeroinitializer<br>
> + ret <16 x float> %r<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _ss16xfloat_load:<br>
> +;CHECK: vbroadcastss (%{{.*}}, %zmm<br>
> +;CHECK: ret<br>
> +define <16 x float> @_ss16xfloat_load(float* %a.ptr) {<br>
> + %a = load float* %a.ptr<br>
> + %b = insertelement <16 x float> undef, float %a, i32 0<br>
> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br>
> + ret <16 x float> %c<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _ss16xfloat_mask_load:<br>
> +;CHECK: vbroadcastss (%rdi), %zmm0 {%k1}<br>
> +;CHECK: ret<br>
> +define <16 x float> @_ss16xfloat_mask_load(float* %a.ptr, <16 x float> %i, <16 x i32> %mask1) {<br>
> + %a = load float* %a.ptr<br>
> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <16 x float> undef, float %a, i32 0<br>
> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br>
> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> %i<br>
> + ret <16 x float> %r<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _ss16xfloat_maskz_load:<br>
> +;CHECK: vbroadcastss (%rdi), %zmm0 {%k1} {z}<br>
> +;CHECK: ret<br>
> +define <16 x float> @_ss16xfloat_maskz_load(float* %a.ptr, <16 x i32> %mask1) {<br>
> + %a = load float* %a.ptr<br>
> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <16 x float> undef, float %a, i32 0<br>
> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br>
> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> zeroinitializer<br>
> + ret <16 x float> %r<br>
> +}<br>
> +<br>
> define <8 x double> @_inreg8xdouble(double %a) {<br>
> ; CHECK-LABEL: _inreg8xdouble:<br>
> ; CHECK: ## BB#0:<br>
> @@ -40,6 +104,62 @@ define <8 x double> @_inreg8xdouble(do<br>
> ret <8 x double> %c<br>
> }<br>
><br>
> +;CHECK-LABEL: _sd8xdouble_mask:<br>
> +;CHECK: vbroadcastsd %xmm0, %zmm1 {%k1}<br>
> +;CHECK: ret<br>
> +define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) {<br>
> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <8 x double> undef, double %a, i32 0<br>
> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br>
> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i<br>
> + ret <8 x double> %r<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _sd8xdouble_maskz:<br>
> +;CHECK: vbroadcastsd %xmm0, %zmm0 {%k1} {z}<br>
> +;CHECK: ret<br>
> +define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) {<br>
> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <8 x double> undef, double %a, i32 0<br>
> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br>
> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer<br>
> + ret <8 x double> %r<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _sd8xdouble_load:<br>
> +;CHECK: vbroadcastsd (%rdi), %zmm<br>
> +;CHECK: ret<br>
> +define <8 x double> @_sd8xdouble_load(double* %a.ptr) {<br>
> + %a = load double* %a.ptr<br>
> + %b = insertelement <8 x double> undef, double %a, i32 0<br>
> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br>
> + ret <8 x double> %c<br>
> +}<br>
> +<br>
> +;CHECK-LABEL: _sd8xdouble_mask_load:<br>
> +;CHECK: vbroadcastsd (%rdi), %zmm0 {%k1}<br>
> +;CHECK: ret<br>
> +define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) {<br>
> + %a = load double* %a.ptr<br>
> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <8 x double> undef, double %a, i32 0<br>
> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br>
> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i<br>
> + ret <8 x double> %r<br>
> +}<br>
> +<br>
> +define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) {<br>
> +; CHECK-LABEL: _sd8xdouble_maskz_load:<br>
> +; CHECK: vbroadcastsd (%rdi), %zmm0 {%k1} {z}<br>
> +; CHECK: ret<br>
> + %a = load double* %a.ptr<br>
> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br>
> + %b = insertelement <8 x double> undef, double %a, i32 0<br>
> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br>
> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer<br>
> + ret <8 x double> %r<br>
> +}<br>
> +<br>
> define <16 x i32> @_xmm16xi32(<16 x i32> %a) {<br>
> ; CHECK-LABEL: _xmm16xi32:<br>
> ; CHECK: ## BB#0:<br>
><br>
><br>
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<br>
</div></div></blockquote></div></div></div><br></div></div>
</blockquote></div><br></div></div>