<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Dec 12, 2014, at 6:22 AM, Robert Khasanov <<a href="mailto:rob.khasanov@gmail.com" class="">rob.khasanov@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><br class="Apple-interchange-newline"><br style="font-family: Helvetica; font-size: 10px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><div class="gmail_quote" style="font-family: Helvetica; font-size: 10px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;">2014-12-12 15:51 GMT+03:00 Robert Khasanov<span class="Apple-converted-space"> </span><span dir="ltr" class=""><<a href="mailto:rob.khasanov@gmail.com" target="_blank" class="">rob.khasanov@gmail.com</a>></span>:<br class=""><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;"><div dir="ltr" class="">Hi Adam,<br class=""><div class="gmail_extra"><br class=""><div class="gmail_quote"><div class=""><div class="h5">2014-12-10 9:38 GMT+03:00 Adam Nemet<span class="Apple-converted-space"> </span><span dir="ltr" class=""><<a href="mailto:anemet@apple.com" target="_blank" class="">anemet@apple.com</a>></span>:<br class=""><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;">Hi Robert,<br class=""><div class=""><div class=""><br class="">> On Dec 9, 2014, at 10:45 AM, Robert Khasanov <<a href="mailto:rob.khasanov@gmail.com" target="_blank" class="">rob.khasanov@gmail.com</a>> wrote:<br class="">><br class="">> Author: rkhasanov<br class="">> Date: Tue Dec 9 12:45:30 2014<br class="">> New Revision: 223804<br class="">><br class="">> URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project?rev=223804&view=rev" target="_blank" class="">http://llvm.org/viewvc/llvm-project?rev=223804&view=rev</a><br class="">> Log:<br class="">> [AVX512] Added lowering for VBROADCASTSS/SD instructions.<br class="">> Lowering patterns were written through avx512_broadcast_pat multiclass as pattern generates VBROADCAST and COPY_TO_REGCLASS nodes.<br class="">> Added lowering tests.<br class="">><br class="">><br class="">> Modified:<br class="">> llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br class="">> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br class="">> llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br class="">><br class="">> Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br class="">> URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=223804&r1=223803&r2=223804&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=223804&r1=223803&r2=223804&view=diff</a><br class="">> ==============================================================================<br class="">> --- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br class="">> +++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Dec 9 12:45:30 2014<br class="">> @@ -651,6 +651,44 @@ let ExeDomain = SSEPackedDouble in {<br class="">> avx512vl_f64_info>, VEX_W, EVEX_CD8<64, CD8VT1>;<br class="">> }<br class="">><br class="">> +// SrcRC_v and SrcRC_s are RegisterClasses for vector and scalar<br class="">> +// representations of source<br class="">> +multiclass avx512_broadcast_pat<string InstName, SDNode OpNode,<br class="">> + X86VectorVTInfo _, RegisterClass SrcRC_v,<br class="">> + RegisterClass SrcRC_s> {<br class="">> + def : Pat<(_.VT (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src))),<br class=""><br class=""></div></div>You should able to fold the cast into X86VTVectorInfo.<br class=""><span class=""><br class=""></span></blockquote></div></div><div class="">Yes, you are right. I'll fix it.</div><span class=""><div class=""><br class=""></div></span></div></div></div></blockquote><div class="">Fixed at rev 224122.<br class=""></div></div></div></blockquote><div><br class=""></div><div>Thanks.</div><br class=""><blockquote type="cite" class=""><div class=""><div class="gmail_quote" style="font-family: Helvetica; font-size: 10px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><div class=""> </div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;"><div dir="ltr" class=""><div class="gmail_extra"><div class="gmail_quote"><span class=""><div class=""></div><div class=""> </div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;"><span class="">> + (!cast<Instruction>(InstName##"r")<br class="">> + (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;<br class="">> +<br class="">> + let AddedComplexity = 30 in {<br class="">> + def : Pat<(_.VT (vselect _.KRCWM:$mask,<br class="">> + (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),<br class="">> + _.RC:$src0)),<br class="">> + (!cast<Instruction>(InstName##"rk") _.RC:$src0, _.KRCWM:$mask,<br class="">> + (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;<br class="">> +<br class="">> + def : Pat<(_.VT(vselect _.KRCWM:$mask,<br class="">> + (OpNode (!cast<ValueType>(_.EltTypeName) SrcRC_s:$src)),<br class="">> + _.ImmAllZerosV)),<br class="">> + (!cast<Instruction>(InstName##"rkz") _.KRCWM:$mask,<br class="">> + (COPY_TO_REGCLASS SrcRC_s:$src, SrcRC_v))>;<br class="">> + }<br class="">> +}<br class=""><br class=""></span>How do these relate to the ISel pattern in the instruction definition?<br class=""><br class=""></blockquote></span><div class="">ISel pattern in the instruction definition create broadcast instructions with 128-bit arguments. avx512_broadcast_pat introduces patterns with scalar argument (patterns were introduced in the same way as in AVX/AVX2). Later we can canonize broadcast instructions before ISel phase and eliminate these additional patterns on ISel.</div></div></div></div></blockquote></div></div></blockquote><div><br class=""></div><div>Thanks for the clarification. Should we add a comment about this?</div><div><br class=""></div><div>Adam</div><br class=""><blockquote type="cite" class=""><div class=""><div class="gmail_quote" style="font-family: Helvetica; font-size: 10px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;"><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;"><div dir="ltr" class=""><div class="gmail_extra"><div class="gmail_quote"><div class=""><br class=""></div><div class="">Thanks,</div><div class="">Robert</div><div class=""><div class="h5"><div class=""> </div><blockquote class="gmail_quote" style="margin: 0px 0px 0px 0.8ex; border-left-width: 1px; border-left-color: rgb(204, 204, 204); border-left-style: solid; padding-left: 1ex;">Thanks,<br class="">Adam<br class=""><div class=""><div class=""><br class="">> +<br class="">> +defm : avx512_broadcast_pat<"VBROADCASTSSZ", X86VBroadcast, v16f32_info,<br class="">> + VR128X, FR32X>;<br class="">> +defm : avx512_broadcast_pat<"VBROADCASTSDZ", X86VBroadcast, v8f64_info,<br class="">> + VR128X, FR64X>;<br class="">> +<br class="">> +let Predicates = [HasVLX] in {<br class="">> + defm : avx512_broadcast_pat<"VBROADCASTSSZ256", X86VBroadcast,<br class="">> + v8f32x_info, VR128X, FR32X>;<br class="">> + defm : avx512_broadcast_pat<"VBROADCASTSSZ128", X86VBroadcast,<br class="">> + v4f32x_info, VR128X, FR32X>;<br class="">> + defm : avx512_broadcast_pat<"VBROADCASTSDZ256", X86VBroadcast,<br class="">> + v4f64x_info, VR128X, FR64X>;<br class="">> +}<br class="">> +<br class="">> def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),<br class="">> (VBROADCASTSSZm addr:$src)>;<br class="">> def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),<br class="">><br class="">> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br class="">> URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=223804&r1=223803&r2=223804&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=223804&r1=223803&r2=223804&view=diff</a><br class="">> ==============================================================================<br class="">> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br class="">> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Dec 9 12:45:30 2014<br class="">> @@ -659,6 +659,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class="">> { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },<br class="">> { X86::VPABSDZrr, X86::VPABSDZrm, 0 },<br class="">> { X86::VPABSQZrr, X86::VPABSQZrm, 0 },<br class="">> + { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },<br class="">> // AVX-512 foldable instructions (256-bit versions)<br class="">> { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },<br class="">> { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },<br class="">> @@ -670,6 +672,8 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class="">> { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },<br class="">> { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },<br class="">> { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },<br class="">> + { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },<br class="">> // AVX-512 foldable instructions (256-bit versions)<br class="">> { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },<br class="">> { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },<br class="">> @@ -681,6 +685,7 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class="">> { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },<br class="">> { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },<br class="">> { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },<br class="">> + { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },<br class="">><br class="">> // AES foldable instructions<br class="">> { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },<br class="">> @@ -1321,6 +1326,13 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class="">> { X86::VALIGNQrri, X86::VALIGNQrmi, 0 },<br class="">> { X86::VALIGNDrri, X86::VALIGNDrmi, 0 },<br class="">> { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },<br class="">> + { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },<br class="">> +<br class="">> + // AVX-512{F,VL} foldable instructions<br class="">> + { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },<br class="">><br class="">> // AES foldable instructions<br class="">> { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },<br class="">> @@ -1501,7 +1513,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget<br class="">> { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },<br class="">> { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },<br class="">> { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },<br class="">> - { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 }<br class="">> + { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },<br class="">> + { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },<br class="">> + { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE }<br class="">> };<br class="">><br class="">> for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {<br class="">><br class="">> Modified: llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br class="">> URL:<span class="Apple-converted-space"> </span><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll?rev=223804&r1=223803&r2=223804&view=diff" target="_blank" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll?rev=223804&r1=223803&r2=223804&view=diff</a><br class="">> ==============================================================================<br class="">> --- llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll (original)<br class="">> +++ llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll Tue Dec 9 12:45:30 2014<br class="">> @@ -20,6 +20,14 @@ define <8 x i64> @_inreg8xi64(i64 %a)<br class="">> ret <8 x i64> %c<br class="">> }<br class="">><br class="">> +;CHECK-LABEL: _ss16xfloat_v4<br class="">> +;CHECK: vbroadcastss %xmm0, %zmm0<br class="">> +;CHECK: ret<br class="">> +define <16 x float> @_ss16xfloat_v4(<4 x float> %a) {<br class="">> + %b = shufflevector <4 x float> %a, <4 x float> undef, <16 x i32> zeroinitializer<br class="">> + ret <16 x float> %b<br class="">> +}<br class="">> +<br class="">> define <16 x float> @_inreg16xfloat(float %a) {<br class="">> ; CHECK-LABEL: _inreg16xfloat:<br class="">> ; CHECK: ## BB#0:<br class="">> @@ -30,6 +38,62 @@ define <16 x float> @_inreg16xfloat(fl<br class="">> ret <16 x float> %c<br class="">> }<br class="">><br class="">> +;CHECK-LABEL: _ss16xfloat_mask:<br class="">> +;CHECK: vbroadcastss %xmm0, %zmm1 {%k1}<br class="">> +;CHECK: ret<br class="">> +define <16 x float> @_ss16xfloat_mask(float %a, <16 x float> %i, <16 x i32> %mask1) {<br class="">> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <16 x float> undef, float %a, i32 0<br class="">> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br class="">> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> %i<br class="">> + ret <16 x float> %r<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _ss16xfloat_maskz:<br class="">> +;CHECK: vbroadcastss %xmm0, %zmm0 {%k1} {z}<br class="">> +;CHECK: ret<br class="">> +define <16 x float> @_ss16xfloat_maskz(float %a, <16 x i32> %mask1) {<br class="">> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <16 x float> undef, float %a, i32 0<br class="">> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br class="">> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> zeroinitializer<br class="">> + ret <16 x float> %r<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _ss16xfloat_load:<br class="">> +;CHECK: vbroadcastss (%{{.*}}, %zmm<br class="">> +;CHECK: ret<br class="">> +define <16 x float> @_ss16xfloat_load(float* %a.ptr) {<br class="">> + %a = load float* %a.ptr<br class="">> + %b = insertelement <16 x float> undef, float %a, i32 0<br class="">> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br class="">> + ret <16 x float> %c<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _ss16xfloat_mask_load:<br class="">> +;CHECK: vbroadcastss (%rdi), %zmm0 {%k1}<br class="">> +;CHECK: ret<br class="">> +define <16 x float> @_ss16xfloat_mask_load(float* %a.ptr, <16 x float> %i, <16 x i32> %mask1) {<br class="">> + %a = load float* %a.ptr<br class="">> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <16 x float> undef, float %a, i32 0<br class="">> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br class="">> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> %i<br class="">> + ret <16 x float> %r<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _ss16xfloat_maskz_load:<br class="">> +;CHECK: vbroadcastss (%rdi), %zmm0 {%k1} {z}<br class="">> +;CHECK: ret<br class="">> +define <16 x float> @_ss16xfloat_maskz_load(float* %a.ptr, <16 x i32> %mask1) {<br class="">> + %a = load float* %a.ptr<br class="">> + %mask = icmp ne <16 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <16 x float> undef, float %a, i32 0<br class="">> + %c = shufflevector <16 x float> %b, <16 x float> undef, <16 x i32> zeroinitializer<br class="">> + %r = select <16 x i1> %mask, <16 x float> %c, <16 x float> zeroinitializer<br class="">> + ret <16 x float> %r<br class="">> +}<br class="">> +<br class="">> define <8 x double> @_inreg8xdouble(double %a) {<br class="">> ; CHECK-LABEL: _inreg8xdouble:<br class="">> ; CHECK: ## BB#0:<br class="">> @@ -40,6 +104,62 @@ define <8 x double> @_inreg8xdouble(do<br class="">> ret <8 x double> %c<br class="">> }<br class="">><br class="">> +;CHECK-LABEL: _sd8xdouble_mask:<br class="">> +;CHECK: vbroadcastsd %xmm0, %zmm1 {%k1}<br class="">> +;CHECK: ret<br class="">> +define <8 x double> @_sd8xdouble_mask(double %a, <8 x double> %i, <8 x i32> %mask1) {<br class="">> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <8 x double> undef, double %a, i32 0<br class="">> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br class="">> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i<br class="">> + ret <8 x double> %r<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _sd8xdouble_maskz:<br class="">> +;CHECK: vbroadcastsd %xmm0, %zmm0 {%k1} {z}<br class="">> +;CHECK: ret<br class="">> +define <8 x double> @_sd8xdouble_maskz(double %a, <8 x i32> %mask1) {<br class="">> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <8 x double> undef, double %a, i32 0<br class="">> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br class="">> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer<br class="">> + ret <8 x double> %r<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _sd8xdouble_load:<br class="">> +;CHECK: vbroadcastsd (%rdi), %zmm<br class="">> +;CHECK: ret<br class="">> +define <8 x double> @_sd8xdouble_load(double* %a.ptr) {<br class="">> + %a = load double* %a.ptr<br class="">> + %b = insertelement <8 x double> undef, double %a, i32 0<br class="">> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br class="">> + ret <8 x double> %c<br class="">> +}<br class="">> +<br class="">> +;CHECK-LABEL: _sd8xdouble_mask_load:<br class="">> +;CHECK: vbroadcastsd (%rdi), %zmm0 {%k1}<br class="">> +;CHECK: ret<br class="">> +define <8 x double> @_sd8xdouble_mask_load(double* %a.ptr, <8 x double> %i, <8 x i32> %mask1) {<br class="">> + %a = load double* %a.ptr<br class="">> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <8 x double> undef, double %a, i32 0<br class="">> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br class="">> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> %i<br class="">> + ret <8 x double> %r<br class="">> +}<br class="">> +<br class="">> +define <8 x double> @_sd8xdouble_maskz_load(double* %a.ptr, <8 x i32> %mask1) {<br class="">> +; CHECK-LABEL: _sd8xdouble_maskz_load:<br class="">> +; CHECK: vbroadcastsd (%rdi), %zmm0 {%k1} {z}<br class="">> +; CHECK: ret<br class="">> + %a = load double* %a.ptr<br class="">> + %mask = icmp ne <8 x i32> %mask1, zeroinitializer<br class="">> + %b = insertelement <8 x double> undef, double %a, i32 0<br class="">> + %c = shufflevector <8 x double> %b, <8 x double> undef, <8 x i32> zeroinitializer<br class="">> + %r = select <8 x i1> %mask, <8 x double> %c, <8 x double> zeroinitializer<br class="">> + ret <8 x double> %r<br class="">> +}<br class="">> +<br class="">> define <16 x i32> @_xmm16xi32(<16 x i32> %a) {<br class="">> ; CHECK-LABEL: _xmm16xi32:<br class="">> ; CHECK: ## BB#0:<br class="">><br class="">><br class="">> _______________________________________________<br class="">> llvm-commits mailing list<br class="">><span class="Apple-converted-space"> </span><a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank" class="">llvm-commits@cs.uiuc.edu</a><br class="">><span class="Apple-converted-space"> </span><a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank" class="">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a></div></div></blockquote></div></div></div></div></div></blockquote></div></div></blockquote></div><br class=""></body></html>