Excellent! Well done!<br><br>-eric<br><br><div class="gmail_quote">On Thu Dec 11 2014 at 11:49:02 AM Matthias Braun <<a href="mailto:matze@braunis.de">matze@braunis.de</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: matze<br>
Date: Thu Dec 11 13:42:09 2014<br>
New Revision: 224043<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=224043&view=rev" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project?rev=224043&view=rev</a><br>
Log:<br>
Enable machineverifier in debug mode for X86, ARM, AArch64, Mips<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/<u></u>AArch64TargetMachine.cpp<br>
llvm/trunk/lib/Target/ARM/<u></u>ARMTargetMachine.cpp<br>
llvm/trunk/lib/Target/Mips/<u></u>MipsTargetMachine.cpp<br>
llvm/trunk/lib/Target/X86/<u></u>X86TargetMachine.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/<u></u>AArch64TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=224043&r1=224042&r2=224043&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>AArch64/AArch64TargetMachine.<u></u>cpp?rev=224043&r1=224042&r2=<u></u>224043&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/AArch64/<u></u>AArch64TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/<u></u>AArch64TargetMachine.cpp Thu Dec 11 13:42:09 2014<br>
@@ -270,7 +270,7 @@ bool AArch64PassConfig::addILPOpts(<u></u>) {<br>
void AArch64PassConfig::<u></u>addPreRegAlloc() {<br>
// Use AdvSIMD scalar instructions whenever profitable.<br>
if (TM->getOptLevel() != CodeGenOpt::None && EnableAdvSIMDScalar) {<br>
- addPass(<u></u>createAArch64AdvSIMDScalar(), false);<br>
+ addPass(<u></u>createAArch64AdvSIMDScalar());<br>
// The AdvSIMD pass may produce copies that can be rewritten to<br>
// be register coaleascer friendly.<br>
addPass(&PeepholeOptimizerID);<br>
@@ -280,7 +280,7 @@ void AArch64PassConfig::<u></u>addPreRegAlloc()<br>
void AArch64PassConfig::<u></u>addPostRegAlloc() {<br>
// Change dead register definitions to refer to the zero register.<br>
if (TM->getOptLevel() != CodeGenOpt::None && EnableDeadRegisterElimination)<br>
- addPass(<u></u>createAArch64DeadRegisterDefin<u></u>itions(), false);<br>
+ addPass(<u></u>createAArch64DeadRegisterDefin<u></u>itions());<br>
if (TM->getOptLevel() != CodeGenOpt::None &&<br>
(TM->getSubtarget<<u></u>AArch64Subtarget>().<u></u>isCortexA53() ||<br>
TM->getSubtarget<<u></u>AArch64Subtarget>().<u></u>isCortexA57()) &&<br>
@@ -291,7 +291,7 @@ void AArch64PassConfig::<u></u>addPostRegAlloc(<br>
<br>
void AArch64PassConfig::<u></u>addPreSched2() {<br>
// Expand some pseudo instructions to allow proper scheduling.<br>
- addPass(<u></u>createAArch64ExpandPseudoPass(<u></u>), false);<br>
+ addPass(<u></u>createAArch64ExpandPseudoPass(<u></u>));<br>
// Use load/store pair instructions when possible.<br>
if (TM->getOptLevel() != CodeGenOpt::None && EnableLoadStoreOpt)<br>
addPass(<u></u>createAArch64LoadStoreOptimiza<u></u>tionPass());<br>
@@ -299,10 +299,10 @@ void AArch64PassConfig::<u></u>addPreSched2() {<br>
<br>
void AArch64PassConfig::<u></u>addPreEmitPass() {<br>
if (EnableA53Fix835769)<br>
- addPass(<u></u>createAArch64A53Fix835769(), false);<br>
+ addPass(<u></u>createAArch64A53Fix835769());<br>
// Relax conditional branch instructions if they're otherwise out of<br>
// range of their destination.<br>
- addPass(<u></u>createAArch64BranchRelaxation(<u></u>), false);<br>
+ addPass(<u></u>createAArch64BranchRelaxation(<u></u>));<br>
if (TM->getOptLevel() != CodeGenOpt::None && EnableCollectLOH &&<br>
TM->getSubtarget<<u></u>AArch64Subtarget>().<u></u>isTargetMachO())<br>
addPass(<u></u>createAArch64CollectLOHPass())<u></u>;<br>
<br>
Modified: llvm/trunk/lib/Target/ARM/<u></u>ARMTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=224043&r1=224042&r2=224043&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>ARM/ARMTargetMachine.cpp?rev=<u></u>224043&r1=224042&r2=224043&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/ARM/<u></u>ARMTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/ARM/<u></u>ARMTargetMachine.cpp Thu Dec 11 13:42:09 2014<br>
@@ -243,9 +243,9 @@ bool ARMPassConfig::<u></u>addInstSelector() {<br>
<br>
void ARMPassConfig::addPreRegAlloc(<u></u>) {<br>
if (getOptLevel() != CodeGenOpt::None)<br>
- addPass(<u></u>createARMLoadStoreOptimization<u></u>Pass(true), false);<br>
+ addPass(<u></u>createARMLoadStoreOptimization<u></u>Pass(true));<br>
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA9()<u></u>)<br>
- addPass(<u></u>createMLxExpansionPass(), false);<br>
+ addPass(<u></u>createMLxExpansionPass());<br>
// Since the A15SDOptimizer pass can insert VDUP instructions, it can only be<br>
// enabled when NEON is available.<br>
if (getOptLevel() != CodeGenOpt::None && getARMSubtarget().isCortexA15(<u></u>) &&<br>
@@ -256,23 +256,23 @@ void ARMPassConfig::addPreRegAlloc(<u></u>) {<br>
<br>
void ARMPassConfig::addPreSched2() {<br>
if (getOptLevel() != CodeGenOpt::None) {<br>
- addPass(<u></u>createARMLoadStoreOptimization<u></u>Pass(), false);<br>
+ addPass(<u></u>createARMLoadStoreOptimization<u></u>Pass());<br>
<br>
if (getARMSubtarget().hasNEON())<br>
- addPass(<u></u>createExecutionDependencyFixPa<u></u>ss(&ARM::DPRRegClass), false);<br>
+ addPass(<u></u>createExecutionDependencyFixPa<u></u>ss(&ARM::DPRRegClass));<br>
}<br>
<br>
// Expand some pseudo instructions into multiple instructions to allow<br>
// proper scheduling.<br>
- addPass(<u></u>createARMExpandPseudoPass(), false);<br>
+ addPass(<u></u>createARMExpandPseudoPass());<br>
<br>
if (getOptLevel() != CodeGenOpt::None) {<br>
if (!getARMSubtarget().<u></u>isThumb1Only()) {<br>
// in v8, IfConversion depends on Thumb instruction widths<br>
if (getARMSubtarget().restrictIT(<u></u>) &&<br>
!getARMSubtarget().<u></u>prefers32BitThumb())<br>
- addPass(<u></u>createThumb2SizeReductionPass(<u></u>), false);<br>
- addPass(&IfConverterID, false);<br>
+ addPass(<u></u>createThumb2SizeReductionPass(<u></u>));<br>
+ addPass(&IfConverterID);<br>
}<br>
}<br>
if (getARMSubtarget().isThumb2())<br>
@@ -282,12 +282,12 @@ void ARMPassConfig::addPreSched2() {<br>
void ARMPassConfig::addPreEmitPass(<u></u>) {<br>
if (getARMSubtarget().isThumb2()) {<br>
if (!getARMSubtarget().<u></u>prefers32BitThumb())<br>
- addPass(<u></u>createThumb2SizeReductionPass(<u></u>), false);<br>
+ addPass(<u></u>createThumb2SizeReductionPass(<u></u>));<br>
<br>
// Constant island pass work on unbundled instructions.<br>
- addPass(&<u></u>UnpackMachineBundlesID, false);<br>
+ addPass(&<u></u>UnpackMachineBundlesID);<br>
}<br>
<br>
- addPass(<u></u>createARMOptimizeBarriersPass(<u></u>), false);<br>
+ addPass(<u></u>createARMOptimizeBarriersPass(<u></u>));<br>
addPass(<u></u>createARMConstantIslandPass())<u></u>;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/<u></u>MipsTargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=224043&r1=224042&r2=224043&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>Mips/MipsTargetMachine.cpp?<u></u>rev=224043&r1=224042&r2=<u></u>224043&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/Mips/<u></u>MipsTargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/<u></u>MipsTargetMachine.cpp Thu Dec 11 13:42:09 2014<br>
@@ -226,7 +226,7 @@ void MipsTargetMachine::<u></u>addAnalysisPasse<br>
// print out the code after the passes.<br>
void MipsPassConfig::<u></u>addPreEmitPass() {<br>
MipsTargetMachine &TM = getMipsTargetMachine();<br>
- addPass(<u></u>createMipsDelaySlotFillerPass(<u></u>TM), false);<br>
- addPass(<u></u>createMipsLongBranchPass(TM), false);<br>
+ addPass(<u></u>createMipsDelaySlotFillerPass(<u></u>TM));<br>
+ addPass(<u></u>createMipsLongBranchPass(TM));<br>
addPass(<u></u>createMipsConstantIslandPass(<u></u>TM));<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=224043&r1=224042&r2=224043&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>X86/X86TargetMachine.cpp?rev=<u></u>224043&r1=224042&r2=224043&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86TargetMachine.cpp Thu Dec 11 13:42:09 2014<br>
@@ -193,13 +193,13 @@ void X86PassConfig::<u></u>addPostRegAlloc() {<br>
<br>
void X86PassConfig::addPreEmitPass(<u></u>) {<br>
if (getOptLevel() != CodeGenOpt::None && getX86Subtarget().hasSSE2())<br>
- addPass(<u></u>createExecutionDependencyFixPa<u></u>ss(&X86::VR128RegClass), false);<br>
+ addPass(<u></u>createExecutionDependencyFixPa<u></u>ss(&X86::VR128RegClass));<br>
<br>
if (UseVZeroUpper)<br>
- addPass(<u></u>createX86IssueVZeroUpperPass()<u></u>, false);<br>
+ addPass(<u></u>createX86IssueVZeroUpperPass()<u></u>);<br>
<br>
if (getOptLevel() != CodeGenOpt::None) {<br>
- addPass(<u></u>createX86PadShortFunctions(), false);<br>
+ addPass(<u></u>createX86PadShortFunctions());<br>
addPass(createX86FixupLEAs());<br>
}<br>
}<br>
<br>
<br>
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</blockquote></div>