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<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Ok, thanks for checking.<o:p></o:p></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Feel free to CC me on the new PR.<o:p></o:p></span></p>
<p class="MsoNormal"><a name="_MailEndCompose"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"><o:p> </o:p></span></a></p>
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<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Quentin Colombet [mailto:qcolombet@apple.com]
<br>
<b>Sent:</b> Monday, December 08, 2014 23:46<br>
<b>To:</b> Kuperstein, Michael M<br>
<b>Cc:</b> Commit Messages and Patches for LLVM<br>
<b>Subject:</b> Re: [llvm] r223360 - [X86] Improve a dag-combine that handles a vector extract -> zext sequence.<o:p></o:p></span></p>
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<p class="MsoNormal">On Dec 8, 2014, at 1:10 PM, Quentin Colombet <<a href="mailto:qcolombet@apple.com">qcolombet@apple.com</a>> wrote:<o:p></o:p></p>
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On Dec 4, 2014, at 11:10 AM, Quentin Colombet <<a href="mailto:qcolombet@apple.com">qcolombet@apple.com</a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Hi,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">On Dec 4, 2014, at 9:19 AM, Chandler Carruth <<a href="mailto:chandlerc@google.com">chandlerc@google.com</a>> wrote:<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><br>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">On Thu, Dec 4, 2014 at 9:05 AM, Kuperstein, Michael M<span class="apple-converted-space"> </span><<a href="mailto:michael.m.kuperstein@intel.com" target="_blank">michael.m.kuperstein@intel.com</a>><span class="apple-converted-space"> </span>wrote:<o:p></o:p></span></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">It looks like in the cited PR it was the best sequence, but I agree with you, it may not be the case
globally.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Which stalls are you talking about? I think domain crossing shouldn’t be a problem in this case,
as the zexts would imply you want to be in the integer domain.</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">The domain cross as I understand it (and feel free to shed more detailed light on this aspect of Intel chips if you can, but I've failed to get any better clarification
from Intel folks in the past) is more problematic than that.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">It stems from separate execution units of some form (which form, and whether the "ports" as described in modern Intel manuals attach to them or are fixed to them isn't really
important). Moving data in a register from one unit to the other unit stalls. This is just as true (if not more true) moving data from an integer xmm register into a gpr as it is moving data produced in the floating point vector unit to an input of an integer
vector unit instruction.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Previously, the *primary* cause of vector shuffle performance problems in the x86 backend was because it heavily relied on pextr and pinsr sequences to manually extract
and insert the elements into the desired positions. But the slow downs were vastly out of proportion to the number of instructions different. The best explanation, and one supported by various timings indications in Agners and elsewhere, is that there is a
rather massive penalty incurred in sequences of these instructions. In my benchmarking, I routinely saw this penalty be much higher than that of domain crossing between integer and floating point units on Intel chips. On AMD chips, the penalties were more
even, but were also both significantly higher than on Intel chips.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regarding systematic testing – no, since this is a fairly specific pattern.</span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Do you have any examples in mind that will match this, but be negatively impacted?</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">I would start off with checking LNT, maybe SPEC (although I'm loath to trust SPEC numbers for this kind of change).<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""> <o:p></o:p></span></p>
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<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D"> </span><o:p></o:p></p>
<p class="MsoNormal" style="mso-margin-top-alt:auto;mso-margin-bottom-alt:auto"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1F497D">Regarding patterns impacted by this - if I understand correctly, the pattern that this was introduced
to catch was precisely the one the LIT test checks – 64-bit GEPs that use indexes extracted from a 4xi32 vector. There’s a rdar linked to the test. Quentin, do you think it’s worth checking what the impact of this is on the original issue?</span><o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">I’ll have a look at the original radar and I’ll let you know.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">This transformation implies a 1% regression there.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">I am not sure if this is the transformation itself or if it uncovers a poor codegen for some shuffle.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Indeed, in this specific example, instead of having vpextr + 1 mov from XMM to GPR, we have a vpshuf + 2 mov from XMM to GPR.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Trying to produce a reduce test case.<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Well in fact the vpextr vs. vpshuf is irrelevant here.<o:p></o:p></p>
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<p class="MsoNormal">The problem is a bad scheduling / register allocation where we end up with two useless moves.<o:p></o:p></p>
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<p class="MsoNormal">Manually fixing that actually improves the code by about 1%.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The problem in that case is that we generate:<o:p></o:p></p>
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<p class="MsoNormal">res1 = extr/mov XMM<o:p></o:p></p>
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<p class="MsoNormal">res2 = COPY res1<o:p></o:p></p>
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<p class="MsoNormal">res2 = res2 >> 32<o:p></o:p></p>
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<p class="MsoNormal">res3 = sext res1<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">The copy is useless and we can get rid of it by rewriting the code like this:<o:p></o:p></p>
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<p class="MsoNormal">res1 = extr/mov XMM<o:p></o:p></p>
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<p class="MsoNormal">res2 = COPY res1<o:p></o:p></p>
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<p class="MsoNormal">res3 = sext res1<o:p></o:p></p>
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<p class="MsoNormal">res2 = res2 >> 32<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Now the copy becomes coalesceable:<o:p></o:p></p>
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<p class="MsoNormal">res2 = extr/mov XMM<o:p></o:p></p>
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<p class="MsoNormal">res3 = sext res2<o:p></o:p></p>
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<p class="MsoNormal">res2 = res2 >> 32<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Therefore the new lowering is indeed better. I will see if I can produce a reduced test case to file a PR.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Thanks Michael. Go ahead and close the PR.<o:p></o:p></p>
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<p class="MsoNormal"><o:p> </o:p></p>
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<p class="MsoNormal">Q.<o:p></o:p></p>
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<p class="MsoNormal"><br>
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<o:p></o:p></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Cheers,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Q.<o:p></o:p></span></p>
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<o:p></o:p></span></p>
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<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">This also might be uncovered by checking the LNT results.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">All this said, I'm not certain of anything here. Maybe this is a strict win. I just think it needs more broad measurements than the PR shows.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">I agree with Chandler and in fact I thought that has been done. Therefore, by all means, please do performance measurements.<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif""><o:p> </o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Thanks,<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:9.0pt;font-family:"Helvetica","sans-serif"">Q.<o:p></o:p></span></p>
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