<div dir="ltr">Hi Cameron,<div><br></div><div>Thanks for this patch. Sorry for delay on review, I was in the hospital last weeks.</div></div><div class="gmail_extra"><br><div class="gmail_quote">2014-11-25 23:41 GMT+03:00 Cameron McInally <span dir="ltr"><<a href="mailto:cameron.mcinally@nyu.edu" target="_blank">cameron.mcinally@nyu.edu</a>></span>:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: mcinally<br>
Date: Tue Nov 25 14:41:51 2014<br>
New Revision: 222786<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=222786&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=222786&view=rev</a><br>
Log:<br>
[AVX512] Add 512b integer shift by variable intrinsics and patterns.<br>
<br>
Modified:<br>
llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
<br>
Modified: llvm/trunk/include/llvm/IR/IntrinsicsX86.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=222786&r1=222785&r2=222786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/IntrinsicsX86.td?rev=222786&r1=222785&r2=222786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/include/llvm/IR/IntrinsicsX86.td (original)<br>
+++ llvm/trunk/include/llvm/IR/IntrinsicsX86.td Tue Nov 25 14:41:51 2014<br>
@@ -1603,6 +1603,25 @@ let TargetPrefix = "x86" in { // All in<br>
def int_x86_avx512_mask_psrai_q : GCCBuiltin<"__builtin_ia32_psraqi512">,<br>
Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
llvm_i32_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
+<br>
+ def int_x86_avx512_mask_psll_d : GCCBuiltin<"__builtin_ia32_pslld512_mask">,<br>
+ Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,<br>
+ llvm_v4i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_psll_q : GCCBuiltin<"__builtin_ia32_psllq512_mask">,<br>
+ Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
+ llvm_v2i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_psrl_d : GCCBuiltin<"__builtin_ia32_psrld512_mask">,<br>
+ Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,<br>
+ llvm_v4i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_psrl_q : GCCBuiltin<"__builtin_ia32_psrlq512_mask">,<br>
+ Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
+ llvm_v2i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_psra_d : GCCBuiltin<"__builtin_ia32_psrad512_mask">,<br>
+ Intrinsic<[llvm_v16i32_ty], [llvm_v16i32_ty,<br>
+ llvm_v4i32_ty, llvm_v16i32_ty, llvm_i16_ty], [IntrNoMem]>;<br>
+ def int_x86_avx512_mask_psra_q : GCCBuiltin<"__builtin_ia32_psraq512_mask">,<br>
+ Intrinsic<[llvm_v8i64_ty], [llvm_v8i64_ty,<br>
+ llvm_v2i64_ty, llvm_v8i64_ty, llvm_i8_ty], [IntrNoMem]>;<br>
}<br>
<br>
// Pack ops.<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=222786&r1=222785&r2=222786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=222786&r1=222785&r2=222786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Nov 25 14:41:51 2014<br>
@@ -16872,7 +16872,11 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
RoundingMode),<br>
Mask, Src0, Subtarget, DAG);<br>
}<br>
-<br>
+ case INTR_TYPE_2OP_MASK: {<br>
+ return getVectorMaskingNode(DAG.getNode(IntrData->Opc0, dl, VT, Op.getOperand(1),<br>
+ Op.getOperand(2)),<br>
+ Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);<br>
+ }<br>
case CMP_MASK:<br>
case CMP_MASK_CC: {<br>
// Comparison intrinsics with masks.<br>
@@ -16924,7 +16928,7 @@ static SDValue LowerINTRINSIC_WO_CHAIN(S<br>
case VSHIFT_MASK:<br>
return getVectorMaskingNode(getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),<br>
Op.getOperand(1), Op.getOperand(2), DAG),<br>
- Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);;<br>
+ Op.getOperand(4), Op.getOperand(3), Subtarget, DAG);<br>
default:<br>
break;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=222786&r1=222785&r2=222786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=222786&r1=222785&r2=222786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Tue Nov 25 14:41:51 2014<br>
@@ -3196,6 +3196,7 @@ def : Pat <(i16 (int_x86_avx512_mask_pte<br>
def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),<br>
(v8i64 VR512:$src2), (i8 -1))),<br>
(COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;<br>
+<br>
//===----------------------------------------------------------------------===//<br>
// AVX-512 Shift instructions<br>
//===----------------------------------------------------------------------===//<br>
@@ -3214,73 +3215,57 @@ multiclass avx512_shift_rmi<bits<8> opc,<br>
}<br>
<br>
multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
- RegisterClass RC, ValueType vt, ValueType SrcVT,<br>
- PatFrag bc_frag, RegisterClass KRC> {<br>
- // src2 is always 128-bit<br>
- def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),<br>
- (ins RC:$src1, VR128X:$src2),<br>
- !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
- [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],<br>
- SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;<br>
- def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),<br>
- (ins KRC:$mask, RC:$src1, VR128X:$src2),<br>
- !strconcat(OpcodeStr,<br>
- "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),<br>
- [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;<br>
- def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),<br>
- (ins RC:$src1, i128mem:$src2),<br>
- !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),<br>
- [(set RC:$dst, (vt (OpNode RC:$src1,<br>
- (bc_frag (memopv2i64 addr:$src2)))))],<br>
- SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;<br>
- def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),<br>
- (ins KRC:$mask, RC:$src1, i128mem:$src2),<br>
- !strconcat(OpcodeStr,<br>
- "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),<br>
- [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;<br>
+ ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {<br>
+ // src2 is always 128-bit<br>
+ defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),<br>
+ (ins _.RC:$src1, VR128X:$src2), OpcodeStr,<br>
+ "$src2, $src1", "$src1, $src2",<br>
+ (_.VT (OpNode _.RC:$src1, (SrcVT VR128X:$src2))),<br>
+ " ", SSE_INTSHIFT_ITINS_P.rr>, AVX512BIBase, EVEX_4V;<br>
+ defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),<br>
+ (ins _.RC:$src1, i128mem:$src2), OpcodeStr,<br>
+ "$src2, $src1", "$src1, $src2",<br>
+ (_.VT (OpNode _.RC:$src1, (bc_frag (memopv2i64 addr:$src2)))),<br>
+ " ", SSE_INTSHIFT_ITINS_P.rm>, AVX512BIBase, EVEX_4V;<br>
+}<br>
+<br>
+multiclass avx512_varshift_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,<br>
+ ValueType SrcVT, PatFrag bc_frag, X86VectorVTInfo _> {<br>
+ defm Z : avx512_shift_rrm<opc, OpcodeStr, OpNode, SrcVT, bc_frag, _>, EVEX_V512;<br>
+}<br>
+<br>
+multiclass avx512_varshift_types<bits<8> opcd, bits<8> opcq, string OpcodeStr,<br>
+ SDNode OpNode> {<br>
+ defm D : avx512_varshift_sizes<opcd, OpcodeStr#"d", OpNode, v4i32, bc_v4i32,<br>
+ v16i32_info>, EVEX_CD8<32, CD8VQ>;<br>
+ defm Q : avx512_varshift_sizes<opcq, OpcodeStr#"q", OpNode, v2i64, bc_v2i64,<br>
+ v8i64_info>, EVEX_CD8<64, CD8VQ>, VEX_W;<br>
}<br>
<br>
defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,<br>
v16i32_info>,<br>
EVEX_V512, EVEX_CD8<32, CD8VF>;<br>
-defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,<br>
- VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,<br>
- EVEX_CD8<32, CD8VQ>;<br>
-<br>
defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,<br>
v8i64_info>, EVEX_V512,<br>
EVEX_CD8<64, CD8VF>, VEX_W;<br>
-defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,<br>
- VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,<br>
- EVEX_CD8<64, CD8VQ>, VEX_W;<br>
<br>
defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,<br>
v16i32_info>, EVEX_V512,<br>
EVEX_CD8<32, CD8VF>;<br>
-defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,<br>
- VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,<br>
- EVEX_CD8<32, CD8VQ>;<br>
-<br>
defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,<br>
v8i64_info>, EVEX_V512,<br>
EVEX_CD8<64, CD8VF>, VEX_W;<br>
-defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,<br>
- VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,<br>
- EVEX_CD8<64, CD8VQ>, VEX_W;<br>
<br>
defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,<br>
v16i32_info>,<br>
EVEX_V512, EVEX_CD8<32, CD8VF>;<br>
-defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,<br>
- VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,<br>
- EVEX_CD8<32, CD8VQ>;<br>
-<br>
defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,<br>
v8i64_info>, EVEX_V512,<br>
EVEX_CD8<64, CD8VF>, VEX_W;<br>
-defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,<br>
- VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,<br>
- EVEX_CD8<64, CD8VQ>, VEX_W;<br>
+<br>
+defm VPSRL : avx512_varshift_types<0xD2, 0xD3, "vpsrl", X86vsrl>;<br>
+defm VPSLL : avx512_varshift_types<0xF2, 0xF3, "vpsll", X86vshl>;<br>
+defm VPSRA : avx512_varshift_types<0xE2, 0xE2, "vpsra", X86vsra>;<br>
<br>
//===-------------------------------------------------------------------===//<br>
// Variable Bit Shifts<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=222786&r1=222785&r2=222786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h?rev=222786&r1=222785&r2=222786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h (original)<br>
+++ llvm/trunk/lib/Target/X86/X86IntrinsicsInfo.h Tue Nov 25 14:41:51 2014<br>
@@ -21,7 +21,7 @@ enum IntrinsicType {<br>
GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, ADX,<br>
INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP,<br>
CMP_MASK, CMP_MASK_CC, VSHIFT, VSHIFT_MASK, COMI,<br>
- INTR_TYPE_1OP_MASK_RM<br>
+ INTR_TYPE_1OP_MASK_RM, INTR_TYPE_2OP_MASK<br>
};<br>
<br>
struct IntrinsicData {<br>
@@ -195,10 +195,16 @@ static const IntrinsicData IntrinsicsWi<br>
X86_INTRINSIC_DATA(avx512_mask_pcmpgt_w_128, CMP_MASK, X86ISD::PCMPGTM, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_pcmpgt_w_256, CMP_MASK, X86ISD::PCMPGTM, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_pcmpgt_w_512, CMP_MASK, X86ISD::PCMPGTM, 0),<br>
+ X86_INTRINSIC_DATA(avx512_mask_psll_d, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),<br>
+ X86_INTRINSIC_DATA(avx512_mask_psll_q, INTR_TYPE_2OP_MASK, X86ISD::VSHL, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_pslli_d, VSHIFT_MASK, X86ISD::VSHLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_pslli_q, VSHIFT_MASK, X86ISD::VSHLI, 0),<br>
+ X86_INTRINSIC_DATA(avx512_mask_psra_d, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),<br>
+ X86_INTRINSIC_DATA(avx512_mask_psra_q, INTR_TYPE_2OP_MASK, X86ISD::VSRA, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrai_d, VSHIFT_MASK, X86ISD::VSRAI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrai_q, VSHIFT_MASK, X86ISD::VSRAI, 0),<br>
+ X86_INTRINSIC_DATA(avx512_mask_psrl_d, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),<br>
+ X86_INTRINSIC_DATA(avx512_mask_psrl_q, INTR_TYPE_2OP_MASK, X86ISD::VSRL, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrli_d, VSHIFT_MASK, X86ISD::VSRLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_psrli_q, VSHIFT_MASK, X86ISD::VSRLI, 0),<br>
X86_INTRINSIC_DATA(avx512_mask_ucmp_b_128, CMP_MASK_CC, X86ISD::CMPMU, 0),<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=222786&r1=222785&r2=222786&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll?rev=222786&r1=222785&r2=222786&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-intrinsics.ll Tue Nov 25 14:41:51 2014<br>
@@ -1088,3 +1088,141 @@ define <8 x i64> @test_x86_avx512_maskz_<br>
}<br>
<br>
declare <8 x i64> @llvm.x86.avx512.mask.psrai.q(<8 x i64>, i32, <8 x i64>, i8) nounwind readnone<br>
+<br>
+define <16 x i32> @test_x86_avx512_psll_d(<16 x i32> %a0, <4 x i32> %a1) {<br>
+ ; CHECK-LABEL: test_x86_avx512_psll_d<br>
+ ; CHECK: vpslld<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_mask_psll_d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_mask_psll_d<br>
+ ; CHECK: vpslld %xmm1, %zmm0, %zmm2 {%k1}<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_maskz_psll_d(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_maskz_psll_d<br>
+ ; CHECK: vpslld %xmm1, %zmm0, %zmm0 {%k1} {z}<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.psll.d(<16 x i32>, <4 x i32>, <16 x i32>, i16) nounwind readnone<br>
+<br>
+define <8 x i64> @test_x86_avx512_psll_q(<8 x i64> %a0, <2 x i64> %a1) {<br>
+ ; CHECK-LABEL: test_x86_avx512_psll_q<br>
+ ; CHECK: vpsllq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_mask_psll_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_mask_psll_q<br>
+ ; CHECK: vpsllq %xmm1, %zmm0, %zmm2 {%k1}<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_maskz_psll_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_maskz_psll_q<br>
+ ; CHECK: vpsllq %xmm1, %zmm0, %zmm0 {%k1} {z}<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.psll.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone<br>
+<br>
+define <16 x i32> @test_x86_avx512_psrl_d(<16 x i32> %a0, <4 x i32> %a1) {<br>
+ ; CHECK-LABEL: test_x86_avx512_psrl_d<br>
+ ; CHECK: vpsrld<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_mask_psrl_d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_mask_psrl_d<br>
+ ; CHECK: vpsrld %xmm1, %zmm0, %zmm2 {%k1}<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_maskz_psrl_d(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_maskz_psrl_d<br>
+ ; CHECK: vpsrld %xmm1, %zmm0, %zmm0 {%k1} {z}<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.psrl.d(<16 x i32>, <4 x i32>, <16 x i32>, i16) nounwind readnone<br>
+<br>
+define <8 x i64> @test_x86_avx512_psrl_q(<8 x i64> %a0, <2 x i64> %a1) {<br>
+ ; CHECK-LABEL: test_x86_avx512_psrl_q<br>
+ ; CHECK: vpsrlq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_mask_psrl_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_mask_psrl_q<br>
+ ; CHECK: vpsrlq %xmm1, %zmm0, %zmm2 {%k1}<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_maskz_psrl_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_maskz_psrl_q<br>
+ ; CHECK: vpsrlq %xmm1, %zmm0, %zmm0 {%k1} {z}<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.psrl.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone<br>
+<br>
+define <16 x i32> @test_x86_avx512_psra_d(<16 x i32> %a0, <4 x i32> %a1) {<br>
+ ; CHECK-LABEL: test_x86_avx512_psra_d<br>
+ ; CHECK: vpsrad<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 -1)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_mask_psra_d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_mask_psra_d<br>
+ ; CHECK: vpsrad %xmm1, %zmm0, %zmm2 {%k1}<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> %a2, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+define <16 x i32> @test_x86_avx512_maskz_psra_d(<16 x i32> %a0, <4 x i32> %a1, i16 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_maskz_psra_d<br>
+ ; CHECK: vpsrad %xmm1, %zmm0, %zmm0 {%k1} {z}<br>
+ %res = call <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32> %a0, <4 x i32> %a1, <16 x i32> zeroinitializer, i16 %mask)<br>
+ ret <16 x i32> %res<br>
+}<br>
+<br>
+declare <16 x i32> @llvm.x86.avx512.mask.psra.d(<16 x i32>, <4 x i32>, <16 x i32>, i16) nounwind readnone<br>
+<br>
+define <8 x i64> @test_x86_avx512_psra_q(<8 x i64> %a0, <2 x i64> %a1) {<br>
+ ; CHECK-LABEL: test_x86_avx512_psra_q<br>
+ ; CHECK: vpsraq<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 -1)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_mask_psra_q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_mask_psra_q<br>
+ ; CHECK: vpsraq %xmm1, %zmm0, %zmm2 {%k1}<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> %a2, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+define <8 x i64> @test_x86_avx512_maskz_psra_q(<8 x i64> %a0, <2 x i64> %a1, i8 %mask) {<br>
+ ; CHECK-LABEL: test_x86_avx512_maskz_psra_q<br>
+ ; CHECK: vpsraq %xmm1, %zmm0, %zmm0 {%k1} {z}<br>
+ %res = call <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64> %a0, <2 x i64> %a1, <8 x i64> zeroinitializer, i8 %mask)<br>
+ ret <8 x i64> %res<br>
+}<br>
+<br>
+declare <8 x i64> @llvm.x86.avx512.mask.psra.q(<8 x i64>, <2 x i64>, <8 x i64>, i8) nounwind readnone<br>
<br>
<br>
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</blockquote></div><br></div>