<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Nov 28, 2014, at 8:07 AM, Marek Olšák <<a href="mailto:maraeo@gmail.com" class="">maraeo@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class="">From: Marek Olšák <<a href="mailto:marek.olsak@amd.com" class="">marek.olsak@amd.com</a>><br class=""><br class="">InstrMapping was causing TableGen crashes with multi classes.<br class=""></div></blockquote><div><br class=""></div><div><br class=""></div><div>Actually I posted a patch which does exactly this (plus some other cleanups) here:</div><div><br class=""></div><div><a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141124/246167.html" class="">http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20141124/246167.html</a> in <span style="white-space: pre-wrap; background-color: rgb(255, 255, 255);" class="">0002-R600-SI-Various-instruction-format-bit-test-cleanups.patch</span></div><div class=""><br class=""></div><div><br class=""></div><br class=""><blockquote type="cite" class=""><div class="">---<br class=""> lib/Target/R600/SIDefines.h | 3 ++-<br class=""> lib/Target/R600/SIInstrFormats.td | 3 +++<br class=""> lib/Target/R600/SIInstrInfo.cpp | 10 +---------<br class=""> lib/Target/R600/SIInstrInfo.td | 8 --------<br class=""> 4 files changed, 6 insertions(+), 18 deletions(-)<br class=""><br class="">diff --git a/lib/Target/R600/SIDefines.h b/lib/Target/R600/SIDefines.h<br class="">index 2e7dab6..36285c7 100644<br class="">--- a/lib/Target/R600/SIDefines.h<br class="">+++ b/lib/Target/R600/SIDefines.h<br class="">@@ -23,7 +23,8 @@ enum {<br class=""> SALU = 1 << 9,<br class=""> MUBUF = 1 << 10,<br class=""> MTBUF = 1 << 11,<br class="">- FLAT = 1 << 12<br class="">+ FLAT = 1 << 12,<br class="">+ DS = 1 << 13<br class=""> };<br class=""> }<br class=""><br class="">diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td<br class="">index 0fbce35..0f95518 100644<br class="">--- a/lib/Target/R600/SIInstrFormats.td<br class="">+++ b/lib/Target/R600/SIInstrFormats.td<br class="">@@ -27,6 +27,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :<br class=""> field bits<1> MUBUF = 0;<br class=""> field bits<1> MTBUF = 0;<br class=""> field bits<1> FLAT = 0;<br class="">+ field bits<1> DS = 0;<br class=""><br class=""> // These need to be kept in sync with the enum in SIInstrFlags.<br class=""> let TSFlags{0} = VM_CNT;<br class="">@@ -42,6 +43,7 @@ class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :<br class=""> let TSFlags{10} = MUBUF;<br class=""> let TSFlags{11} = MTBUF;<br class=""> let TSFlags{12} = FLAT;<br class="">+ let TSFlags{13} = DS;<br class=""><br class=""> // Most instructions require adjustments after selection to satisfy<br class=""> // operand requirements.<br class="">@@ -544,6 +546,7 @@ let Uses = [EXEC] in {<br class=""> class DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :<br class=""> InstSI <outs, ins, asm, pattern> , DSe<op> {<br class=""><br class="">+ let DS = 1;<br class=""> let LGKM_CNT = 1;<br class=""> let UseNamedOperandTable = 1;<br class=""> let DisableEncoding = "$m0";<br class="">diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp<br class="">index 1a0010c..f71c580 100644<br class="">--- a/lib/Target/R600/SIInstrInfo.cpp<br class="">+++ b/lib/Target/R600/SIInstrInfo.cpp<br class="">@@ -895,16 +895,8 @@ bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr *MIa,<br class=""> return false;<br class=""> }<br class=""><br class="">-namespace llvm {<br class="">-namespace AMDGPU {<br class="">-// Helper function generated by tablegen. We are wrapping this with<br class="">-// an SIInstrInfo function that returns bool rather than int.<br class="">-int isDS(uint16_t Opcode);<br class="">-}<br class="">-}<br class="">-<br class=""> bool SIInstrInfo::isDS(uint16_t Opcode) const {<br class="">- return ::AMDGPU::isDS(Opcode) != -1;<br class="">+ return get(Opcode).TSFlags & SIInstrFlags::DS;<br class=""> }<br class=""><br class=""> bool SIInstrInfo::isMIMG(uint16_t Opcode) const {<br class="">diff --git a/lib/Target/R600/SIInstrInfo.td b/lib/Target/R600/SIInstrInfo.td<br class="">index 392c272..cdbc22e 100644<br class="">--- a/lib/Target/R600/SIInstrInfo.td<br class="">+++ b/lib/Target/R600/SIInstrInfo.td<br class="">@@ -1497,14 +1497,6 @@ def getCommuteOrig : InstrMapping {<br class=""> let ValueCols = [["1"]];<br class=""> }<br class=""><br class="">-def isDS : InstrMapping {<br class="">- let FilterClass = "DS";<br class="">- let RowFields = ["Inst"];<br class="">- let ColFields = ["Size"];<br class="">- let KeyCol = ["8"];<br class="">- let ValueCols = [["8"]];<br class="">-}<br class="">-<br class=""> def getMCOpcode : InstrMapping {<br class=""> let FilterClass = "SIMCInstr";<br class=""> let RowFields = ["PseudoInstr"];<br class="">-- <br class="">2.1.0<br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class=""><a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a><br class="">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br class=""></div></blockquote></div><br class=""></body></html>