<div dir="ltr">This is causing my LLVM build to complain that NeedM0 is never read, only stored to. Is the variable dead or should it be used for something?</div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Nov 21, 2014 at 2:31 PM, Tom Stellard <span dir="ltr"><<a href="mailto:thomas.stellard@amd.com" target="_blank">thomas.stellard@amd.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: tstellar<br>
Date: Fri Nov 21 16:31:44 2014<br>
New Revision: 222583<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=222583&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=222583&view=rev</a><br>
Log:<br>
R600/SI: Emit s_mov_b32 m0, -1 before every DS instruction<br>
<br>
This s_mov_b32 will write to a virtual register from the M0Reg<br>
class and all the ds instructions now take an extra M0Reg explicit<br>
argument.<br>
<br>
This change is necessary to prevent issues with the scheduler<br>
mixing together instructions that expect different values in the m0<br>
registers.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/R600/SIISelLowering.cpp<br>
llvm/trunk/lib/Target/R600/SIInstrFormats.td<br>
llvm/trunk/lib/Target/R600/SIInstrInfo.td<br>
llvm/trunk/lib/Target/R600/SIInstructions.td<br>
llvm/trunk/lib/Target/R600/SILoadStoreOptimizer.cpp<br>
llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp<br>
llvm/trunk/test/CodeGen/R600/shl_add_ptr.ll<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIISelLowering.cpp?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/SIISelLowering.cpp Fri Nov 21 16:31:44 2014<br>
@@ -1986,6 +1986,7 @@ void SITargetLowering::AdjustInstrPostIn<br>
const SIInstrInfo *TII = static_cast<const SIInstrInfo *>(<br>
getTargetMachine().getSubtargetImpl()->getInstrInfo());<br>
<br>
+ MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();<br>
TII->legalizeOperands(MI);<br>
<br>
if (TII->isMIMG(MI->getOpcode())) {<br>
@@ -2005,7 +2006,6 @@ void SITargetLowering::AdjustInstrPostIn<br>
<br>
unsigned NewOpcode = TII->getMaskedMIMGOp(MI->getOpcode(), BitsSet);<br>
MI->setDesc(TII->get(NewOpcode));<br>
- MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();<br>
MRI.setRegClass(VReg, RC);<br>
return;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/R600/SIInstrFormats.td Fri Nov 21 16:31:44 2014<br>
@@ -546,6 +546,7 @@ class DS <bits<8> op, dag outs, dag ins,<br>
<br>
let LGKM_CNT = 1;<br>
let UseNamedOperandTable = 1;<br>
+ let DisableEncoding = "$m0";<br>
}<br>
<br>
class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrInfo.td?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/R600/SIInstrInfo.td Fri Nov 21 16:31:44 2014<br>
@@ -948,7 +948,7 @@ class DS_1A <bits<8> op, dag outs, dag i<br>
class DS_Load_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <<br>
op,<br>
(outs regClass:$vdst),<br>
- (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset),<br>
+ (ins i1imm:$gds, VReg_32:$addr, ds_offset:$offset, M0Reg:$m0),<br>
asm#" $vdst, $addr"#"$offset"#" [M0]",<br>
[]> {<br>
let data0 = 0;<br>
@@ -960,7 +960,8 @@ class DS_Load_Helper <bits<8> op, string<br>
class DS_Load2_Helper <bits<8> op, string asm, RegisterClass regClass> : DS <<br>
op,<br>
(outs regClass:$vdst),<br>
- (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1),<br>
+ (ins i1imm:$gds, VReg_32:$addr, ds_offset0:$offset0, ds_offset1:$offset1,<br>
+ M0Reg:$m0),<br>
asm#" $vdst, $addr"#"$offset0"#"$offset1 [M0]",<br>
[]> {<br>
let data0 = 0;<br>
@@ -973,7 +974,7 @@ class DS_Load2_Helper <bits<8> op, strin<br>
class DS_Store_Helper <bits<8> op, string asm, RegisterClass regClass> : DS_1A <<br>
op,<br>
(outs),<br>
- (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset),<br>
+ (ins i1imm:$gds, VReg_32:$addr, regClass:$data0, ds_offset:$offset, M0Reg:$m0),<br>
asm#" $addr, $data0"#"$offset"#" [M0]",<br>
[]> {<br>
let data1 = 0;<br>
@@ -986,7 +987,7 @@ class DS_Store2_Helper <bits<8> op, stri<br>
op,<br>
(outs),<br>
(ins i1imm:$gds, VReg_32:$addr, regClass:$data0, regClass:$data1,<br>
- ds_offset0:$offset0, ds_offset1:$offset1),<br>
+ ds_offset0:$offset0, ds_offset1:$offset1, M0Reg:$m0),<br>
asm#" $addr, $data0, $data1"#"$offset0"#"$offset1 [M0]",<br>
[]> {<br>
let mayStore = 1;<br>
@@ -999,7 +1000,7 @@ class DS_Store2_Helper <bits<8> op, stri<br>
class DS_1A1D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <<br>
op,<br>
(outs rc:$vdst),<br>
- (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),<br>
+ (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),<br>
asm#" $vdst, $addr, $data0"#"$offset"#" [M0]", []>,<br>
AtomicNoRet<noRetOp, 1> {<br>
<br>
@@ -1014,7 +1015,7 @@ class DS_1A1D_RET <bits<8> op, string as<br>
class DS_1A2D_RET <bits<8> op, string asm, RegisterClass rc, string noRetOp = ""> : DS_1A <<br>
op,<br>
(outs rc:$vdst),<br>
- (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),<br>
+ (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),<br>
asm#" $vdst, $addr, $data0, $data1"#"$offset"#" [M0]",<br>
[]>,<br>
AtomicNoRet<noRetOp, 1> {<br>
@@ -1027,7 +1028,7 @@ class DS_1A2D_RET <bits<8> op, string as<br>
class DS_1A2D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <<br>
op,<br>
(outs),<br>
- (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset),<br>
+ (ins i1imm:$gds, VReg_32:$addr, rc:$data0, rc:$data1, ds_offset:$offset, M0Reg:$m0),<br>
asm#" $addr, $data0, $data1"#"$offset"#" [M0]",<br>
[]>,<br>
AtomicNoRet<noRetOp, 0> {<br>
@@ -1039,7 +1040,7 @@ class DS_1A2D_NORET <bits<8> op, string<br>
class DS_1A1D_NORET <bits<8> op, string asm, RegisterClass rc, string noRetOp = asm> : DS_1A <<br>
op,<br>
(outs),<br>
- (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset),<br>
+ (ins i1imm:$gds, VReg_32:$addr, rc:$data0, ds_offset:$offset, M0Reg:$m0),<br>
asm#" $addr, $data0"#"$offset"#" [M0]",<br>
[]>,<br>
AtomicNoRet<noRetOp, 0> {<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/R600/SIInstructions.td Fri Nov 21 16:31:44 2014<br>
@@ -2614,7 +2614,7 @@ def : ROTRPattern <V_ALIGNBIT_B32>;<br>
<br>
class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <<br>
(vt (frag (DS1Addr1Offset i32:$ptr, i32:$offset))),<br>
- (inst (i1 0), $ptr, (as_i16imm $offset))<br>
+ (inst (i1 0), $ptr, (as_i16imm $offset), (S_MOV_B32 -1))<br>
>;<br>
<br>
def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;<br>
@@ -2632,12 +2632,12 @@ def : DSReadPat <DS_READ_B64, v2i32, loc<br>
def : Pat <<br>
(v2i32 (local_load (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,<br>
i8:$offset1))),<br>
- (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1)<br>
+ (DS_READ2_B32 (i1 0), $ptr, $offset0, $offset1, (S_MOV_B32 -1))<br>
>;<br>
<br>
class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <<br>
(frag vt:$value, (DS1Addr1Offset i32:$ptr, i32:$offset)),<br>
- (inst (i1 0), $ptr, $value, (as_i16imm $offset))<br>
+ (inst (i1 0), $ptr, $value, (as_i16imm $offset), (S_MOV_B32 -1))<br>
>;<br>
<br>
def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;<br>
@@ -2653,12 +2653,13 @@ def : Pat <<br>
(local_store v2i32:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0,<br>
i8:$offset1)),<br>
(DS_WRITE2_B32 (i1 0), $ptr, (EXTRACT_SUBREG $value, sub0),<br>
- (EXTRACT_SUBREG $value, sub1), $offset0, $offset1)<br>
+ (EXTRACT_SUBREG $value, sub1), $offset0, $offset1,<br>
+ (S_MOV_B32 -1))<br>
>;<br>
<br>
class DSAtomicRetPat<DS inst, ValueType vt, PatFrag frag> : Pat <<br>
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$value),<br>
- (inst (i1 0), $ptr, $value, (as_i16imm $offset))<br>
+ (inst (i1 0), $ptr, $value, (as_i16imm $offset), (S_MOV_B32 -1))<br>
>;<br>
<br>
// Special case of DSAtomicRetPat for add / sub 1 -> inc / dec<br>
@@ -2674,13 +2675,13 @@ class DSAtomicRetPat<DS inst, ValueType<br>
class DSAtomicIncRetPat<DS inst, ValueType vt,<br>
Instruction LoadImm, PatFrag frag> : Pat <<br>
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), (vt 1)),<br>
- (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset))<br>
+ (inst (i1 0), $ptr, (LoadImm (vt -1)), (as_i16imm $offset), (S_MOV_B32 -1))<br>
>;<br>
<br>
<br>
class DSAtomicCmpXChg <DS inst, ValueType vt, PatFrag frag> : Pat <<br>
(frag (DS1Addr1Offset i32:$ptr, i32:$offset), vt:$cmp, vt:$swap),<br>
- (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset))<br>
+ (inst (i1 0), $ptr, $cmp, $swap, (as_i16imm $offset), (S_MOV_B32 -1))<br>
>;<br>
<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SILoadStoreOptimizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILoadStoreOptimizer.cpp?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILoadStoreOptimizer.cpp?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SILoadStoreOptimizer.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/SILoadStoreOptimizer.cpp Fri Nov 21 16:31:44 2014<br>
@@ -222,6 +222,7 @@ MachineBasicBlock::iterator SILoadStore<br>
// Be careful, since the addresses could be subregisters themselves in weird<br>
// cases, like vectors of pointers.<br>
const MachineOperand *AddrReg = TII->getNamedOperand(*I, AMDGPU::OpName::addr);<br>
+ const MachineOperand *M0Reg = TII->getNamedOperand(*I, AMDGPU::OpName::m0);<br>
<br>
unsigned DestReg0 = TII->getNamedOperand(*I, AMDGPU::OpName::vdst)->getReg();<br>
unsigned DestReg1<br>
@@ -262,6 +263,7 @@ MachineBasicBlock::iterator SILoadStore<br>
.addOperand(*AddrReg) // addr<br>
.addImm(NewOffset0) // offset0<br>
.addImm(NewOffset1) // offset1<br>
+ .addOperand(*M0Reg) // M0<br>
.addMemOperand(*I->memoperands_begin())<br>
.addMemOperand(*Paired->memoperands_begin());<br>
<br>
@@ -280,6 +282,9 @@ MachineBasicBlock::iterator SILoadStore<br>
LiveInterval &AddrRegLI = LIS->getInterval(AddrReg->getReg());<br>
LIS->shrinkToUses(&AddrRegLI);<br>
<br>
+ LiveInterval &M0RegLI = LIS->getInterval(M0Reg->getReg());<br>
+ LIS->shrinkToUses(&M0RegLI);<br>
+<br>
LIS->getInterval(DestReg); // Create new LI<br>
<br>
DEBUG(dbgs() << "Inserted read2: " << *Read2 << '\n');<br>
@@ -295,6 +300,7 @@ MachineBasicBlock::iterator SILoadStoreO<br>
// Be sure to use .addOperand(), and not .addReg() with these. We want to be<br>
// sure we preserve the subregister index and any register flags set on them.<br>
const MachineOperand *Addr = TII->getNamedOperand(*I, AMDGPU::OpName::addr);<br>
+ const MachineOperand *M0Reg = TII->getNamedOperand(*I, AMDGPU::OpName::m0);<br>
const MachineOperand *Data0 = TII->getNamedOperand(*I, AMDGPU::OpName::data0);<br>
const MachineOperand *Data1<br>
= TII->getNamedOperand(*Paired, AMDGPU::OpName::data0);<br>
@@ -333,11 +339,13 @@ MachineBasicBlock::iterator SILoadStoreO<br>
.addOperand(*Data1) // data1<br>
.addImm(NewOffset0) // offset0<br>
.addImm(NewOffset1) // offset1<br>
+ .addOperand(*M0Reg) // m0<br>
.addMemOperand(*I->memoperands_begin())<br>
.addMemOperand(*Paired->memoperands_begin());<br>
<br>
// XXX - How do we express subregisters here?<br>
- unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg() };<br>
+ unsigned OrigRegs[] = { Data0->getReg(), Data1->getReg(), Addr->getReg(),<br>
+ M0Reg->getReg()};<br>
<br>
LIS->RemoveMachineInstrFromMaps(I);<br>
LIS->RemoveMachineInstrFromMaps(Paired);<br>
<br>
Modified: llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp (original)<br>
+++ llvm/trunk/lib/Target/R600/SILowerControlFlow.cpp Fri Nov 21 16:31:44 2014<br>
@@ -88,7 +88,6 @@ private:<br>
void Kill(MachineInstr &MI);<br>
void Branch(MachineInstr &MI);<br>
<br>
- void InitM0ForLDS(MachineBasicBlock::iterator MI);<br>
void LoadM0(MachineInstr &MI, MachineInstr *MovRel);<br>
void IndirectSrc(MachineInstr &MI);<br>
void IndirectDst(MachineInstr &MI);<br>
@@ -325,14 +324,6 @@ void SILowerControlFlowPass::Kill(Machin<br>
MI.eraseFromParent();<br>
}<br>
<br>
-/// The m0 register stores the maximum allowable address for LDS reads and<br>
-/// writes. Its value must be at least the size in bytes of LDS allocated by<br>
-/// the shader. For simplicity, we set it to the maximum possible value.<br>
-void SILowerControlFlowPass::InitM0ForLDS(MachineBasicBlock::iterator MI) {<br>
- BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32),<br>
- AMDGPU::M0).addImm(0xffffffff);<br>
-}<br>
-<br>
void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) {<br>
<br>
MachineBasicBlock &MBB = *MI.getParent();<br>
@@ -391,12 +382,6 @@ void SILowerControlFlowPass::LoadM0(Mach<br>
.addReg(Save);<br>
<br>
}<br>
- // FIXME: Are there any values other than the LDS address clamp that need to<br>
- // be stored in the m0 register and may be live for more than a few<br>
- // instructions? If so, we should save the m0 register at the beginning<br>
- // of this function and restore it here.<br>
- // FIXME: Add support for LDS direct loads.<br>
- InitM0ForLDS(&MI);<br>
MI.eraseFromParent();<br>
}<br>
<br>
@@ -465,7 +450,6 @@ bool SILowerControlFlowPass::runOnMachin<br>
<br>
MachineInstr &MI = *I;<br>
if (TII->isDS(MI.getOpcode())) {<br>
- NeedM0 = true;<br>
NeedWQM = true;<br>
}<br>
<br>
@@ -544,13 +528,6 @@ bool SILowerControlFlowPass::runOnMachin<br>
}<br>
}<br>
<br>
- if (NeedM0) {<br>
- MachineBasicBlock &MBB = MF.front();<br>
- // Initialize M0 to a value that won't cause LDS access to be discarded<br>
- // due to offset clamping<br>
- InitM0ForLDS(MBB.getFirstNonPHI());<br>
- }<br>
-<br>
if (NeedWQM && MFI->getShaderType() == ShaderType::PIXEL) {<br>
MachineBasicBlock &MBB = MF.front();<br>
BuildMI(MBB, MBB.getFirstNonPHI(), DebugLoc(), TII->get(AMDGPU::S_WQM_B64),<br>
<br>
Modified: llvm/trunk/test/CodeGen/R600/shl_add_ptr.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/shl_add_ptr.ll?rev=222583&r1=222582&r2=222583&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/R600/shl_add_ptr.ll?rev=222583&r1=222582&r2=222583&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/R600/shl_add_ptr.ll (original)<br>
+++ llvm/trunk/test/CodeGen/R600/shl_add_ptr.ll Fri Nov 21 16:31:44 2014<br>
@@ -68,7 +68,8 @@ define void @load_shl_base_lds_max_offse<br>
; pointer can be used with an offset into the second one.<br>
<br>
; SI-LABEL: {{^}}load_shl_base_lds_2:<br>
-; SI: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}<br>
+; SI: s_mov_b32 m0, -1<br>
+; SI-NEXT: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 2, {{v[0-9]+}}<br>
; SI-NEXT: ds_read2st64_b32 {{v\[[0-9]+:[0-9]+\]}}, [[PTR]] offset0:1 offset1:9 [M0]<br>
; SI: s_endpgm<br>
define void @load_shl_base_lds_2(float addrspace(1)* %out) #0 {<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div>