<HTML><HEAD><TITLE>Samsung Enterprise Portal mySingle</TITLE>
<META content=IE=5 http-equiv=X-UA-Compatible>
<META content="text/html; charset=windows-1252" http-equiv=Content-Type>
<STYLE id=mysingle_style type=text/css>P {
MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px
}
TD {
MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px
}
LI {
MARGIN-BOTTOM: 5px; FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN-TOP: 5px
}
BODY {
FONT-SIZE: 9pt; FONT-FAMILY: Arial, arial; MARGIN: 10px; LINE-HEIGHT: 1.4
}
</STYLE>
<META name=GENERATOR content=ActiveSquare></HEAD>
<BODY>
<META name=GENERATOR content=ActiveSquare>
<P>Hi Tim, </P>
<P>default bool operator==() is not added implicitly.</P>
<P>Not declaring bool operator==(const RegListOperandRules &rhs) const was giving errors while compiling like these as default operator== was not defined for the type RegListOperandRules</P>
<P><SPAN style="COLOR: rgb(255,0,0)">In file included from /usr/include/c++/4.8/bits/stl_algobase.h:64:0,</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">from /usr/include/c++/4.8/bits/char_traits.h:39,<BR>from /usr/include/c++/4.8/string:40,<BR>from /home/jyoti.allur/LLVM/llvm/lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h:18,<BR>from /home/jyoti.allur/LLVM/llvm/lib/Target/ARM/ARMFeatures.h:17,<BR>from /home/jyoti.allur/LLVM/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp:11:</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">/usr/include/c++/4.8/bits/stl_pair.h:214:5: note: template<class _T1, class _T2> constexpr bool std::operator==(const std::pair<_T1, _T2>&, const std::pair<_T1, _T2>&)</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">operator==(const pair<_T1, _T2>& __x, const pair<_T1, _T2>& __y)<BR>^</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">/usr/include/c++/4.8/bits/stl_pair.h:214:5: note: template argument deduction/substitution failed:<BR>In file included from /usr/include/c++/4.8/algorithm:62:0,</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">from /home/jyoti.allur/LLVM/llvm/include/llvm/ADT/SmallVector.h:22,<BR>from /home/jyoti.allur/LLVM/llvm/include/llvm/ADT/ArrayRef.h:15,<BR>from /home/jyoti.allur/LLVM/llvm/include/llvm/ADT/APInt.h:19,<BR>from /home/jyoti.allur/LLVM/llvm/include/llvm/ADT/APFloat.h:20,<BR>from /home/jyoti.allur/LLVM/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h:17,<BR>from /home/jyoti.allur/LLVM/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp:12:</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">/usr/include/c++/4.8/bits/stl_algo.h:194:17: note: âconst RegListOperandRulesâ is not derived from âconst std::pair<_T1, _T2>â</SPAN></P>
<P><SPAN style="COLOR: rgb(255,0,0)">if (*__first == __val)</SPAN></P>
<P> </P>
<P>I am not sure if I follow your comment, did you mean we should provide 'default' keyword of c++11 like below and compile llvm with -std=c++11 flag?<BR>bool operator==(const RegListOperandRules &rhs) const = default;</P>
<P>OR</P>
<P> </P>
<P>Implement something like :-</P>
<P> </P>
<P>struct RegListOperandRulesForSTM<BR>{<BR> RegListOperandRules RegListOperand;<BR> RegListOperandRulesForSTM(const RegListOperandRules& X): RegListOperand(X) {}<BR> bool operator()(const RegListOperandRules& regListOperand) const {<BR> return (RegListOperand.OPcode == regListOperand.OPcode &&<BR> RegListOperand.AllowSP == regListOperand.AllowSP &&<BR> RegListOperand.AllowPC == regListOperand.AllowPC &&<BR> RegListOperand.AllowBaseRegister == regListOperand.AllowBaseRegister &&<BR> RegListOperand.AllowLowRegisterOnly == regListOperand.AllowLowRegisterOnly);<BR> }<BR>}; //as we check only these flags for STM set of instructions.</P>
<P>auto Entry = std::find_if(std::begin(AllowedCombinations), std::end(AllowedCombinations), RegListOperandRulesForSTM(RegListOperandRules(regListOp)));</P>
<P> if (Entry == std::end(AllowedCombinations)) {</P>
<P> switch (Opcode) {<BR> case ARM::t2STMIA_UPD:<BR> case ARM::t2STMDB_UPD: {<BR> if (BaseReg)<BR> return Error(Operands.back()->getStartLoc(),<BR> "writeback register not allowed in register list");<BR>.............</P>
<P>...........</P>
<P>...........</P>
<P> </P>
<P>and similarly implement for LDM ? </P>
<P>If we follow above method we will have to define 4 operator==(), for LDM set, STM set, POP, ARM instructions set as rules to check are different for each of these set mentioned. </P>
<P>The problem is even though we would search based on custom operator==(), we will still need to print the diagnostic after checking the bool flags <SPAN style="WHITE-SPACE: pre-wrap; WORD-SPACING: 0px; TEXT-TRANSFORM: none; FLOAT: none; COLOR: rgb(0,0,0); TEXT-ALIGN: left; FONT: 11px/16px Menlo, Consolas, Monaco, monospace; DISPLAY: inline !important; LETTER-SPACING: normal; BACKGROUND-COLOR: rgb(170,255,170); TEXT-INDENT: 0px; -webkit-text-stroke-width: 0px">bool SP, PC, LR, BaseReg, LowReg</SPAN> for throwing appropriate of diagnostic.</P>
<P> </P>
<P> </P>
<P>Regards,</P>
<P>Jyoti Allur<BR><BR>------- Original Message -------<BR>Sender : Tim Northover<t.p.northover@gmail.com> <BR>Date : Nov 20, 2014 03:21 (GMT+05:30)<BR>Title : Re: [PATCH] [PATCH] [Thumb/Thumb2] Added restrictions on PC, LR,<BR> SP in the register list for PUSH/POP/LDM/STM<BR><BR>I think this is splitting up the logic along confusing lines. Some checks are still in the parent switch, but others have been moved to the new validateRegListOperands function.<BR><BR>It looks like that split might be because they use subtarget predicates. If so, just make validateRegListOperands a member of ARMAsmParser.<BR><BR>Cheers.<BR><BR>Tim.<BR><BR>================<BR>Comment at: lib/Target/ARM/AsmParser/ARMAsmParser.cpp:5816-5819<BR>@@ +5815,6 @@<BR>+<BR>+ bool operator==(const RegListOperandRules &rhs) const {<BR>+ return (OPcode == rhs.OPcode && AllowSP == rhs.AllowSP &&<BR>+ AllowPC == rhs.AllowPC && AllowPCAndLR == rhs.AllowPCAndLR &&<BR>+ AllowInITBlock == rhs.AllowInITBlock);<BR>+ }<BR>----------------<BR>Isn't this the default?<BR><BR>http://reviews.llvm.org/D6090<BR><BR><BR><p> </p><p> </p></P></BODY></HTML><img src='http://ext.samsung.net/mailcheck/SeenTimeChecker?do=e3e1a57eba32dd3d0c563648d127f60e20e5e2e43fe82fe58858b930e647c73db5b181570026814a8769d93e1d9e9a7cddaee51834417892db9fdddda33e82cbe4a391424e62fcf6cf878f9a26ce15a0' border=0 width=0 height=0 style='display:none'>