Hi Tom,<br><br>This is failing on at least:<div><br></div><div><a href="http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/18432">http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/18432</a><br></div><div><br></div><div>Mind looking? I'll probably revert in a bit if I don't hear anything as I'd like to get the bots back green.</div><div><br></div><div>Thanks.</div><div><br></div><div>-eric</div><br><div class="gmail_quote">On Fri Nov 14 2014 at 6:10:58 AM Tom Stellard <<a href="mailto:thomas.stellard@amd.com">thomas.stellard@amd.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: tstellar<br>
Date: Fri Nov 14 08:08:00 2014<br>
New Revision: 221994<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=221994&view=rev" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project?rev=221994&view=rev</a><br>
Log:<br>
R600/SI: Start implementing an assembler<br>
<br>
This was done using the Sparc and PowerPC AsmParsers as guides. So far it<br>
is very simple and only supports sopp instructions.<br>
<br>
Added:<br>
llvm/trunk/docs/R600Usage.rst<br>
llvm/trunk/lib/Target/R600/<u></u>AsmParser/<br>
llvm/trunk/lib/Target/R600/<u></u>AsmParser/AMDGPUAsmParser.cpp<br>
llvm/trunk/lib/Target/R600/<u></u>AsmParser/CMakeLists.txt<br>
llvm/trunk/lib/Target/R600/<u></u>AsmParser/LLVMBuild.txt<br>
- copied, changed from r221977, llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt<br>
llvm/trunk/lib/Target/R600/<u></u>AsmParser/Makefile<br>
llvm/trunk/test/MC/R600/<br>
llvm/trunk/test/MC/R600/lit.<u></u>local.cfg<br>
llvm/trunk/test/MC/R600/sopp.s<br>
Modified:<br>
llvm/trunk/docs/index.rst<br>
llvm/trunk/lib/Target/R600/<u></u>AMDGPU.td<br>
llvm/trunk/lib/Target/R600/<u></u>AMDGPUInstructions.td<br>
llvm/trunk/lib/Target/R600/<u></u>CMakeLists.txt<br>
llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt<br>
llvm/trunk/lib/Target/R600/<u></u>Makefile<br>
llvm/trunk/lib/Target/R600/<u></u>R600InstrFormats.td<br>
llvm/trunk/lib/Target/R600/<u></u>R600Instructions.td<br>
llvm/trunk/lib/Target/R600/<u></u>SIInstrFormats.td<br>
llvm/trunk/lib/Target/R600/<u></u>SIInstructions.td<br>
<br>
Added: llvm/trunk/docs/R600Usage.rst<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/R600Usage.rst?rev=221994&view=auto" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/docs/<u></u>R600Usage.rst?rev=221994&view=<u></u>auto</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/docs/R600Usage.rst (added)<br>
+++ llvm/trunk/docs/R600Usage.rst Fri Nov 14 08:08:00 2014<br>
@@ -0,0 +1,43 @@<br>
+============================<br>
+User Guide for R600 Back-end<br>
+============================<br>
+<br>
+Introduction<br>
+============<br>
+<br>
+The R600 back-end provides ISA code generation for AMD GPUs, starting with<br>
+the R600 family up until the current Sea Islands (GCN Gen 2).<br>
+<br>
+<br>
+Assembler<br>
+=========<br>
+<br>
+The assembler is currently a work in progress and not yet complete. Below<br>
+are the currently supported features.<br>
+<br>
+SOPP Instructions<br>
+-----------------<br>
+<br>
+Unless otherwise mentioned, all SOPP instructions that with an operand<br>
+accept a integer operand(s) only. No verification is performed on the<br>
+operands, so it is up to the programmer to be familiar with the range<br>
+or acceptable values.<br>
+<br>
+s_waitcnt<br>
+^^^^^^^^^<br>
+<br>
+s_waitcnt accepts named arguments to specify which memory counter(s) to<br>
+wait for.<br>
+<br>
+.. code-block:: nasm<br>
+<br>
+ // Wait for all counters to be 0<br>
+ s_waitcnt 0<br>
+<br>
+ // Equivalent to s_waitcnt 0. Counter names can also be delimited by<br>
+ // '&' or ','.<br>
+ s_waitcnt vmcnt(0) expcnt(0) lgkcmt(0)<br>
+<br>
+ // Wait for vmcnt counter to be 1.<br>
+ s_waitcnt vmcnt(1)<br>
+<br>
<br>
Modified: llvm/trunk/docs/index.rst<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/index.rst?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/docs/index.<u></u>rst?rev=221994&r1=221993&r2=<u></u>221994&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/docs/index.rst (original)<br>
+++ llvm/trunk/docs/index.rst Fri Nov 14 08:08:00 2014<br>
@@ -235,6 +235,7 @@ For API clients and LLVM developers.<br>
WritingAnLLVMPass<br>
HowToUseAttributes<br>
NVPTXUsage<br>
+ R600Usage<br>
StackMaps<br>
InAlloca<br>
BigEndianNEON<br>
@@ -317,6 +318,9 @@ For API clients and LLVM developers.<br>
:doc:`NVPTXUsage`<br>
This document describes using the NVPTX back-end to compile GPU kernels.<br>
<br>
+:doc:`R600Usage`<br>
+ This document describes how to use the R600 back-end.<br>
+<br>
:doc:`StackMaps`<br>
LLVM support for mapping instruction addresses to the location of<br>
values and allowing code to be patched.<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>AMDGPU.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPU.td?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/AMDGPU.td?rev=221994&r1=<u></u>221993&r2=221994&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>AMDGPU.td (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>AMDGPU.td Fri Nov 14 08:08:00 2014<br>
@@ -153,9 +153,16 @@ def AMDGPUInstrInfo : InstrInfo {<br>
let guessInstructionProperties = 1;<br>
}<br>
<br>
+def AMDGPUAsmParser : AsmParser {<br>
+ // Some of the R600 registers have the same name, so this crashes.<br>
+ // For example T0_XYZW and T0_XY both have the asm name T0.<br>
+ let ShouldEmitMatchRegisterName = 0;<br>
+}<br>
+<br>
def AMDGPU : Target {<br>
// Pull in Instruction Info:<br>
let InstructionSet = AMDGPUInstrInfo;<br>
+ let AssemblyParsers = [AMDGPUAsmParser];<br>
}<br>
<br>
// Dummy Instruction itineraries for pseudo instructions<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>AMDGPUInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AMDGPUInstructions.td?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/AMDGPUInstructions.td?<u></u>rev=221994&r1=221993&r2=<u></u>221994&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>AMDGPUInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>AMDGPUInstructions.td Fri Nov 14 08:08:00 2014<br>
@@ -23,6 +23,8 @@ class AMDGPUInst <dag outs, dag ins, str<br>
let Pattern = pattern;<br>
let Itinerary = NullALU;<br>
<br>
+ let isCodeGenOnly = 1;<br>
+<br>
let TSFlags{63} = isRegisterLoad;<br>
let TSFlags{62} = isRegisterStore;<br>
}<br>
<br>
Added: llvm/trunk/lib/Target/R600/<u></u>AsmParser/AMDGPUAsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AsmParser/AMDGPUAsmParser.cpp?rev=221994&view=auto" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/AsmParser/<u></u>AMDGPUAsmParser.cpp?rev=<u></u>221994&view=auto</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>AsmParser/AMDGPUAsmParser.cpp (added)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>AsmParser/AMDGPUAsmParser.cpp Fri Nov 14 08:08:00 2014<br>
@@ -0,0 +1,320 @@<br>
+//===-- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===------------------------<u></u>------------------------------<u></u>----------------===//<br>
+<br>
+#include "MCTargetDesc/<u></u>AMDGPUMCTargetDesc.h"<br>
+#include "llvm/ADT/SmallString.h"<br>
+#include "llvm/ADT/SmallVector.h"<br>
+#include "llvm/ADT/STLExtras.h"<br>
+#include "llvm/ADT/StringSwitch.h"<br>
+#include "llvm/ADT/Twine.h"<br>
+#include "llvm/MC/MCContext.h"<br>
+#include "llvm/MC/MCExpr.h"<br>
+#include "llvm/MC/MCInst.h"<br>
+#include "llvm/MC/MCInstrInfo.h"<br>
+#include "llvm/MC/MCParser/MCAsmLexer.<u></u>h"<br>
+#include "llvm/MC/MCParser/MCAsmParser.<u></u>h"<br>
+#include "llvm/MC/MCParser/<u></u>MCParsedAsmOperand.h"<br>
+#include "llvm/MC/MCRegisterInfo.h"<br>
+#include "llvm/MC/MCStreamer.h"<br>
+#include "llvm/MC/MCSubtargetInfo.h"<br>
+#include "llvm/MC/MCTargetAsmParser.h"<br>
+#include "llvm/Support/SourceMgr.h"<br>
+#include "llvm/Support/TargetRegistry.<u></u>h"<br>
+#include "llvm/Support/raw_ostream.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+namespace {<br>
+<br>
+class AMDGPUAsmParser : public MCTargetAsmParser {<br>
+ MCSubtargetInfo &STI;<br>
+ MCAsmParser &Parser;<br>
+<br>
+<br>
+ /// @name Auto-generated Match Functions<br>
+ /// {<br>
+<br>
+#define GET_ASSEMBLER_HEADER<br>
+#include "AMDGPUGenAsmMatcher.inc"<br>
+<br>
+ /// }<br>
+<br>
+public:<br>
+ AMDGPUAsmParser(<u></u>MCSubtargetInfo &_STI, MCAsmParser &_Parser,<br>
+ const MCInstrInfo &_MII,<br>
+ const MCTargetOptions &Options)<br>
+ : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {<br>
+ setAvailableFeatures(<u></u>ComputeAvailableFeatures(STI.<u></u>getFeatureBits()));<br>
+ }<br>
+ bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;<br>
+ bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,<br>
+ OperandVector &Operands, MCStreamer &Out,<br>
+ uint64_t &ErrorInfo,<br>
+ bool MatchingInlineAsm) override;<br>
+ bool ParseDirective(AsmToken DirectiveID) override;<br>
+ OperandMatchResultTy parseOperand(OperandVector &Operands, StringRef Mnemonic);<br>
+ bool ParseInstruction(<u></u>ParseInstructionInfo &Info, StringRef Name,<br>
+ SMLoc NameLoc, OperandVector &Operands) override;<br>
+<br>
+ bool parseCnt(int64_t &IntVal);<br>
+ OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);<br>
+};<br>
+<br>
+class AMDGPUOperand : public MCParsedAsmOperand {<br>
+ enum KindTy {<br>
+ Token,<br>
+ Immediate<br>
+ } Kind;<br>
+<br>
+public:<br>
+ AMDGPUOperand(enum KindTy K) : MCParsedAsmOperand(), Kind(K) {}<br>
+<br>
+ struct TokOp {<br>
+ const char *Data;<br>
+ unsigned Length;<br>
+ };<br>
+<br>
+ struct ImmOp {<br>
+ int64_t Val;<br>
+ };<br>
+<br>
+ union {<br>
+ TokOp Tok;<br>
+ ImmOp Imm;<br>
+ };<br>
+<br>
+ void addImmOperands(MCInst &Inst, unsigned N) const {<br>
+ Inst.addOperand(MCOperand::<u></u>CreateImm(getImm()));<br>
+ }<br>
+ void addRegOperands(MCInst &Inst, unsigned N) const {<br>
+ llvm_unreachable("<u></u>addRegOperands");<br>
+ }<br>
+ StringRef getToken() const {<br>
+ return StringRef(Tok.Data, Tok.Length);<br>
+ }<br>
+ bool isToken() const override {<br>
+ return Kind == Token;<br>
+ }<br>
+<br>
+ bool isImm() const override {<br>
+ return Kind == Immediate;<br>
+ }<br>
+<br>
+ int64_t getImm() const {<br>
+ return Imm.Val;<br>
+ }<br>
+<br>
+ bool isReg() const override {<br>
+ return false;<br>
+ }<br>
+<br>
+ unsigned getReg() const override {<br>
+ return 0;<br>
+ }<br>
+<br>
+ bool isMem() const override {<br>
+ return false;<br>
+ }<br>
+<br>
+ SMLoc getStartLoc() const override {<br>
+ return SMLoc();<br>
+ }<br>
+<br>
+ SMLoc getEndLoc() const override {<br>
+ return SMLoc();<br>
+ }<br>
+<br>
+ void print(raw_ostream &OS) const override { }<br>
+<br>
+ static std::unique_ptr<AMDGPUOperand> CreateImm(int64_t Val) {<br>
+ auto Op = llvm::make_unique<<u></u>AMDGPUOperand>(Immediate);<br>
+ Op->Imm.Val = Val;<br>
+ return Op;<br>
+ }<br>
+<br>
+ static std::unique_ptr<AMDGPUOperand> CreateToken(StringRef Str, SMLoc Loc) {<br>
+ auto Res = llvm::make_unique<<u></u>AMDGPUOperand>(Token);<br>
+ Res->Tok.Data = Str.data();<br>
+ Res->Tok.Length = Str.size();<br>
+ return Res;<br>
+ }<br>
+<br>
+ bool isSWaitCnt() const;<br>
+};<br>
+<br>
+}<br>
+<br>
+bool AMDGPUAsmParser::<u></u>ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {<br>
+ return true;<br>
+}<br>
+<br>
+<br>
+bool AMDGPUAsmParser::<u></u>MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,<br>
+ OperandVector &Operands,<br>
+ MCStreamer &Out,<br>
+ uint64_t &ErrorInfo,<br>
+ bool MatchingInlineAsm) {<br>
+ MCInst Inst;<br>
+<br>
+ switch (MatchInstructionImpl(<u></u>Operands, Inst, ErrorInfo, MatchingInlineAsm)) {<br>
+ default: break;<br>
+ case Match_Success:<br>
+ Inst.setLoc(IDLoc);<br>
+ Out.EmitInstruction(Inst, STI);<br>
+ return false;<br>
+ case Match_MissingFeature:<br>
+ return Error(IDLoc, "instruction use requires an option to be enabled");<br>
+ case Match_MnemonicFail:<br>
+ return Error(IDLoc, "unrecognized instruction mnemonic");<br>
+ case Match_InvalidOperand: {<br>
+ if (ErrorInfo != ~0ULL) {<br>
+ if (ErrorInfo >= Operands.size())<br>
+ return Error(IDLoc, "too few operands for instruction");<br>
+<br>
+ }<br>
+ return Error(IDLoc, "invalid operand for instruction");<br>
+ }<br>
+ }<br>
+ llvm_unreachable("Implement any new match types added!");<br>
+}<br>
+<br>
+bool AMDGPUAsmParser::<u></u>ParseDirective(AsmToken DirectiveID) {<br>
+ return true;<br>
+}<br>
+<br>
+AMDGPUAsmParser::<u></u>OperandMatchResultTy<br>
+AMDGPUAsmParser::<u></u>parseOperand(OperandVector &Operands, StringRef Mnemonic) {<br>
+<br>
+ // Try to parse with a custom parser<br>
+ OperandMatchResultTy ResTy = MatchOperandParserImpl(<u></u>Operands, Mnemonic);<br>
+<br>
+ // If we successfully parsed the operand or if there as an error parsing,<br>
+ // we are done.<br>
+ if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail)<br>
+ return ResTy;<br>
+<br>
+ switch(getLexer().getKind()) {<br>
+ case AsmToken::Integer: {<br>
+ int64_t IntVal;<br>
+ if (getParser().<u></u>parseAbsoluteExpression(<u></u>IntVal))<br>
+ return MatchOperand_ParseFail;<br>
+ Operands.push_back(<u></u>AMDGPUOperand::CreateImm(<u></u>IntVal));<br>
+ return MatchOperand_Success;<br>
+ }<br>
+ default:<br>
+ return MatchOperand_NoMatch;<br>
+ }<br>
+}<br>
+<br>
+bool AMDGPUAsmParser::<u></u>ParseInstruction(<u></u>ParseInstructionInfo &Info,<br>
+ StringRef Name,<br>
+ SMLoc NameLoc, OperandVector &Operands) {<br>
+ // Add the instruction mnemonic<br>
+ Operands.push_back(<u></u>AMDGPUOperand::CreateToken(<u></u>Name, NameLoc));<br>
+<br>
+ if (getLexer().is(AsmToken::<u></u>EndOfStatement))<br>
+ return false;<br>
+<br>
+ AMDGPUAsmParser::<u></u>OperandMatchResultTy Res = parseOperand(Operands, Name);<br>
+ switch (Res) {<br>
+ case MatchOperand_Success: return false;<br>
+ case MatchOperand_ParseFail: return Error(NameLoc,<br>
+ "Failed parsing operand");<br>
+ case MatchOperand_NoMatch: return Error(NameLoc, "Not a valid operand");<br>
+ }<br>
+ return true;<br>
+}<br>
+<br>
+//===------------------------<u></u>------------------------------<u></u>----------------===//<br>
+// s_waitcnt<br>
+//===------------------------<u></u>------------------------------<u></u>----------------===//<br>
+<br>
+bool AMDGPUAsmParser::parseCnt(<u></u>int64_t &IntVal) {<br>
+ StringRef CntName = Parser.getTok().getString();<br>
+ int64_t CntVal;<br>
+<br>
+ Parser.Lex();<br>
+ if (getLexer().isNot(AsmToken::<u></u>LParen))<br>
+ return true;<br>
+<br>
+ Parser.Lex();<br>
+ if (getLexer().isNot(AsmToken::<u></u>Integer))<br>
+ return true;<br>
+<br>
+ if (getParser().<u></u>parseAbsoluteExpression(<u></u>CntVal))<br>
+ return true;<br>
+<br>
+ if (getLexer().isNot(AsmToken::<u></u>RParen))<br>
+ return true;<br>
+<br>
+ Parser.Lex();<br>
+ if (getLexer().is(AsmToken::Amp) || getLexer().is(AsmToken::Comma)<u></u>)<br>
+ Parser.Lex();<br>
+<br>
+ int CntShift;<br>
+ int CntMask;<br>
+<br>
+ if (CntName == "vmcnt") {<br>
+ CntMask = 0xf;<br>
+ CntShift = 0;<br>
+ } else if (CntName == "expcnt") {<br>
+ CntMask = 0x7;<br>
+ CntShift = 4;<br>
+ } else if (CntName == "lgkmcnt") {<br>
+ CntMask = 0x7;<br>
+ CntShift = 8;<br>
+ } else {<br>
+ return true;<br>
+ }<br>
+<br>
+ IntVal &= ~(CntMask << CntShift);<br>
+ IntVal |= (CntVal << CntShift);<br>
+ return false;<br>
+}<br>
+<br>
+AMDGPUAsmParser::<u></u>OperandMatchResultTy<br>
+AMDGPUAsmParser::<u></u>parseSWaitCntOps(OperandVector &Operands) {<br>
+ // Disable all counters by default.<br>
+ // vmcnt [3:0]<br>
+ // expcnt [6:4]<br>
+ // lgkmcnt [10:8]<br>
+ int64_t CntVal = 0x77f;<br>
+<br>
+ switch(getLexer().getKind()) {<br>
+ default: return MatchOperand_ParseFail;<br>
+ case AsmToken::Integer:<br>
+ // The operand can be an integer value.<br>
+ if (getParser().<u></u>parseAbsoluteExpression(<u></u>CntVal))<br>
+ return MatchOperand_ParseFail;<br>
+ break;<br>
+<br>
+ case AsmToken::Identifier:<br>
+ do {<br>
+ if (parseCnt(CntVal))<br>
+ return MatchOperand_ParseFail;<br>
+ } while(getLexer().isNot(<u></u>AsmToken::EndOfStatement));<br>
+ break;<br>
+ }<br>
+ Operands.push_back(<u></u>AMDGPUOperand::CreateImm(<u></u>CntVal));<br>
+ return MatchOperand_Success;<br>
+}<br>
+<br>
+bool AMDGPUOperand::isSWaitCnt() const {<br>
+ return isImm();<br>
+}<br>
+<br>
+/// Force static initialization.<br>
+extern "C" void LLVMInitializeR600AsmParser() {<br>
+ RegisterMCAsmParser<<u></u>AMDGPUAsmParser> A(TheAMDGPUTarget);<br>
+}<br>
+<br>
+#define GET_REGISTER_MATCHER<br>
+#define GET_MATCHER_IMPLEMENTATION<br>
+#include "AMDGPUGenAsmMatcher.inc"<br>
+<br>
<br>
Added: llvm/trunk/lib/Target/R600/<u></u>AsmParser/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AsmParser/CMakeLists.txt?rev=221994&view=auto" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/AsmParser/CMakeLists.txt?<u></u>rev=221994&view=auto</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>AsmParser/CMakeLists.txt (added)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>AsmParser/CMakeLists.txt Fri Nov 14 08:08:00 2014<br>
@@ -0,0 +1,3 @@<br>
+add_llvm_library(<u></u>LLVMR600AsmParser<br>
+ AMDGPUAsmParser.cpp<br>
+ )<br>
<br>
Copied: llvm/trunk/lib/Target/R600/<u></u>AsmParser/LLVMBuild.txt (from r221977, llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt)<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AsmParser/LLVMBuild.txt?p2=llvm/trunk/lib/Target/R600/AsmParser/LLVMBuild.txt&p1=llvm/trunk/lib/Target/R600/LLVMBuild.txt&r1=221977&r2=221994&rev=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/AsmParser/LLVMBuild.txt?<u></u>p2=llvm/trunk/lib/Target/R600/<u></u>AsmParser/LLVMBuild.txt&p1=<u></u>llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt&r1=221977&r2=<u></u>221994&rev=221994&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>AsmParser/LLVMBuild.txt Fri Nov 14 08:08:00 2014<br>
@@ -1,4 +1,4 @@<br>
-;===- ./lib/Target/AMDIL/LLVMBuild.<u></u>txt -------------------------*- Conf -*--===;<br>
+;===- ./lib/Target/R600/AsmParser/<u></u>LLVMBuild.txt -------------*- Conf -*--===;<br>
;<br>
; The LLVM Compiler Infrastructure<br>
;<br>
@@ -15,18 +15,9 @@<br>
;<br>
;===--------------------------<u></u>------------------------------<u></u>----------------===;<br>
<br>
-[common]<br>
-subdirectories = InstPrinter MCTargetDesc TargetInfo<br>
-<br>
[component_0]<br>
-type = TargetGroup<br>
-name = R600<br>
-parent = Target<br>
-has_asmprinter = 1<br>
-<br>
-[component_1]<br>
type = Library<br>
-name = R600CodeGen<br>
+name = R600AsmParser<br>
parent = R600<br>
-required_libraries = Analysis AsmPrinter CodeGen Core IPO MC R600AsmPrinter R600Desc R600Info Scalar SelectionDAG Support Target TransformUtils<br>
+required_libraries = MC MCParser R600Desc R600Info Support<br>
add_to_library_groups = R600<br>
<br>
Added: llvm/trunk/lib/Target/R600/<u></u>AsmParser/Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/AsmParser/Makefile?rev=221994&view=auto" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/AsmParser/Makefile?rev=<u></u>221994&view=auto</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>AsmParser/Makefile (added)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>AsmParser/Makefile Fri Nov 14 08:08:00 2014<br>
@@ -0,0 +1,15 @@<br>
+##===- lib/Target/R600/AsmParser/<u></u>Makefile ----------------*- Makefile -*-===##<br>
+#<br>
+# The LLVM Compiler Infrastructure<br>
+#<br>
+# This file is distributed under the University of Illinois Open Source<br>
+# License. See LICENSE.TXT for details.<br>
+#<br>
+##===------------------------<u></u>------------------------------<u></u>----------------===##<br>
+LEVEL = ../../../..<br>
+LIBRARYNAME = LLVMR600AsmParser<br>
+<br>
+# Hack: we need to include 'main' R600 target directory to grab private headers<br>
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..<br>
+<br>
+include $(LEVEL)/Makefile.common<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/CMakeLists.txt?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/CMakeLists.txt?rev=<u></u>221994&r1=221993&r2=221994&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>CMakeLists.txt Fri Nov 14 08:08:00 2014<br>
@@ -9,6 +9,7 @@ tablegen(LLVM AMDGPUGenIntrinsics.inc -g<br>
tablegen(LLVM AMDGPUGenMCCodeEmitter.inc -gen-emitter)<br>
tablegen(LLVM AMDGPUGenDFAPacketizer.inc -gen-dfa-packetizer)<br>
tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer)<br>
+tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher)<br>
add_public_tablegen_target(<u></u>AMDGPUCommonTableGen)<br>
<br>
add_llvm_target(R600CodeGen<br>
@@ -54,6 +55,7 @@ add_llvm_target(R600CodeGen<br>
SITypeRewriter.cpp<br>
)<br>
<br>
+add_subdirectory(AsmParser)<br>
add_subdirectory(InstPrinter)<br>
add_subdirectory(TargetInfo)<br>
add_subdirectory(MCTargetDesc)<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/LLVMBuild.txt?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/LLVMBuild.txt?rev=221994&<u></u>r1=221993&r2=221994&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>LLVMBuild.txt Fri Nov 14 08:08:00 2014<br>
@@ -16,17 +16,18 @@<br>
;===--------------------------<u></u>------------------------------<u></u>----------------===;<br>
<br>
[common]<br>
-subdirectories = InstPrinter MCTargetDesc TargetInfo<br>
+subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo<br>
<br>
[component_0]<br>
type = TargetGroup<br>
name = R600<br>
parent = Target<br>
+has_asmparser = 1<br>
has_asmprinter = 1<br>
<br>
[component_1]<br>
type = Library<br>
name = R600CodeGen<br>
parent = R600<br>
-required_libraries = Analysis AsmPrinter CodeGen Core IPO MC R600AsmPrinter R600Desc R600Info Scalar SelectionDAG Support Target TransformUtils<br>
+required_libraries = Analysis AsmPrinter CodeGen Core IPO MC R600AsmParser R600AsmPrinter R600Desc R600Info Scalar SelectionDAG Support Target TransformUtils<br>
add_to_library_groups = R600<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/Makefile?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/Makefile?rev=221994&r1=<u></u>221993&r2=221994&view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>Makefile (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>Makefile Fri Nov 14 08:08:00 2014<br>
@@ -16,8 +16,8 @@ BUILT_SOURCES = AMDGPUGenRegisterInfo.in<br>
AMDGPUGenDAGISel.inc AMDGPUGenSubtargetInfo.inc \<br>
AMDGPUGenMCCodeEmitter.inc AMDGPUGenCallingConv.inc \<br>
AMDGPUGenIntrinsics.inc AMDGPUGenDFAPacketizer.inc \<br>
- AMDGPUGenAsmWriter.inc<br>
+ AMDGPUGenAsmWriter.inc AMDGPUGenAsmMatcher.inc<br>
<br>
-DIRS = InstPrinter TargetInfo MCTargetDesc<br>
+DIRS = AsmParser InstPrinter TargetInfo MCTargetDesc<br>
<br>
include $(LEVEL)/Makefile.common<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>R600InstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600InstrFormats.td?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/R600InstrFormats.td?rev=<u></u>221994&r1=221993&r2=221994&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>R600InstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>R600InstrFormats.td Fri Nov 14 08:08:00 2014<br>
@@ -38,6 +38,9 @@ class InstR600 <dag outs, dag ins, strin<br>
let Pattern = pattern;<br>
let Itinerary = itin;<br>
<br>
+ // No AsmMatcher support.<br>
+ let isCodeGenOnly = 1;<br>
+<br>
let TSFlags{4} = Trig;<br>
let TSFlags{5} = Op3;<br>
<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>R600Instructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Instructions.td?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/R600Instructions.td?rev=<u></u>221994&r1=221993&r2=221994&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>R600Instructions.td (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>R600Instructions.td Fri Nov 14 08:08:00 2014<br>
@@ -1496,6 +1496,7 @@ class ILFormat<dag outs, dag ins, string<br>
let mayLoad = 0;<br>
let mayStore = 0;<br>
let hasSideEffects = 0;<br>
+ let isCodeGenOnly = 1;<br>
}<br>
<br>
multiclass BranchConditional<SDNode Op, RegisterClass rci, RegisterClass rcf> {<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>SIInstrFormats.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstrFormats.td?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/SIInstrFormats.td?rev=<u></u>221994&r1=221993&r2=221994&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>SIInstrFormats.td (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>SIInstrFormats.td Fri Nov 14 08:08:00 2014<br>
@@ -204,12 +204,13 @@ class SOPK <bits<5> op, dag outs, dag in<br>
let UseNamedOperandTable = 1;<br>
}<br>
<br>
-class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :<br>
+class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :<br>
InstSI <(outs), ins, asm, pattern >, SOPPe <op> {<br>
<br>
let mayLoad = 0;<br>
let mayStore = 0;<br>
let hasSideEffects = 0;<br>
+ let isCodeGenOnly = 0;<br>
let SALU = 1;<br>
<br>
let UseNamedOperandTable = 1;<br>
<br>
Modified: llvm/trunk/lib/Target/R600/<u></u>SIInstructions.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/SIInstructions.td?rev=221994&r1=221993&r2=221994&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/lib/Target/<u></u>R600/SIInstructions.td?rev=<u></u>221994&r1=221993&r2=221994&<u></u>view=diff</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/lib/Target/R600/<u></u>SIInstructions.td (original)<br>
+++ llvm/trunk/lib/Target/R600/<u></u>SIInstructions.td Fri Nov 14 08:08:00 2014<br>
@@ -33,7 +33,15 @@ def isCI : Predicate<"Subtarget.getGener<br>
">= AMDGPUSubtarget::SEA_ISLANDS"><u></u>;<br>
def HasFlatAddressSpace : Predicate<"Subtarget.<u></u>hasFlatAddressSpace()">;<br>
<br>
-def WAIT_FLAG : InstFlag<"printWaitFlag">;<br>
+def SWaitMatchClass : AsmOperandClass {<br>
+ let Name = "SWaitCnt";<br>
+ let RenderMethod = "addImmOperands";<br>
+ let ParserMethod = "parseSWaitCntOps";<br>
+}<br>
+<br>
+def WAIT_FLAG : InstFlag<"printWaitFlag"> {<br>
+ let ParserMatchClass = SWaitMatchClass;<br>
+}<br>
<br>
let SubtargetPredicate = isSI in {<br>
<br>
@@ -371,7 +379,7 @@ def S_GETREG_REGRD_B32 : SOPK_32 <0x0000<br>
// SOPP Instructions<br>
//===-------------------------<u></u>------------------------------<u></u>---------------===//<br>
<br>
-def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16", []>;<br>
+def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;<br>
<br>
let isTerminator = 1 in {<br>
<br>
@@ -392,36 +400,31 @@ def S_BRANCH : SOPP <<br>
let DisableEncoding = "$scc" in {<br>
def S_CBRANCH_SCC0 : SOPP <<br>
0x00000004, (ins sopp_brtarget:$simm16, SCCReg:$scc),<br>
- "s_cbranch_scc0 $simm16", []<br>
+ "s_cbranch_scc0 $simm16"<br>
>;<br>
def S_CBRANCH_SCC1 : SOPP <<br>
0x00000005, (ins sopp_brtarget:$simm16, SCCReg:$scc),<br>
- "s_cbranch_scc1 $simm16",<br>
- []<br>
+ "s_cbranch_scc1 $simm16"<br>
>;<br>
} // End DisableEncoding = "$scc"<br>
<br>
def S_CBRANCH_VCCZ : SOPP <<br>
0x00000006, (ins sopp_brtarget:$simm16, VCCReg:$vcc),<br>
- "s_cbranch_vccz $simm16",<br>
- []<br>
+ "s_cbranch_vccz $simm16"<br>
>;<br>
def S_CBRANCH_VCCNZ : SOPP <<br>
0x00000007, (ins sopp_brtarget:$simm16, VCCReg:$vcc),<br>
- "s_cbranch_vccnz $simm16",<br>
- []<br>
+ "s_cbranch_vccnz $simm16"<br>
>;<br>
<br>
let DisableEncoding = "$exec" in {<br>
def S_CBRANCH_EXECZ : SOPP <<br>
0x00000008, (ins sopp_brtarget:$simm16, EXECReg:$exec),<br>
- "s_cbranch_execz $simm16",<br>
- []<br>
+ "s_cbranch_execz $simm16"<br>
>;<br>
def S_CBRANCH_EXECNZ : SOPP <<br>
0x00000009, (ins sopp_brtarget:$simm16, EXECReg:$exec),<br>
- "s_cbranch_execnz $simm16",<br>
- []<br>
+ "s_cbranch_execnz $simm16"<br>
>;<br>
} // End DisableEncoding = "$exec"<br>
<br>
@@ -440,12 +443,10 @@ def S_BARRIER : SOPP <0x0000000a, (ins),<br>
let mayStore = 1;<br>
}<br>
<br>
-def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16",<br>
- []<br>
->;<br>
-//def S_SETHALT : SOPP_ <0x0000000d, "s_sethalt", []>;<br>
-//def S_SLEEP : SOPP_ <0x0000000e, "s_sleep", []>;<br>
-//def S_SETPRIO : SOPP_ <0x0000000f, "s_setprio", []>;<br>
+def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;<br>
+def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;<br>
+def S_SLEEP : SOPP <0x0000000e, (ins i16imm:$simm16), "s_sleep $simm16">;<br>
+def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">;<br>
<br>
let Uses = [EXEC] in {<br>
def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "s_sendmsg $simm16",<br>
@@ -455,12 +456,16 @@ let Uses = [EXEC] in {<br>
}<br>
} // End Uses = [EXEC]<br>
<br>
-//def S_SENDMSGHALT : SOPP_ <0x00000011, "s_sendmsghalt", []>;<br>
-//def S_TRAP : SOPP_ <0x00000012, "s_trap", []>;<br>
-//def S_ICACHE_INV : SOPP_ <0x00000013, "s_icache_inv", []>;<br>
-//def S_INCPERFLEVEL : SOPP_ <0x00000014, "s_incperflevel", []>;<br>
-//def S_DECPERFLEVEL : SOPP_ <0x00000015, "s_decperflevel", []>;<br>
-//def S_TTRACEDATA : SOPP_ <0x00000016, "s_ttracedata", []>;<br>
+def S_SENDMSGHALT : SOPP <0x00000011, (ins i16imm:$simm16), "s_sendmsghalt $simm16">;<br>
+def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;<br>
+def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {<br>
+ let simm16 = 0;<br>
+}<br>
+def S_INCPERFLEVEL : SOPP <0x00000014, (ins i16imm:$simm16), "s_incperflevel $simm16">;<br>
+def S_DECPERFLEVEL : SOPP <0x00000015, (ins i16imm:$simm16), "s_decperflevel $simm16">;<br>
+def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {<br>
+ let simm16 = 0;<br>
+}<br>
} // End hasSideEffects<br>
<br>
//===-------------------------<u></u>------------------------------<u></u>---------------===//<br>
<br>
Added: llvm/trunk/test/MC/R600/lit.<u></u>local.cfg<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/R600/lit.local.cfg?rev=221994&view=auto" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/test/MC/<u></u>R600/lit.local.cfg?rev=221994&<u></u>view=auto</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/test/MC/R600/lit.<u></u>local.cfg (added)<br>
+++ llvm/trunk/test/MC/R600/lit.<u></u>local.cfg Fri Nov 14 08:08:00 2014<br>
@@ -0,0 +1,2 @@<br>
+if not 'R600' in config.root.targets:<br>
+ config.unsupported = True<br>
<br>
Added: llvm/trunk/test/MC/R600/sopp.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/R600/sopp.s?rev=221994&view=auto" target="_blank">http://llvm.org/viewvc/llvm-<u></u>project/llvm/trunk/test/MC/<u></u>R600/sopp.s?rev=221994&view=<u></u>auto</a><br>
==============================<u></u>==============================<u></u>==================<br>
--- llvm/trunk/test/MC/R600/sopp.s (added)<br>
+++ llvm/trunk/test/MC/R600/sopp.s Fri Nov 14 08:08:00 2014<br>
@@ -0,0 +1,52 @@<br>
+// RUN: llvm-mc -arch=r600 -mcpu=SI -show-encoding %s | FileCheck %s<br>
+<br>
+ s_nop 1 // CHECK: s_nop 1 ; encoding: [0x01,0x00,0x80,0xbf]<br>
+ s_endpgm // CHECK: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]<br>
+ s_branch 2 // CHECK: s_branch 2 ; encoding: [0x02,0x00,0x82,0xbf]<br>
+ s_cbranch_scc0 3 // CHECK: s_cbranch_scc0 3 ; encoding: [0x03,0x00,0x84,0xbf]<br>
+ s_cbranch_scc1 4 // CHECK: s_cbranch_scc1 4 ; encoding: [0x04,0x00,0x85,0xbf]<br>
+ s_cbranch_vccz 5 // CHECK: s_cbranch_vccz 5 ; encoding: [0x05,0x00,0x86,0xbf]<br>
+ s_cbranch_vccnz 6 // CHECK: s_cbranch_vccnz 6 ; encoding: [0x06,0x00,0x87,0xbf]<br>
+ s_cbranch_execz 7 // CHECK: s_cbranch_execz 7 ; encoding: [0x07,0x00,0x88,0xbf]<br>
+ s_cbranch_execnz 8 // CHECK: s_cbranch_execnz 8 ; encoding: [0x08,0x00,0x89,0xbf]<br>
+ s_barrier // CHECK: s_barrier ; encoding: [0x00,0x00,0x8a,0xbf]<br>
+<br>
+//===------------------------<u></u>------------------------------<u></u>----------------===//<br>
+// s_waitcnt<br>
+//===------------------------<u></u>------------------------------<u></u>----------------===//<br>
+<br>
+ s_waitcnt 0<br>
+ // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]<br>
+<br>
+ s_waitcnt vmcnt(0) & expcnt(0) & lgkmcnt(0)<br>
+ // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]<br>
+<br>
+ s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)<br>
+ // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]<br>
+<br>
+ s_waitcnt vmcnt(0), expcnt(0), lgkmcnt(0)<br>
+ // CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]<br>
+<br>
+ s_waitcnt vmcnt(1)<br>
+ // CHECK: s_waitcnt vmcnt(1) ; encoding: [0x71,0x07,0x8c,0xbf]<br>
+<br>
+ s_waitcnt expcnt(2)<br>
+ // CHECK: s_waitcnt expcnt(2) ; encoding: [0x2f,0x07,0x8c,0xbf]<br>
+<br>
+ s_waitcnt lgkmcnt(3)<br>
+ // CHECK: s_waitcnt lgkmcnt(3) ; encoding: [0x7f,0x03,0x8c,0xbf]<br>
+<br>
+ s_waitcnt vmcnt(0), expcnt(0)<br>
+ // CHECK: s_waitcnt vmcnt(0) expcnt(0) ; encoding: [0x00,0x07,0x8c,0xbf]<br>
+<br>
+<br>
+ s_sethalt 9 // CHECK: s_sethalt 9 ; encoding: [0x09,0x00,0x8d,0xbf]<br>
+ s_sleep 10 // CHECK: s_sleep 10 ; encoding: [0x0a,0x00,0x8e,0xbf]<br>
+ s_setprio 1 // CHECK: s_setprio 1 ; encoding: [0x01,0x00,0x8f,0xbf]<br>
+ s_sendmsg 2 // CHECK: s_sendmsg Gs(nop), [m0] ; encoding: [0x02,0x00,0x90,0xbf]<br>
+ s_sendmsghalt 3 // CHECK: s_sendmsghalt 3 ; encoding: [0x03,0x00,0x91,0xbf]<br>
+ s_trap 4 // CHECK: s_trap 4 ; encoding: [0x04,0x00,0x92,0xbf]<br>
+ s_icache_inv // CHECK: s_icache_inv ; encoding: [0x00,0x00,0x93,0xbf]<br>
+ s_incperflevel 5 // CHECK: s_incperflevel 5 ; encoding: [0x05,0x00,0x94,0xbf]<br>
+ s_decperflevel 6 // CHECK: s_decperflevel 6 ; encoding: [0x06,0x00,0x95,0xbf]<br>
+ s_ttracedata // CHECK: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf]<br>
<br>
<br>
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