<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Nov 13, 2014 at 4:40 PM, Reid Kleckner <span dir="ltr"><<a href="mailto:rnk@google.com" target="_blank">rnk@google.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr">Please don't use GCC-specific features like __attribute__ directly. Use the portability macros in llvm/Support/Compiler.h, as in r221956.</div></blockquote><div><br>Why are these marked as unused anyway - if they're unused they should just be deleted, yes? (question more to Reed than Reid)<br> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Thu, Nov 13, 2014 at 3:37 PM, Reed Kotler <span dir="ltr"><<a href="mailto:rkotler@mips.com" target="_blank">rkotler@mips.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rkotler<br>
Date: Thu Nov 13 17:37:45 2014<br>
New Revision: 221948<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=221948&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=221948&view=rev</a><br>
Log:<br>
First stage of call lowering for Mips fast-isel<br>
<br>
Summary:<br>
This has most of what is needed for mips fast-isel call lowering for O32.<br>
What is missing I will add on the next patch because this patch is already too large.<br>
It should not be doing anything wrong but it will punt on some cases that it is basically<br>
capable of doing.<br>
<br>
The mechanism is there for parameters to be passed on the stack but I have not enabled it because it serves as a way for now to prevent some of the strange cases of O32 register passing that I have not fully checked yet and have some issues.<br>
<br>
The Mips O32 abi rules are very complicated as far how data is passed in floating and integer registers.<br>
<br>
However there is a way to think about this all very simply and this implementation reflects that.<br>
<br>
Basically, the ABI rules are written as if everything is passed on the stack and aligned as such.<br>
Once that is conceptually done, it is nearly trivial to reassign those locations to registers and<br>
then all the complexity disappears.<br>
<br>
So I have told tablegen that all the data is passed on the stack and during the lowering I fix<br>
this by assigning to registers as per the ABI doc.<br>
<br>
This has been my approach and you can line up what I did with the ABI document and see 1 to 1 what<br>
is going on.<br>
<br>
<br>
<br>
Test Plan: callabi.ll<br>
<br>
Reviewers: dsanders<br>
<br>
Reviewed By: dsanders<br>
<br>
Subscribers: jholewinski, echristo, ahatanak, llvm-commits, rfuhler<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D5714" target="_blank">http://reviews.llvm.org/D5714</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll<br>
Modified:<br>
llvm/trunk/lib/Target/Mips/MipsCallingConv.td<br>
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp<br>
llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsCallingConv.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCallingConv.td?rev=221948&r1=221947&r2=221948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCallingConv.td?rev=221948&r1=221947&r2=221948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsCallingConv.td (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsCallingConv.td Thu Nov 13 17:37:45 2014<br>
@@ -51,6 +51,19 @@ def RetCC_F128 : CallingConv<[<br>
// Mips O32 Calling Convention<br>
//===----------------------------------------------------------------------===//<br>
<br>
+def CC_MipsO32 : CallingConv<[<br>
+ // Promote i8/i16 arguments to i32.<br>
+ CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,<br>
+<br>
+ // Integer values get stored in stack slots that are 4 bytes in<br>
+ // size and 4-byte aligned.<br>
+ CCIfType<[i32, f32], CCAssignToStack<4, 4>>,<br>
+<br>
+ // Integer values get stored in stack slots that are 8 bytes in<br>
+ // size and 8-byte aligned.<br>
+ CCIfType<[f64], CCAssignToStack<8, 8>><br>
+]>;<br>
+<br>
// Only the return rules are defined here for O32. The rules for argument<br>
// passing are defined in MipsISelLowering.cpp.<br>
def RetCC_MipsO32 : CallingConv<[<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=221948&r1=221947&r2=221948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=221948&r1=221947&r2=221948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Thu Nov 13 17:37:45 2014<br>
@@ -8,6 +8,7 @@<br>
#include "llvm/IR/GlobalVariable.h"<br>
#include "llvm/Target/TargetInstrInfo.h"<br>
#include "llvm/Target/TargetLibraryInfo.h"<br>
+#include "MipsCCState.h"<br>
#include "MipsRegisterInfo.h"<br>
#include "MipsISelLowering.h"<br>
#include "MipsMachineFunction.h"<br>
@@ -68,6 +69,8 @@ class MipsFastISel final : public FastIS<br>
// Convenience variables to avoid some queries.<br>
LLVMContext *Context;<br>
<br>
+ bool fastLowerCall(CallLoweringInfo &CLI) override;<br>
+<br>
bool TargetSupported;<br>
bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle<br>
// floating point but not reject doing fast-isel in other<br>
@@ -87,17 +90,20 @@ private:<br>
bool selectIntExt(const Instruction *I);<br>
<br>
// Utility helper routines.<br>
-<br>
bool isTypeLegal(Type *Ty, MVT &VT);<br>
bool isLoadTypeLegal(Type *Ty, MVT &VT);<br>
bool computeAddress(const Value *Obj, Address &Addr);<br>
+ bool computeCallAddress(const Value *V, Address &Addr);<br>
<br>
// Emit helper routines.<br>
bool emitCmp(unsigned DestReg, const CmpInst *CI);<br>
bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,<br>
unsigned Alignment = 0);<br>
+ bool emitStore(MVT VT, unsigned SrcReg, Address Addr,<br>
+ MachineMemOperand *MMO = nullptr);<br>
bool emitStore(MVT VT, unsigned SrcReg, Address &Addr,<br>
unsigned Alignment = 0);<br>
+ unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);<br>
bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,<br>
<br>
bool IsZExt);<br>
@@ -140,9 +146,15 @@ private:<br>
return 0;<br>
}<br>
<br>
+ // Call handling routines.<br>
+private:<br>
+ CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;<br>
+ bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,<br>
+ unsigned &NumBytes);<br>
+ bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);<br>
+<br>
public:<br>
// Backend specific FastISel code.<br>
-<br>
explicit MipsFastISel(FunctionLoweringInfo &funcInfo,<br>
const TargetLibraryInfo *libInfo)<br>
: FastISel(funcInfo, libInfo),<br>
@@ -166,6 +178,28 @@ public:<br>
};<br>
} // end anonymous namespace.<br>
<br>
+static bool CC_Mips(unsigned ValNo, MVT ValVT, MVT LocVT,<br>
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,<br>
+ CCState &State) __attribute__((unused));<br>
+<br>
+static bool CC_MipsO32_FP32(unsigned ValNo, MVT ValVT, MVT LocVT,<br>
+ CCValAssign::LocInfo LocInfo,<br>
+ ISD::ArgFlagsTy ArgFlags, CCState &State) {<br>
+ llvm_unreachable("should not be called");<br>
+}<br>
+<br>
+bool CC_MipsO32_FP64(unsigned ValNo, MVT ValVT, MVT LocVT,<br>
+ CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,<br>
+ CCState &State) {<br>
+ llvm_unreachable("should not be called");<br>
+}<br>
+<br>
+#include "MipsGenCallingConv.inc"<br>
+<br>
+CCAssignFn *MipsFastISel::CCAssignFnForCall(CallingConv::ID CC) const {<br>
+ return CC_MipsO32;<br>
+}<br>
+<br>
unsigned MipsFastISel::materializeInt(const Constant *C, MVT VT) {<br>
if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)<br>
return 0;<br>
@@ -284,6 +318,19 @@ bool MipsFastISel::computeAddress(const<br>
return Addr.getReg() != 0;<br>
}<br>
<br>
+bool MipsFastISel::computeCallAddress(const Value *V, Address &Addr) {<br>
+ const GlobalValue *GV = dyn_cast<GlobalValue>(V);<br>
+ if (GV && isa<Function>(GV) && dyn_cast<Function>(GV)->isIntrinsic())<br>
+ return false;<br>
+ if (!GV)<br>
+ return false;<br>
+ if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) {<br>
+ Addr.setGlobalValue(GV);<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
bool MipsFastISel::isTypeLegal(Type *Ty, MVT &VT) {<br>
EVT evt = TLI.getValueType(Ty, true);<br>
// Only handle simple types.<br>
@@ -694,6 +741,250 @@ bool MipsFastISel::selectFPToInt(const I<br>
return true;<br>
}<br>
//<br>
+bool MipsFastISel::processCallArgs(CallLoweringInfo &CLI,<br>
+ SmallVectorImpl<MVT> &OutVTs,<br>
+ unsigned &NumBytes) {<br>
+ CallingConv::ID CC = CLI.CallConv;<br>
+ SmallVector<CCValAssign, 16> ArgLocs;<br>
+ CCState CCInfo(CC, false, *FuncInfo.MF, ArgLocs, *Context);<br>
+ CCInfo.AnalyzeCallOperands(OutVTs, CLI.OutFlags, CCAssignFnForCall(CC));<br>
+ // Get a count of how many bytes are to be pushed on the stack.<br>
+ NumBytes = CCInfo.getNextStackOffset();<br>
+ // This is the minimum argument area used for A0-A3.<br>
+ if (NumBytes < 16)<br>
+ NumBytes = 16;<br>
+<br>
+ emitInst(Mips::ADJCALLSTACKDOWN).addImm(16);<br>
+ // Process the args.<br>
+ MVT firstMVT;<br>
+ for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {<br>
+ CCValAssign &VA = ArgLocs[i];<br>
+ const Value *ArgVal = CLI.OutVals[VA.getValNo()];<br>
+ MVT ArgVT = OutVTs[VA.getValNo()];<br>
+<br>
+ if (i == 0) {<br>
+ firstMVT = ArgVT;<br>
+ if (ArgVT == MVT::f32) {<br>
+ VA.convertToReg(Mips::F12);<br>
+ } else if (ArgVT == MVT::f64) {<br>
+ VA.convertToReg(Mips::D6);<br>
+ }<br>
+ } else if (i == 1) {<br>
+ if ((firstMVT == MVT::f32) || (firstMVT == MVT::f64)) {<br>
+ if (ArgVT == MVT::f32) {<br>
+ VA.convertToReg(Mips::F14);<br>
+ } else if (ArgVT == MVT::f64) {<br>
+ VA.convertToReg(Mips::D7);<br>
+ }<br>
+ }<br>
+ }<br>
+ if (((ArgVT == MVT::i32) || (ArgVT == MVT::f32)) && VA.isMemLoc()) {<br>
+ switch (VA.getLocMemOffset()) {<br>
+ case 0:<br>
+ VA.convertToReg(Mips::A0);<br>
+ break;<br>
+ case 4:<br>
+ VA.convertToReg(Mips::A1);<br>
+ break;<br>
+ case 8:<br>
+ VA.convertToReg(Mips::A2);<br>
+ break;<br>
+ case 12:<br>
+ VA.convertToReg(Mips::A3);<br>
+ break;<br>
+ default:<br>
+ break;<br>
+ }<br>
+ }<br>
+ unsigned ArgReg = getRegForValue(ArgVal);<br>
+ if (!ArgReg)<br>
+ return false;<br>
+<br>
+ // Handle arg promotion: SExt, ZExt, AExt.<br>
+ switch (VA.getLocInfo()) {<br>
+ case CCValAssign::Full:<br>
+ break;<br>
+ case CCValAssign::AExt:<br>
+ case CCValAssign::SExt: {<br>
+ MVT DestVT = VA.getLocVT();<br>
+ MVT SrcVT = ArgVT;<br>
+ ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);<br>
+ if (!ArgReg)<br>
+ return false;<br>
+ break;<br>
+ }<br>
+ case CCValAssign::ZExt: {<br>
+ MVT DestVT = VA.getLocVT();<br>
+ MVT SrcVT = ArgVT;<br>
+ ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);<br>
+ if (!ArgReg)<br>
+ return false;<br>
+ break;<br>
+ }<br>
+ default:<br>
+ llvm_unreachable("Unknown arg promotion!");<br>
+ }<br>
+<br>
+ // Now copy/store arg to correct locations.<br>
+ if (VA.isRegLoc() && !VA.needsCustom()) {<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br>
+ TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);<br>
+ CLI.OutRegs.push_back(VA.getLocReg());<br>
+ } else if (VA.needsCustom()) {<br>
+ llvm_unreachable("Mips does not use custom args.");<br>
+ return false;<br>
+ } else {<br>
+ //<br>
+ // FIXME: This path will currently return false. It was copied<br>
+ // from the AArch64 port and should be essentially fine for Mips too.<br>
+ // The work to finish up this path will be done in a follow-on patch.<br>
+ //<br>
+ assert(VA.isMemLoc() && "Assuming store on stack.");<br>
+ // Don't emit stores for undef values.<br>
+ if (isa<UndefValue>(ArgVal))<br>
+ continue;<br>
+<br>
+ // Need to store on the stack.<br>
+ // FIXME: This alignment is incorrect but this path is disabled<br>
+ // for now (will return false). We need to determine the right alignment<br>
+ // based on the normal alignment for the underlying machine type.<br>
+ //<br>
+ unsigned ArgSize = RoundUpToAlignment(ArgVT.getSizeInBits(), 4);<br>
+<br>
+ unsigned BEAlign = 0;<br>
+ if (ArgSize < 8 && !Subtarget->isLittle())<br>
+ BEAlign = 8 - ArgSize;<br>
+<br>
+ Address Addr;<br>
+ Addr.setKind(Address::RegBase);<br>
+ Addr.setReg(Mips::SP);<br>
+ Addr.setOffset(VA.getLocMemOffset() + BEAlign);<br>
+<br>
+ unsigned Alignment = DL.getABITypeAlignment(ArgVal->getType());<br>
+ MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand(<br>
+ MachinePointerInfo::getStack(Addr.getOffset()),<br>
+ MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);<br>
+ (void)(MMO);<br>
+ // if (!emitStore(ArgVT, ArgReg, Addr, MMO))<br>
+ return false; // can't store on the stack yet.<br>
+ }<br>
+ }<br>
+<br>
+ return true;<br>
+}<br>
+<br>
+bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,<br>
+ unsigned NumBytes) {<br>
+ CallingConv::ID CC = CLI.CallConv;<br>
+ emitInst(Mips::ADJCALLSTACKUP).addImm(16);<br>
+ if (RetVT != MVT::isVoid) {<br>
+ SmallVector<CCValAssign, 16> RVLocs;<br>
+ CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);<br>
+ CCInfo.AnalyzeCallResult(RetVT, RetCC_Mips);<br>
+<br>
+ // Only handle a single return value.<br>
+ if (RVLocs.size() != 1)<br>
+ return false;<br>
+ // Copy all of the result registers out of their specified physreg.<br>
+ MVT CopyVT = RVLocs[0].getValVT();<br>
+ // Special handling for extended integers.<br>
+ if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16)<br>
+ CopyVT = MVT::i32;<br>
+<br>
+ unsigned ResultReg = createResultReg(TLI.getRegClassFor(CopyVT));<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,<br>
+ TII.get(TargetOpcode::COPY),<br>
+ ResultReg).addReg(RVLocs[0].getLocReg());<br>
+ CLI.InRegs.push_back(RVLocs[0].getLocReg());<br>
+<br>
+ CLI.ResultReg = ResultReg;<br>
+ CLI.NumResultRegs = 1;<br>
+ }<br>
+ return true;<br>
+}<br>
+<br>
+bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) {<br>
+ CallingConv::ID CC = CLI.CallConv;<br>
+ bool IsTailCall = CLI.IsTailCall;<br>
+ bool IsVarArg = CLI.IsVarArg;<br>
+ const Value *Callee = CLI.Callee;<br>
+ // const char *SymName = CLI.SymName;<br>
+<br>
+ // Allow SelectionDAG isel to handle tail calls.<br>
+ if (IsTailCall)<br>
+ return false;<br>
+<br>
+ // Let SDISel handle vararg functions.<br>
+ if (IsVarArg)<br>
+ return false;<br>
+<br>
+ // FIXME: Only handle *simple* calls for now.<br>
+ MVT RetVT;<br>
+ if (CLI.RetTy->isVoidTy())<br>
+ RetVT = MVT::isVoid;<br>
+ else if (!isTypeLegal(CLI.RetTy, RetVT))<br>
+ return false;<br>
+<br>
+ for (auto Flag : CLI.OutFlags)<br>
+ if (Flag.isInReg() || Flag.isSRet() || Flag.isNest() || Flag.isByVal())<br>
+ return false;<br>
+<br>
+ // Set up the argument vectors.<br>
+ SmallVector<MVT, 16> OutVTs;<br>
+ OutVTs.reserve(CLI.OutVals.size());<br>
+<br>
+ for (auto *Val : CLI.OutVals) {<br>
+ MVT VT;<br>
+ if (!isTypeLegal(Val->getType(), VT) &&<br>
+ !(VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16))<br>
+ return false;<br>
+<br>
+ // We don't handle vector parameters yet.<br>
+ if (VT.isVector() || VT.getSizeInBits() > 64)<br>
+ return false;<br>
+<br>
+ OutVTs.push_back(VT);<br>
+ }<br>
+<br>
+ Address Addr;<br>
+ if (!computeCallAddress(Callee, Addr))<br>
+ return false;<br>
+<br>
+ // Handle the arguments now that we've gotten them.<br>
+ unsigned NumBytes;<br>
+ if (!processCallArgs(CLI, OutVTs, NumBytes))<br>
+ return false;<br>
+<br>
+ // Issue the call.<br>
+ unsigned DestAddress = materializeGV(Addr.getGlobalValue(), MVT::i32);<br>
+ emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);<br>
+ MachineInstrBuilder MIB =<br>
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),<br>
+ Mips::RA).addReg(Mips::T9);<br>
+<br>
+ // Add implicit physical register uses to the call.<br>
+ for (auto Reg : CLI.OutRegs)<br>
+ MIB.addReg(Reg, RegState::Implicit);<br>
+<br>
+ // Add a register mask with the call-preserved registers.<br>
+ // Proper defs for return values will be added by setPhysRegsDeadExcept().<br>
+ MIB.addRegMask(TRI.getCallPreservedMask(CC));<br>
+<br>
+ CLI.Call = MIB;<br>
+<br>
+ // Add implicit physical register uses to the call.<br>
+ for (auto Reg : CLI.OutRegs)<br>
+ MIB.addReg(Reg, RegState::Implicit);<br>
+<br>
+ // Add a register mask with the call-preserved registers. Proper<br>
+ // defs for return values will be added by setPhysRegsDeadExcept().<br>
+ MIB.addRegMask(TRI.getCallPreservedMask(CC));<br>
+<br>
+ CLI.Call = MIB;<br>
+ // Finish off the call including any return values.<br>
+ return finishCall(CLI, RetVT, NumBytes);<br>
+}<br>
+<br>
bool MipsFastISel::selectRet(const Instruction *I) {<br>
const ReturnInst *Ret = cast<ReturnInst>(I);<br>
<br>
@@ -812,6 +1103,7 @@ bool MipsFastISel::emitIntZExt(MVT SrcVT<br>
break;<br>
case MVT::i16:<br>
emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(0xffff);<br>
+ break;<br>
}<br>
return true;<br>
}<br>
@@ -822,6 +1114,13 @@ bool MipsFastISel::emitIntExt(MVT SrcVT,<br>
return emitIntZExt(SrcVT, SrcReg, DestVT, DestReg);<br>
return emitIntSExt(SrcVT, SrcReg, DestVT, DestReg);<br>
}<br>
+<br>
+unsigned MipsFastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,<br>
+ bool isZExt) {<br>
+ unsigned DestReg = createResultReg(&Mips::GPR32RegClass);<br>
+ return emitIntExt(SrcVT, SrcReg, DestVT, DestReg, isZExt);<br>
+}<br>
+<br>
bool MipsFastISel::fastSelectInstruction(const Instruction *I) {<br>
if (!TargetSupported)<br>
return false;<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=221948&r1=221947&r2=221948&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=221948&r1=221947&r2=221948&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu Nov 13 17:37:45 2014<br>
@@ -2356,6 +2356,11 @@ static bool CC_MipsO32_FP64(unsigned Val<br>
return CC_MipsO32(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State, F64Regs);<br>
}<br>
<br>
+static bool CC_MipsO32(unsigned ValNo, MVT ValVT,<br>
+ MVT LocVT, CCValAssign::LocInfo LocInfo,<br>
+ ISD::ArgFlagsTy ArgFlags, CCState &State)<br>
+__attribute__((unused));<br>
+<br>
#include "MipsGenCallingConv.inc"<br>
<br>
//===----------------------------------------------------------------------===//<br>
<br>
Added: llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=221948&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll?rev=221948&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll (added)<br>
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/callabi.ll Thu Nov 13 17:37:45 2014<br>
@@ -0,0 +1,477 @@<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \<br>
+; RUN: < %s | FileCheck %s<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \<br>
+; RUN: < %s | FileCheck %s<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \<br>
+; RUN: < %s | FileCheck %s -check-prefix=mips32r2<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \<br>
+; RUN: < %s | FileCheck %s -check-prefix=mips32<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \<br>
+; RUN: < %s | FileCheck %s -check-prefix=CHECK2<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \<br>
+; RUN: < %s | FileCheck %s -check-prefix=CHECK2<br>
+<br>
+<br>
+@c1 = global i8 -45, align 1<br>
+@uc1 = global i8 27, align 1<br>
+@s1 = global i16 -1789, align 2<br>
+@us1 = global i16 1256, align 2<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxi() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxi<br>
+ call void @xi(i32 10)<br>
+; CHECK-DAG: addiu $4, $zero, 10<br>
+; CHECK-DAG: lw $25, %got(xi)(${{[0-9]+}})<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xi(i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxii() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxii<br>
+ call void @xii(i32 746, i32 892)<br>
+; CHECK-DAG: addiu $4, $zero, 746<br>
+; CHECK-DAG: addiu $5, $zero, 892<br>
+; CHECK-DAG: lw $25, %got(xii)(${{[0-9]+}})<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xii(i32, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxiii() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxiii<br>
+ call void @xiii(i32 88, i32 44, i32 11)<br>
+; CHECK-DAG: addiu $4, $zero, 88<br>
+; CHECK-DAG: addiu $5, $zero, 44<br>
+; CHECK-DAG: addiu $6, $zero, 11<br>
+; CHECK-DAG: lw $25, %got(xiii)(${{[0-9]+}})<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xiii(i32, i32, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxiiii() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxiiii<br>
+ call void @xiiii(i32 167, i32 320, i32 97, i32 14)<br>
+; CHECK-DAG: addiu $4, $zero, 167<br>
+; CHECK-DAG: addiu $5, $zero, 320<br>
+; CHECK-DAG: addiu $6, $zero, 97<br>
+; CHECK-DAG: addiu $7, $zero, 14<br>
+; CHECK-DAG: lw $25, %got(xiiii)(${{[0-9]+}})<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xiiii(i32, i32, i32, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxiiiiconv() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxiiiiconv<br>
+; mips32r2-LABEL: cxiiiiconv<br>
+; mips32-LABEL: cxiiiiconv<br>
+ %0 = load i8* @c1, align 1<br>
+ %conv = sext i8 %0 to i32<br>
+ %1 = load i8* @uc1, align 1<br>
+ %conv1 = zext i8 %1 to i32<br>
+ %2 = load i16* @s1, align 2<br>
+ %conv2 = sext i16 %2 to i32<br>
+ %3 = load i16* @us1, align 2<br>
+ %conv3 = zext i16 %3 to i32<br>
+ call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32r2-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])<br>
+; mips32r2-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])<br>
+; mips32r2-DAG seb $3, $[[REG_C1]]<br>
+; mips32-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])<br>
+; mips32-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])<br>
+; mips32-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24<br>
+; mips32-DAG: sra $4, $[[REG_C1_1]], 24<br>
+; CHECK-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])<br>
+; CHECK-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])<br>
+; FIXME andi is superfulous<br>
+; CHECK-DAG: andi $5, $[[REG_UC1]], 255<br>
+; mips32r2-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])<br>
+; mips32r2-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])<br>
+; mips32r2-DAG: seh $6, $[[REG_S1]]<br>
+; mips32-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])<br>
+; mips32-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])<br>
+; mips32-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16<br>
+; mips32-DAG: sra $6, $[[REG_S1_1]], 16<br>
+; CHECK-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])<br>
+; CHECK-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])<br>
+; FIXME andi is superfulous<br>
+; CHECK-DAG: andi $7, $[[REG_US1]], 65535<br>
+; mips32r2: jalr $25<br>
+; mips32r2: jalr $25<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxf() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxf<br>
+ call void @xf(float 0x40BBC85560000000)<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK: lui $[[REG_FPCONST_1:[0-9]+]], 17886<br>
+; CHECK: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067<br>
+; CHECK: mtc1 $[[REG_FPCONST]], $f12<br>
+; CHECK: lw $25, %got(xf)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xf(float) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxff() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxff<br>
+ call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314<br>
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349<br>
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12<br>
+; CHECK-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593<br>
+; CHECK-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642<br>
+; CHECK-DAG: mtc1 $[[REG_FPCONST_3]], $f14<br>
+; CHECK: lw $25, %got(xff)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xff(float, float) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxfi() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxfi<br>
+ call void @xfi(float 0x4013906240000000, i32 102)<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540<br>
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554<br>
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12<br>
+; CHECK-DAG: addiu $5, $zero, 102<br>
+; CHECK: lw $25, %got(xfi)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xfi(float, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxfii() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxfii<br>
+ call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142<br>
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240<br>
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12<br>
+; CHECK-DAG: addiu $5, $zero, 9993<br>
+; CHECK-DAG: addiu $6, $zero, 10922<br>
+; CHECK: lw $25, %got(xfii)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xfii(float, i32, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxfiii() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxfiii<br>
+ call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120<br>
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681<br>
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12<br>
+; CHECK-DAG: addiu $5, $zero, 3948<br>
+; CHECK-DAG: lui $[[REG_I_1:[0-9]+]], 1<br>
+; CHECK-DAG: ori $6, $[[REG_I_1]], 23475<br>
+; CHECK-DAG: lui $[[REG_I_2:[0-9]+]], 1<br>
+; CHECK-DAG: ori $7, $[[REG_I_2]], 45686<br>
+; CHECK: lw $25, %got(xfiii)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xfiii(float, i32, i32, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxd() #0 {<br>
+entry:<br>
+; mips32r2-LABEL: cxd:<br>
+; mips32-LABEL: cxd:<br>
+ call void @xd(double 5.994560e+02)<br>
+; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514<br>
+; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037<br>
+; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195<br>
+; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439<br>
+; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12<br>
+; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13<br>
+; mips32-DAG: lw $25, %got(xd)($[[REG_GP]])<br>
+; mips32: jalr $25<br>
+; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514<br>
+; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037<br>
+; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195<br>
+; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439<br>
+; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12<br>
+; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12<br>
+; mips32r2-DAG: lw $25, %got(xd)($[[REG_GP]])<br>
+; mips32r2 : jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xd(double) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxdd() #0 {<br>
+; mips32r2-LABEL: cxdd:<br>
+; mips32-LABEL: cxdd:<br>
+entry:<br>
+ call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)<br>
+; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531<br>
+; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435<br>
+; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078<br>
+; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186<br>
+; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12<br>
+; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13<br>
+; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629<br>
+; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873<br>
+; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438<br>
+; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575<br>
+; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f14<br>
+; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f15<br>
+; mips32-DAG: lw $25, %got(xdd)($[[REG_GP]])<br>
+; mips32: jalr $25<br>
+; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531<br>
+; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435<br>
+; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078<br>
+; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186<br>
+; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12<br>
+; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12<br>
+; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629<br>
+; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873<br>
+; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438<br>
+; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575<br>
+; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f14<br>
+; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f14<br>
+; mips32r2-DAG: lw $25, %got(xdd)($[[REG_GP]])<br>
+; mips32r2 : jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xdd(double, double) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxif() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxif:<br>
+ call void @xif(i32 345, float 0x407BCE5A20000000)<br>
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: addiu $4, $zero, 345<br>
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17374<br>
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393<br>
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]<br>
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]<br>
+; CHECK-DAG: lw $25, %got(xif)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xif(i32, float) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxiff() #0 {<br>
+entry:<br>
+; CHECK-LABEL: cxiff:<br>
+; CHECK2-LABEL: cxiff:<br>
+ call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)<br>
+; We need to do the two floating point parameters in a separate<br>
+; check because we can't control the ordering of parts of the sequence<br>
+;;<br>
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK: addiu $4, $zero, 12239<br>
+; CHECK2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK2: addiu $4, $zero, 12239<br>
+; CHECK: lui $[[REGF_1:[0-9]+]], 17526<br>
+; CHECK: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706<br>
+; CHECK: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]<br>
+; CHECK: mfc1 $5, $f[[REGF_3]]<br>
+; CHECK2: lui $[[REGF2_1:[0-9]+]], 16543<br>
+; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 65326<br>
+; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]<br>
+; CHECK2: mfc1 $6, $f[[REGF2_3]]<br>
+; CHECK: lw $25, %got(xiff)($[[REG_GP]])<br>
+; CHECK2: lw $25, %got(xiff)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+; CHECK2: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xiff(i32, float, float) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxifi() #0 {<br>
+entry:<br>
+; CHECK: cxifi:<br>
+ call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)<br>
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: addiu $4, $zero, 887<br>
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16659<br>
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759<br>
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]<br>
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]<br>
+; CHECk-DAG: addiu $6, $zero, 888<br>
+; CHECK-DAG: lw $25, %got(xifi)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xifi(i32, float, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxifif() #0 {<br>
+entry:<br>
+; CHECK: cxifif:<br>
+; CHECK2: cxifif:<br>
+ call void @xifif(i32 67774, float 0x408EE0FBE0000000, i32 9991, float 0x40B15C8CC0000000)<br>
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: lui $[[REGI:[0-9]+]], 1<br>
+; CHECK-DAG: ori $4, $[[REGI]], 2238<br>
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17527<br>
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 2015<br>
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]<br>
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]<br>
+; CHECk-DAG: addiu $6, $zero, 888<br>
+; CHECK2: lui $[[REGF2_1:[0-9]+]], 17802<br>
+; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 58470<br>
+; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]<br>
+; CHECK2: mfc1 $7, $f[[REGF2_3]]<br>
+; CHECK: lw $25, %got(xifif)($[[REG_GP]])<br>
+; CHECK2: lw $25, %got(xifif)($[[REG_GP]])<br>
+; CHECK2: jalr $25<br>
+; CHECK: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xifif(i32, float, i32, float) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxiffi() #0 {<br>
+entry:<br>
+; CHECK-label: cxiffi:<br>
+; CHECK2-label: cxiffi:<br>
+ call void @xiffi(i32 45, float 0x3FF6666660000000, float 0x408F333340000000, i32 234)<br>
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: addiu $4, $zero, 45<br>
+; CHECK2-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK2-DAG: addiu $4, $zero, 45<br>
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16307<br>
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 13107<br>
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]<br>
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]<br>
+; CHECK2: lui $[[REGF2_1:[0-9]+]], 17529<br>
+; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 39322<br>
+; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]<br>
+; CHECK2: mfc1 $6, $f[[REGF2_3]]<br>
+; CHECK-DAG: lw $25, %got(xiffi)($[[REG_GP]])<br>
+; CHECK-DAG: addiu $7, $zero, 234<br>
+; CHECK2-DAG: lw $25, %got(xiffi)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+; CHECK2: jalr $25<br>
+<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xiffi(i32, float, float, i32) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @cxifii() #0 {<br>
+entry:<br>
+; CHECK-DAG: cxifii:<br>
+ call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)<br>
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}<br>
+; CHECK-DAG: addiu $4, $zero, 12239<br>
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17526<br>
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706<br>
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]<br>
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]<br>
+; CHECK-DAG: lui $[[REGI2:[0-9]+]], 15<br>
+; CHECK-DAG: ori $6, $[[REGI2]], 15837<br>
+; CHECk-DAG: addiu $7, $zero, 1234<br>
+; CHECK-DAG: lw $25, %got(xifii)($[[REG_GP]])<br>
+; CHECK: jalr $25<br>
+ ret void<br>
+}<br>
+<br>
+declare void @xifii(i32, float, i32, i32) #1<br>
+<br>
+; FIXME: this function will not pass yet.<br>
+; Function Attrs: nounwind<br>
+; define void @cxfid() #0 {<br>
+;entry:<br>
+; call void @xfid(float 0x4013B851E0000000, i32 811123, double 0x40934BFF487FCB92)<br>
+; ret void<br>
+;}<br>
+<br>
+declare void @xfid(float, i32, double) #1<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @g() #0 {<br>
+entry:<br>
+ call void @cxi()<br>
+ call void @cxii()<br>
+ call void @cxiii()<br>
+ call void @cxiiii()<br>
+ call void @cxiiiiconv()<br>
+ call void @cxf()<br>
+ call void @cxff()<br>
+ call void @cxd()<br>
+ call void @cxfi()<br>
+ call void @cxfii()<br>
+ call void @cxfiii()<br>
+ call void @cxdd()<br>
+ call void @cxif()<br>
+ call void @cxiff()<br>
+ call void @cxifi()<br>
+ call void @cxifii()<br>
+ call void @cxifif()<br>
+ call void @cxiffi()<br>
+ ret void<br>
+}<br>
+<br>
+<br>
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }<br>
+<br>
+!llvm.ident = !{!0}<br>
+<br>
+!0 = metadata !{metadata !"clang version 3.6.0 (gitosis@dmz-portal.mips.com:clang 43992fe7b17de5553ac06d323cb80cc6723a9ae3) (gitosis@dmz-portal.mips.com:llvm.git 0834e6839eb170197c81bb02e916258d1527e312)"}<br>
<br>
<br>
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