<div dir="ltr">Hi Elena,<div><br></div><div>There doesn't seem to be a change to LangRef here. Could you please briefly describe the semantics of masked load and store intrinsics?</div><div><br></div><div>We have strided load/store instructions in NEON that could be modelled with them, depending on their semantics.</div><div><br></div><div>Cheers,</div><div><br></div><div>James</div></div><div class="gmail_extra"><br><div class="gmail_quote">On 10 November 2014 13:19, Elena Demikhovsky <span dir="ltr"><<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Hi anemet, hfinkel, rob.khasanov, resistor,<br>
<br>
Introduced new target-independent intrinsics in order to support masked vector loads and stores. The loop vectorizer optimizes loops containing conditional memory accesses by generating these intrinsics for existing targets AVX2 and AVX-512. The vectorizer asks the target about availability of masked vector loads and stores.<br>
Added SDNodes for masked operations and lowering patterns for X86 code generator.<br>
<br>
Scalarizer for other targets (not AVX2/AVX-512) will be done in a separate patch.<br>
<br>
<a href="http://reviews.llvm.org/D6191" target="_blank">http://reviews.llvm.org/D6191</a><br>
<br>
Files:<br>
  include/llvm/Analysis/TargetTransformInfo.h<br>
  include/llvm/CodeGen/ISDOpcodes.h<br>
  include/llvm/CodeGen/SelectionDAG.h<br>
  include/llvm/CodeGen/SelectionDAGNodes.h<br>
  include/llvm/IR/IRBuilder.h<br>
  include/llvm/IR/Intrinsics.h<br>
  include/llvm/IR/Intrinsics.td<br>
  include/llvm/Target/TargetSelectionDAG.td<br>
  lib/Analysis/TargetTransformInfo.cpp<br>
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp<br>
  lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp<br>
  lib/CodeGen/SelectionDAG/LegalizeTypes.h<br>
  lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp<br>
  lib/CodeGen/SelectionDAG/SelectionDAG.cpp<br>
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp<br>
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h<br>
  lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp<br>
  lib/IR/Function.cpp<br>
  lib/IR/IRBuilder.cpp<br>
  lib/IR/Verifier.cpp<br>
  lib/Target/X86/X86ISelLowering.cpp<br>
  lib/Target/X86/X86InstrAVX512.td<br>
  lib/Target/X86/X86InstrSSE.td<br>
  lib/Target/X86/X86TargetTransformInfo.cpp<br>
  lib/Transforms/Vectorize/LoopVectorize.cpp<br>
  test/CodeGen/X86/masked_memop.ll<br>
  test/Transforms/LoopVectorize/X86/mask1.ll<br>
  test/Transforms/LoopVectorize/X86/mask2.ll<br>
  test/Transforms/LoopVectorize/X86/mask3.ll<br>
  test/Transforms/LoopVectorize/X86/mask4.ll<br>
  utils/TableGen/CodeGenTarget.cpp<br>
  utils/TableGen/IntrinsicEmitter.cpp<br>
<br>_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
<br></blockquote></div><br></div>