<div dir="ltr">There's some problems with this code in the TwoAddressInstructionPass. I played around with fixing it a long time ago. Let me look at it again.<div><br></div><div>
<p class=""><span class=""> unsigned FromRegB = getMappedReg(regB, SrcRegMap);</span></p>
<p class=""><span class=""> unsigned FromRegC = getMappedReg(regC, SrcRegMap);</span></p>
<p class=""><span class=""> bool BComp = !FromRegB || regsAreCompatible(FromRegB, ToRegA, TRI);</span></p>
<p class=""><span class=""> bool CComp = !FromRegC || regsAreCompatible(FromRegC, ToRegA, TRI);</span></p>
<p class=""><span class=""> if (BComp != CComp)</span></p>
<p class=""><span class=""> return !BComp && CComp;</span></p></div></div><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Nov 4, 2014 at 7:27 PM, Sean Silva <span dir="ltr"><<a href="mailto:chisophugis@gmail.com" target="_blank">chisophugis@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir="ltr"><span class=""><div><span style="font-family:arial,sans-serif;font-size:13px">-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],</span><span style="font-family:arial,sans-serif;font-size:13px">xmm1[6,7]</span><br style="font-family:arial,sans-serif;font-size:13px"><span style="font-family:arial,sans-serif;font-size:13px">+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],</span><span style="font-family:arial,sans-serif;font-size:13px">xmm1[6,7]</span><br style="font-family:arial,sans-serif;font-size:13px"><span style="font-family:arial,sans-serif;font-size:13px">+; SSE41-NEXT: movdqa %xmm1, %xmm0</span><br></div><div><br></div></span>This is really interesting. Most of the test changes are "in the opposite direction", where this patch avoids emitting a reg-reg move (yay!). Do you know why the reverse is happening in this case?<span class="HOEnZb"><font color="#888888"><div><br></div><div>-- Sean Silva</div><div><br></div></font></span></div><div class="HOEnZb"><div class="h5"><div class="gmail_extra"><br><div class="gmail_quote">On Tue, Nov 4, 2014 at 3:25 PM, Simon Pilgrim <span dir="ltr"><<a href="mailto:llvm-dev@redking.me.uk" target="_blank">llvm-dev@redking.me.uk</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: rksimon<br>
Date: Tue Nov 4 17:25:08 2014<br>
New Revision: 221313<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=221313&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=221313&view=rev</a><br>
Log:<br>
[X86][SSE] Enable commutation for SSE immediate blend instructions<br>
<br>
Patch to allow (v)blendps, (v)blendpd, (v)pblendw and vpblendd instructions to be commuted - swaps the src registers and inverts the blend mask.<br>
<br>
This is primarily to improve memory folding (see new tests), but it also improves the quality of shuffles (see modified tests).<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D6015" target="_blank">http://reviews.llvm.org/D6015</a><br>
<br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/X86/commute-blend-avx2.ll<br>
llvm/trunk/test/CodeGen/X86/commute-blend-sse41.ll<br>
Modified:<br>
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
llvm/trunk/test/CodeGen/X86/combine-or.ll<br>
llvm/trunk/test/CodeGen/X86/vector-blend.ll<br>
llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v2.ll<br>
llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=221313&r1=221312&r2=221313&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=221313&r1=221312&r2=221313&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Nov 4 17:25:08 2014<br>
@@ -2420,6 +2420,41 @@ X86InstrInfo::commuteInstruction(Machine<br>
MI->getOperand(3).setImm(Size-Amt);<br>
return TargetInstrInfo::commuteInstruction(MI, NewMI);<br>
}<br>
+ case X86::BLENDPDrri:<br>
+ case X86::BLENDPSrri:<br>
+ case X86::PBLENDWrri:<br>
+ case X86::VBLENDPDrri:<br>
+ case X86::VBLENDPSrri:<br>
+ case X86::VBLENDPDYrri:<br>
+ case X86::VBLENDPSYrri:<br>
+ case X86::VPBLENDDrri:<br>
+ case X86::VPBLENDWrri:<br>
+ case X86::VPBLENDDYrri:<br>
+ case X86::VPBLENDWYrri:{<br>
+ unsigned Mask;<br>
+ switch (MI->getOpcode()) {<br>
+ default: llvm_unreachable("Unreachable!");<br>
+ case X86::BLENDPDrri: Mask = 0x03; break;<br>
+ case X86::BLENDPSrri: Mask = 0x0F; break;<br>
+ case X86::PBLENDWrri: Mask = 0xFF; break;<br>
+ case X86::VBLENDPDrri: Mask = 0x03; break;<br>
+ case X86::VBLENDPSrri: Mask = 0x0F; break;<br>
+ case X86::VBLENDPDYrri: Mask = 0x0F; break;<br>
+ case X86::VBLENDPSYrri: Mask = 0xFF; break;<br>
+ case X86::VPBLENDDrri: Mask = 0x0F; break;<br>
+ case X86::VPBLENDWrri: Mask = 0xFF; break;<br>
+ case X86::VPBLENDDYrri: Mask = 0xFF; break;<br>
+ case X86::VPBLENDWYrri: Mask = 0xFF; break;<br>
+ }<br>
+ unsigned Imm = MI->getOperand(3).getImm();<br>
+ if (NewMI) {<br>
+ MachineFunction &MF = *MI->getParent()->getParent();<br>
+ MI = MF.CloneMachineInstr(MI);<br>
+ NewMI = false;<br>
+ }<br>
+ MI->getOperand(3).setImm(Mask ^ Imm);<br>
+ return TargetInstrInfo::commuteInstruction(MI, NewMI);<br>
+ }<br>
case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:<br>
case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:<br>
case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:<br>
@@ -2504,6 +2539,20 @@ X86InstrInfo::commuteInstruction(Machine<br>
bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,<br>
unsigned &SrcOpIdx2) const {<br>
switch (MI->getOpcode()) {<br>
+ case X86::BLENDPDrri:<br>
+ case X86::BLENDPSrri:<br>
+ case X86::PBLENDWrri:<br>
+ case X86::VBLENDPDrri:<br>
+ case X86::VBLENDPSrri:<br>
+ case X86::VBLENDPDYrri:<br>
+ case X86::VBLENDPSYrri:<br>
+ case X86::VPBLENDDrri:<br>
+ case X86::VPBLENDDYrri:<br>
+ case X86::VPBLENDWrri:<br>
+ case X86::VPBLENDWYrri:<br>
+ SrcOpIdx1 = 1;<br>
+ SrcOpIdx2 = 2;<br>
+ return true;<br>
case X86::VFMADDPDr231r:<br>
case X86::VFMADDPSr231r:<br>
case X86::VFMADDSDr231r:<br>
<br>
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=221313&r1=221312&r2=221313&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=221313&r1=221312&r2=221313&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Nov 4 17:25:08 2014<br>
@@ -7537,31 +7537,33 @@ multiclass SS41I_binop_rmi_int<bits<8> o<br>
<br>
let Predicates = [HasAVX] in {<br>
let isCommutable = 0 in {<br>
- let ExeDomain = SSEPackedSingle in {<br>
- defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,<br>
- VR128, loadv4f32, f128mem, 0,<br>
- DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;<br>
- defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",<br>
- int_x86_avx_blend_ps_256, VR256, loadv8f32,<br>
- f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,<br>
- VEX_4V, VEX_L;<br>
- }<br>
- let ExeDomain = SSEPackedDouble in {<br>
- defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,<br>
- VR128, loadv2f64, f128mem, 0,<br>
- DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;<br>
- defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",<br>
- int_x86_avx_blend_pd_256,VR256, loadv4f64,<br>
- f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,<br>
- VEX_4V, VEX_L;<br>
- }<br>
+ defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,<br>
+ VR128, loadv2i64, i128mem, 0,<br>
+ DEFAULT_ITINS_MPSADSCHED>, VEX_4V;<br>
+ }<br>
+<br>
+ let ExeDomain = SSEPackedSingle in {<br>
+ defm VBLENDPS : SS41I_binop_rmi_int<0x0C, "vblendps", int_x86_sse41_blendps,<br>
+ VR128, loadv4f32, f128mem, 0,<br>
+ DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;<br>
+ defm VBLENDPSY : SS41I_binop_rmi_int<0x0C, "vblendps",<br>
+ int_x86_avx_blend_ps_256, VR256, loadv8f32,<br>
+ f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,<br>
+ VEX_4V, VEX_L;<br>
+ }<br>
+ let ExeDomain = SSEPackedDouble in {<br>
+ defm VBLENDPD : SS41I_binop_rmi_int<0x0D, "vblendpd", int_x86_sse41_blendpd,<br>
+ VR128, loadv2f64, f128mem, 0,<br>
+ DEFAULT_ITINS_FBLENDSCHED>, VEX_4V;<br>
+ defm VBLENDPDY : SS41I_binop_rmi_int<0x0D, "vblendpd",<br>
+ int_x86_avx_blend_pd_256,VR256, loadv4f64,<br>
+ f256mem, 0, DEFAULT_ITINS_FBLENDSCHED>,<br>
+ VEX_4V, VEX_L;<br>
+ }<br>
defm VPBLENDW : SS41I_binop_rmi_int<0x0E, "vpblendw", int_x86_sse41_pblendw,<br>
VR128, loadv2i64, i128mem, 0,<br>
DEFAULT_ITINS_BLENDSCHED>, VEX_4V;<br>
- defm VMPSADBW : SS41I_binop_rmi_int<0x42, "vmpsadbw", int_x86_sse41_mpsadbw,<br>
- VR128, loadv2i64, i128mem, 0,<br>
- DEFAULT_ITINS_MPSADSCHED>, VEX_4V;<br>
- }<br>
+<br>
let ExeDomain = SSEPackedSingle in<br>
defm VDPPS : SS41I_binop_rmi_int<0x40, "vdpps", int_x86_sse41_dpps,<br>
VR128, loadv4f32, f128mem, 0,<br>
@@ -7589,6 +7591,10 @@ let Predicates = [HasAVX2] in {<br>
<br>
let Constraints = "$src1 = $dst" in {<br>
let isCommutable = 0 in {<br>
+ defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,<br>
+ VR128, memopv2i64, i128mem,<br>
+ 1, SSE_MPSADBW_ITINS>;<br>
+ }<br>
let ExeDomain = SSEPackedSingle in<br>
defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps,<br>
VR128, memopv4f32, f128mem,<br>
@@ -7600,10 +7606,6 @@ let Constraints = "$src1 = $dst" in {<br>
defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw,<br>
VR128, memopv2i64, i128mem,<br>
1, SSE_INTALU_ITINS_BLEND_P>;<br>
- defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw,<br>
- VR128, memopv2i64, i128mem,<br>
- 1, SSE_MPSADBW_ITINS>;<br>
- }<br>
let ExeDomain = SSEPackedSingle in<br>
defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps,<br>
VR128, memopv4f32, f128mem, 1,<br>
@@ -8827,12 +8829,10 @@ multiclass AVX2_binop_rmi_int<bits<8> op<br>
Sched<[WriteBlendLd, ReadAfterLd]>, VEX_4V;<br>
}<br>
<br>
-let isCommutable = 0 in {<br>
defm VPBLENDD : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_128,<br>
VR128, loadv2i64, i128mem>;<br>
defm VPBLENDDY : AVX2_binop_rmi_int<0x02, "vpblendd", int_x86_avx2_pblendd_256,<br>
VR256, loadv4i64, i256mem>, VEX_L;<br>
-}<br>
<br>
def : Pat<(v4i32 (X86Blendi (v4i32 VR128:$src1), (v4i32 VR128:$src2),<br>
imm:$mask)),<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/combine-or.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-or.ll?rev=221313&r1=221312&r2=221313&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/combine-or.ll?rev=221313&r1=221312&r2=221313&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/combine-or.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/combine-or.ll Tue Nov 4 17:25:08 2014<br>
@@ -19,8 +19,7 @@ define <2 x i64> @test1(<2 x i64> %a, <2<br>
define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) {<br>
; CHECK-LABEL: test2:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3><br>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4><br>
@@ -32,8 +31,7 @@ define <4 x i32> @test2(<4 x i32> %a, <4<br>
define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) {<br>
; CHECK-LABEL: test3:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32><i32 2, i32 1><br>
%shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32><i32 0, i32 2><br>
@@ -45,8 +43,7 @@ define <2 x i64> @test3(<2 x i64> %a, <2<br>
define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) {<br>
; CHECK-LABEL: test4:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4><br>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 1, i32 2, i32 3><br>
@@ -106,8 +103,7 @@ define <2 x i64> @test8(<2 x i64> %a, <2<br>
define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) {<br>
; CHECK-LABEL: test9:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%and1 = and <4 x i32> %a, <i32 0, i32 0, i32 -1, i32 -1><br>
%and2 = and <4 x i32> %b, <i32 -1, i32 -1, i32 0, i32 0><br>
@@ -119,8 +115,7 @@ define <4 x i32> @test9(<4 x i32> %a, <4<br>
define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) {<br>
; CHECK-LABEL: test10:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%and1 = and <2 x i64> %a, <i64 0, i64 -1><br>
%and2 = and <2 x i64> %b, <i64 -1, i64 0><br>
@@ -132,8 +127,7 @@ define <2 x i64> @test10(<2 x i64> %a, <<br>
define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) {<br>
; CHECK-LABEL: test11:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%and1 = and <4 x i32> %a, <i32 -1, i32 0, i32 0, i32 0><br>
%and2 = and <4 x i32> %b, <i32 0, i32 -1, i32 -1, i32 -1><br>
@@ -230,12 +224,10 @@ define <4 x i32> @test18(<4 x i32> %a, <<br>
; CHECK-LABEL: test18:<br>
; CHECK: # BB#0:<br>
; CHECK-NEXT: xorps %xmm2, %xmm2<br>
-; CHECK-NEXT: xorps %xmm3, %xmm3<br>
-; CHECK-NEXT: blendps {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3]<br>
-; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,1,1]<br>
-; CHECK-NEXT: blendps {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]<br>
-; CHECK-NEXT: orps %xmm0, %xmm2<br>
-; CHECK-NEXT: movaps %xmm2, %xmm0<br>
+; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]<br>
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1]<br>
+; CHECK-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3]<br>
+; CHECK-NEXT: por %xmm1, %xmm0<br>
; CHECK-NEXT: retq<br>
%shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32><i32 4, i32 0, i32 4, i32 4><br>
%shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32><i32 0, i32 4, i32 4, i32 4><br>
@@ -295,8 +287,7 @@ define <2 x i64> @test21(<2 x i64> %a, <<br>
define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) {<br>
; CHECK-LABEL: test_crash:<br>
; CHECK: # BB#0:<br>
-; CHECK-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
-; CHECK-NEXT: movdqa %xmm1, %xmm0<br>
+; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
; CHECK-NEXT: retq<br>
%shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32><i32 4, i32 4, i32 2, i32 3><br>
%shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32><i32 0, i32 1, i32 4, i32 4><br>
<br>
Added: llvm/trunk/test/CodeGen/X86/commute-blend-avx2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-blend-avx2.ll?rev=221313&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-blend-avx2.ll?rev=221313&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/commute-blend-avx2.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/commute-blend-avx2.ll Tue Nov 4 17:25:08 2014<br>
@@ -0,0 +1,89 @@<br>
+; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=core-avx2 -mattr=avx2 < %s | FileCheck %s<br>
+<br>
+define <8 x i16> @commute_fold_vpblendw_128(<8 x i16> %a, <8 x i16>* %b) #0 {<br>
+ %1 = load <8 x i16>* %b<br>
+ %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %1, <8 x i16> %a, i8 17)<br>
+ ret <8 x i16> %2<br>
+<br>
+ ;LABEL: commute_fold_vpblendw_128<br>
+ ;CHECK: vpblendw {{.*#+}} xmm0 = xmm0[0],mem[1,2,3],xmm0[4],mem[5,6,7]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone<br>
+<br>
+define <16 x i16> @commute_fold_vpblendw_256(<16 x i16> %a, <16 x i16>* %b) #0 {<br>
+ %1 = load <16 x i16>* %b<br>
+ %2 = call <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16> %1, <16 x i16> %a, i8 17)<br>
+ ret <16 x i16> %2<br>
+<br>
+ ;LABEL: commute_fold_vpblendw_256<br>
+ ;CHECK: vpblendw {{.*#+}} ymm0 = ymm0[0],mem[1,2,3],ymm0[4],mem[5,6,7],ymm0[8],mem[9,10,11],ymm0[12],mem[13,14,15]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <16 x i16> @llvm.x86.avx2.pblendw(<16 x i16>, <16 x i16>, i8) nounwind readnone<br>
+<br>
+define <4 x i32> @commute_fold_vpblendd_128(<4 x i32> %a, <4 x i32>* %b) #0 {<br>
+ %1 = load <4 x i32>* %b<br>
+ %2 = call <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32> %1, <4 x i32> %a, i8 1)<br>
+ ret <4 x i32> %2<br>
+<br>
+ ;LABEL: commute_fold_vpblendd_128<br>
+ ;CHECK: vpblendd {{.*#+}} xmm0 = xmm0[0],mem[1,2,3]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <4 x i32> @llvm.x86.avx2.pblendd.128(<4 x i32>, <4 x i32>, i8) nounwind readnone<br>
+<br>
+define <8 x i32> @commute_fold_vpblendd_256(<8 x i32> %a, <8 x i32>* %b) #0 {<br>
+ %1 = load <8 x i32>* %b<br>
+ %2 = call <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32> %1, <8 x i32> %a, i8 129)<br>
+ ret <8 x i32> %2<br>
+<br>
+ ;LABEL: commute_fold_vpblendd_256<br>
+ ;CHECK: vpblendd {{.*#+}} ymm0 = ymm0[0],mem[1,2,3,4,5,6],ymm0[7]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <8 x i32> @llvm.x86.avx2.pblendd.256(<8 x i32>, <8 x i32>, i8) nounwind readnone<br>
+<br>
+define <4 x float> @commute_fold_vblendps_128(<4 x float> %a, <4 x float>* %b) #0 {<br>
+ %1 = load <4 x float>* %b<br>
+ %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 3)<br>
+ ret <4 x float> %2<br>
+<br>
+ ;LABEL: commute_fold_vblendps_128<br>
+ ;CHECK: vblendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone<br>
+<br>
+define <8 x float> @commute_fold_vblendps_256(<8 x float> %a, <8 x float>* %b) #0 {<br>
+ %1 = load <8 x float>* %b<br>
+ %2 = call <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float> %1, <8 x float> %a, i8 7)<br>
+ ret <8 x float> %2<br>
+<br>
+ ;LABEL: commute_fold_vblendps_256<br>
+ ;CHECK: vblendps {{.*#+}} ymm0 = ymm0[0,1,2],mem[3,4,5,6,7]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <8 x float> @llvm.x86.avx.blend.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone<br>
+<br>
+define <2 x double> @commute_fold_vblendpd_128(<2 x double> %a, <2 x double>* %b) #0 {<br>
+ %1 = load <2 x double>* %b<br>
+ %2 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %1, <2 x double> %a, i8 1)<br>
+ ret <2 x double> %2<br>
+<br>
+ ;LABEL: commute_fold_vblendpd_128<br>
+ ;CHECK: vblendpd {{.*#+}} xmm0 = xmm0[0],mem[1]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone<br>
+<br>
+define <4 x double> @commute_fold_vblendpd_256(<4 x double> %a, <4 x double>* %b) #0 {<br>
+ %1 = load <4 x double>* %b<br>
+ %2 = call <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double> %1, <4 x double> %a, i8 7)<br>
+ ret <4 x double> %2<br>
+<br>
+ ;LABEL: commute_fold_vblendpd_256<br>
+ ;CHECK: vblendpd {{.*#+}} ymm0 = ymm0[0,1,2],mem[3]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <4 x double> @llvm.x86.avx.blend.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone<br>
<br>
Added: llvm/trunk/test/CodeGen/X86/commute-blend-sse41.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-blend-sse41.ll?rev=221313&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/commute-blend-sse41.ll?rev=221313&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/commute-blend-sse41.ll (added)<br>
+++ llvm/trunk/test/CodeGen/X86/commute-blend-sse41.ll Tue Nov 4 17:25:08 2014<br>
@@ -0,0 +1,34 @@<br>
+; RUN: llc -O3 -mtriple=x86_64-unknown -mcpu=corei7 < %s | FileCheck %s<br>
+<br>
+define <8 x i16> @commute_fold_pblendw(<8 x i16> %a, <8 x i16>* %b) #0 {<br>
+ %1 = load <8 x i16>* %b<br>
+ %2 = call <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16> %1, <8 x i16> %a, i8 17)<br>
+ ret <8 x i16> %2<br>
+<br>
+ ;LABEL: commute_fold_pblendw<br>
+ ;CHECK: pblendw {{.*#+}} xmm0 = xmm0[0],mem[1,2,3],xmm0[4],mem[5,6,7]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <8 x i16> @llvm.x86.sse41.pblendw(<8 x i16>, <8 x i16>, i8) nounwind readnone<br>
+<br>
+define <4 x float> @commute_fold_blendps(<4 x float> %a, <4 x float>* %b) #0 {<br>
+ %1 = load <4 x float>* %b<br>
+ %2 = call <4 x float> @llvm.x86.sse41.blendps(<4 x float> %1, <4 x float> %a, i8 3)<br>
+ ret <4 x float> %2<br>
+<br>
+ ;LABEL: commute_fold_blendps<br>
+ ;CHECK: blendps {{.*#+}} xmm0 = xmm0[0,1],mem[2,3]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <4 x float> @llvm.x86.sse41.blendps(<4 x float>, <4 x float>, i8) nounwind readnone<br>
+<br>
+define <2 x double> @commute_fold_blendpd(<2 x double> %a, <2 x double>* %b) #0 {<br>
+ %1 = load <2 x double>* %b<br>
+ %2 = call <2 x double> @llvm.x86.sse41.blendpd(<2 x double> %1, <2 x double> %a, i8 1)<br>
+ ret <2 x double> %2<br>
+<br>
+ ;LABEL: commute_fold_vblendpd<br>
+ ;CHECK: blendpd {{.*#+}} xmm0 = xmm0[0],mem[1]<br>
+ ;CHECK-NEXT: retq<br>
+}<br>
+declare <2 x double> @llvm.x86.sse41.blendpd(<2 x double>, <2 x double>, i8) nounwind readnone<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-blend.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-blend.ll?rev=221313&r1=221312&r2=221313&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-blend.ll?rev=221313&r1=221312&r2=221313&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-blend.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-blend.ll Tue Nov 4 17:25:08 2014<br>
@@ -202,8 +202,7 @@ define <8 x i16> @vsel_8xi16(<8 x i16> %<br>
;<br>
; SSE41-LABEL: vsel_8xi16:<br>
; SSE41: # BB#0: # %entry<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: vsel_8xi16:<br>
@@ -518,10 +517,8 @@ define <8 x float> @constant_blendvps_av<br>
;<br>
; SSE41-LABEL: constant_blendvps_avx:<br>
; SSE41: # BB#0: # %entry<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0,1,2],xmm0[3]<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm3 = xmm3[0,1,2],xmm1[3]<br>
-; SSE41-NEXT: movaps %xmm2, %xmm0<br>
-; SSE41-NEXT: movaps %xmm3, %xmm1<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3]<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: constant_blendvps_avx:<br>
@@ -637,10 +634,8 @@ define <8 x float> @blend_shufflevector_<br>
;<br>
; SSE41-LABEL: blend_shufflevector_8xfloat:<br>
; SSE41: # BB#0: # %entry<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2],xmm3[3]<br>
-; SSE41-NEXT: movaps %xmm2, %xmm0<br>
-; SSE41-NEXT: movaps %xmm3, %xmm1<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm3[0,1],xmm1[2],xmm3[3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: blend_shufflevector_8xfloat:<br>
@@ -694,8 +689,7 @@ define <4 x i64> @blend_shufflevector_4x<br>
;<br>
; SSE41-LABEL: blend_shufflevector_4xi64:<br>
; SSE41: # BB#0: # %entry<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm2, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]<br>
; SSE41-NEXT: movaps %xmm3, %xmm1<br>
; SSE41-NEXT: retq<br>
;<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v2.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v2.ll?rev=221313&r1=221312&r2=221313&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v2.ll?rev=221313&r1=221312&r2=221313&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v2.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v2.ll Tue Nov 4 17:25:08 2014<br>
@@ -260,8 +260,7 @@ define <2 x double> @shuffle_v2f64_21(<2<br>
;<br>
; SSE41-LABEL: shuffle_v2f64_21:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]<br>
-; SSE41-NEXT: movapd %xmm1, %xmm0<br>
+; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: shuffle_v2f64_21:<br>
@@ -508,8 +507,7 @@ define <2 x i64> @shuffle_v2i64_21(<2 x<br>
;<br>
; SSE41-LABEL: shuffle_v2i64_21:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: shuffle_v2i64_21:<br>
@@ -545,8 +543,8 @@ define <2 x i64> @shuffle_v2i64_21_copy(<br>
;<br>
; SSE41-LABEL: shuffle_v2i64_21_copy:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm2, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]<br>
+; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: shuffle_v2i64_21_copy:<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll?rev=221313&r1=221312&r2=221313&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll?rev=221313&r1=221312&r2=221313&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/vector-shuffle-combining.ll Tue Nov 4 17:25:08 2014<br>
@@ -369,7 +369,8 @@ define <4 x i32> @combine_bitwise_ops_te<br>
; SSE41: # BB#0:<br>
; SSE41-NEXT: pxor %xmm1, %xmm0<br>
; SSE41-NEXT: pxor %xmm1, %xmm1<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]<br>
+; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_bitwise_ops_test3b:<br>
@@ -411,8 +412,7 @@ define <4 x i32> @combine_bitwise_ops_te<br>
; SSE41-LABEL: combine_bitwise_ops_test4b:<br>
; SSE41: # BB#0:<br>
; SSE41-NEXT: pand %xmm1, %xmm0<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]<br>
-; SSE41-NEXT: movdqa %xmm2, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_bitwise_ops_test4b:<br>
@@ -452,8 +452,7 @@ define <4 x i32> @combine_bitwise_ops_te<br>
; SSE41-LABEL: combine_bitwise_ops_test5b:<br>
; SSE41: # BB#0:<br>
; SSE41-NEXT: por %xmm1, %xmm0<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]<br>
-; SSE41-NEXT: movdqa %xmm2, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2,3],xmm2[4,5],xmm0[6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_bitwise_ops_test5b:<br>
@@ -1170,8 +1169,7 @@ define <4 x float> @combine_test2(<4 x f<br>
;<br>
; SSE41-LABEL: combine_test2:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_test2:<br>
@@ -1237,8 +1235,7 @@ define <4 x float> @combine_test5(<4 x f<br>
;<br>
; SSE41-LABEL: combine_test5:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2,3]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_test5:<br>
@@ -1299,8 +1296,7 @@ define <4 x i32> @combine_test7(<4 x i32<br>
;<br>
; SSE41-LABEL: combine_test7:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_test7:<br>
@@ -1371,8 +1367,7 @@ define <4 x i32> @combine_test10(<4 x i3<br>
;<br>
; SSE41-LABEL: combine_test10:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_test10:<br>
@@ -1415,8 +1410,7 @@ define <4 x float> @combine_test12(<4 x<br>
;<br>
; SSE41-LABEL: combine_test12:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_test12:<br>
@@ -1479,8 +1473,7 @@ define <4 x float> @combine_test15(<4 x<br>
;<br>
; SSE41-LABEL: combine_test15:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2,3]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_test15:<br>
@@ -1518,8 +1511,7 @@ define <4 x i32> @combine_test17(<4 x i3<br>
;<br>
; SSE41-LABEL: combine_test17:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3,4,5,6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_test17:<br>
@@ -1587,8 +1579,7 @@ define <4 x i32> @combine_test20(<4 x i3<br>
;<br>
; SSE41-LABEL: combine_test20:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]<br>
-; SSE41-NEXT: movdqa %xmm1, %xmm0<br>
+; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3],xmm1[4,5,6,7]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX1-LABEL: combine_test20:<br>
@@ -1632,10 +1623,9 @@ define <4 x float> @combine_test1b(<4 x<br>
;<br>
; SSE41-LABEL: combine_test1b:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: movaps %xmm1, %xmm2<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm2[0,0]<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm2[2,0]<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]<br>
+; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,0],xmm0[0,0]<br>
+; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm0[2,0]<br>
; SSE41-NEXT: movaps %xmm1, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
@@ -1673,11 +1663,9 @@ define <4 x float> @combine_test2b(<4 x<br>
;<br>
; SSE41-LABEL: combine_test2b:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: movaps %xmm1, %xmm2<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[1,1]<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2,1,3]<br>
-; SSE41-NEXT: movaps %xmm2, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]<br>
+; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0],xmm1[1,1]<br>
+; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_test2b:<br>
@@ -1736,10 +1724,9 @@ define <4 x float> @combine_test4b(<4 x<br>
;<br>
; SSE41-LABEL: combine_test4b:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: movaps %xmm1, %xmm2<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0],xmm0[1],xmm2[2],xmm0[3]<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm2 = xmm2[2,0],xmm1[3,0]<br>
-; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm2[0,2]<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]<br>
+; SSE41-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[3,0]<br>
+; SSE41-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[0,2]<br>
; SSE41-NEXT: movaps %xmm1, %xmm0<br>
; SSE41-NEXT: retq<br>
;<br>
@@ -2006,8 +1993,7 @@ define <4 x float> @combine_blend_01(<4<br>
;<br>
; SSE41-LABEL: combine_blend_01:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]<br>
-; SSE41-NEXT: movapd %xmm1, %xmm0<br>
+; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_blend_01:<br>
@@ -2036,8 +2022,7 @@ define <4 x float> @combine_blend_02(<4<br>
;<br>
; SSE41-LABEL: combine_blend_02:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_blend_02:<br>
@@ -2070,8 +2055,7 @@ define <4 x float> @combine_blend_123(<4<br>
;<br>
; SSE41-LABEL: combine_blend_123:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]<br>
-; SSE41-NEXT: movaps %xmm1, %xmm0<br>
+; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_blend_123:<br>
@@ -2153,8 +2137,7 @@ define <4 x float> @combine_undef_input_<br>
;<br>
; SSE41-LABEL: combine_undef_input_test1:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]<br>
-; SSE41-NEXT: movapd %xmm1, %xmm0<br>
+; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_undef_input_test1:<br>
@@ -2343,8 +2326,7 @@ define <4 x float> @combine_undef_input_<br>
;<br>
; SSE41-LABEL: combine_undef_input_test11:<br>
; SSE41: # BB#0:<br>
-; SSE41-NEXT: blendpd {{.*#+}} xmm1 = xmm1[0],xmm0[1]<br>
-; SSE41-NEXT: movapd %xmm1, %xmm0<br>
+; SSE41-NEXT: blendpd {{.*#+}} xmm0 = xmm1[0],xmm0[1]<br>
; SSE41-NEXT: retq<br>
;<br>
; AVX-LABEL: combine_undef_input_test11:<br>
<br>
<br>
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</blockquote></div><br></div>
</div></div><br>_______________________________________________<br>
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<br></blockquote></div><br><br clear="all"><div><br></div>-- <br>~Craig
</div>