<div dir="ltr"><br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Oct 24, 2014 at 12:00 PM, Colin LeMahieu <span dir="ltr"><<a href="mailto:colinl@codeaurora.org" target="_blank">colinl@codeaurora.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">Author: colinl<br>
Date: Fri Oct 24 14:00:32 2014<br>
New Revision: 220584<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=220584&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=220584&view=rev</a><br>
Log:<br>
[Hexagon] Resubmission of 220427<br>
Modified library structure to deal with circular dependency between HexagonInstPrinter and HexagonMCInst.<br>
Adding encoding bits for add opcode.<br>
Adding llvm-mc tests.<br>
Removing unit tests.<br></blockquote><div><br></div><div>Looks like the test is still failing on at least one bot:<br><br><a href="http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/18053/steps/check-all/logs/LLVM%3A%3Aalu32.txt">http://lab.llvm.org:8011/builders/clang-x86_64-ubuntu-gdb-75/builds/18053/steps/check-all/logs/LLVM%3A%3Aalu32.txt</a><br></div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex">
<br>
<a href="http://reviews.llvm.org/D5624" target="_blank">http://reviews.llvm.org/D5624</a><br>
<br>
Added:<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h<br>
llvm/trunk/test/MC/Disassembler/Hexagon/<br>
llvm/trunk/test/MC/Disassembler/Hexagon/alu32.txt<br>
llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg<br>
Removed:<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/CMakeLists.txt<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt<br>
llvm/trunk/lib/Target/Hexagon/InstPrinter/Makefile<br>
llvm/trunk/unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp<br>
Modified:<br>
llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br>
llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp<br>
llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>
llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp<br>
llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h<br>
llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt<br>
llvm/trunk/lib/Target/Hexagon/Makefile<br>
llvm/trunk/unittests/MC/CMakeLists.txt<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/CMakeLists.txt?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/CMakeLists.txt Fri Oct 24 14:00:32 2014<br>
@@ -40,6 +40,5 @@ add_llvm_target(HexagonCodeGen<br>
)<br>
<br>
add_subdirectory(TargetInfo)<br>
-add_subdirectory(InstPrinter)<br>
add_subdirectory(MCTargetDesc)<br>
add_subdirectory(Disassembler)<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp Fri Oct 24 14:00:32 2014<br>
@@ -48,6 +48,40 @@ public:<br>
};<br>
}<br>
<br>
+static const uint16_t IntRegDecoderTable[] = {<br>
+ Hexagon::R0, Hexagon::R1, Hexagon::R2, Hexagon::R3, Hexagon::R4,<br>
+ Hexagon::R5, Hexagon::R6, Hexagon::R7, Hexagon::R8, Hexagon::R9,<br>
+ Hexagon::R10, Hexagon::R11, Hexagon::R12, Hexagon::R13, Hexagon::R14,<br>
+ Hexagon::R15, Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,<br>
+ Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23, Hexagon::R24,<br>
+ Hexagon::R25, Hexagon::R26, Hexagon::R27, Hexagon::R28, Hexagon::R29,<br>
+ Hexagon::R30, Hexagon::R31};<br>
+<br>
+static const uint16_t PredRegDecoderTable[] = {Hexagon::P0, Hexagon::P1,<br>
+ Hexagon::P2, Hexagon::P3};<br>
+<br>
+static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>
+ uint64_t /*Address*/,<br>
+ void const *Decoder) {<br>
+ if (RegNo > 31)<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ unsigned Register = IntRegDecoderTable[RegNo];<br>
+ Inst.addOperand(MCOperand::CreateReg(Register));<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
+static DecodeStatus DecodePredRegsRegisterClass(MCInst &Inst, unsigned RegNo,<br>
+ uint64_t /*Address*/,<br>
+ void const *Decoder) {<br>
+ if (RegNo > 3)<br>
+ return MCDisassembler::Fail;<br>
+<br>
+ unsigned Register = PredRegDecoderTable[RegNo];<br>
+ Inst.addOperand(MCOperand::CreateReg(Register));<br>
+ return MCDisassembler::Success;<br>
+}<br>
+<br>
#include "HexagonGenDisassemblerTables.inc"<br>
<br>
static MCDisassembler *createHexagonDisassembler(Target const &T,<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp Fri Oct 24 14:00:32 2014<br>
@@ -18,7 +18,7 @@<br>
#include "HexagonMachineFunctionInfo.h"<br>
#include "HexagonSubtarget.h"<br>
#include "HexagonTargetMachine.h"<br>
-#include "InstPrinter/HexagonInstPrinter.h"<br>
+#include "MCTargetDesc/HexagonInstPrinter.h"<br>
#include "MCTargetDesc/HexagonMCInst.h"<br>
#include "llvm/ADT/SmallString.h"<br>
#include "llvm/ADT/SmallVector.h"<br>
@@ -195,8 +195,8 @@ void HexagonAsmPrinter::EmitInstruction(<br>
unsigned Size = BundleMIs.size();<br>
assert((Size+IgnoreCount) == MI->getBundleSize() && "Corrupt Bundle!");<br>
for (unsigned Index = 0; Index < Size; Index++) {<br>
- HexagonMCInst MCI;<br>
- MCI.setPacketStart(Index == 0);<br>
+ HexagonMCInst MCI (BundleMIs[Index]->getOpcode());<br>
+ MCI.setPacketBegin(Index == 0);<br>
MCI.setPacketEnd(Index == (Size-1));<br>
<br>
HexagonLowerToMC(BundleMIs[Index], MCI, *this);<br>
@@ -204,9 +204,9 @@ void HexagonAsmPrinter::EmitInstruction(<br>
}<br>
}<br>
else {<br>
- HexagonMCInst MCI;<br>
+ HexagonMCInst MCI(MI->getOpcode());<br>
if (MI->getOpcode() == Hexagon::ENDLOOP0) {<br>
- MCI.setPacketStart(true);<br>
+ MCI.setPacketBegin(true);<br>
MCI.setPacketEnd(true);<br>
}<br>
HexagonLowerToMC(MI, MCI, *this);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.td Fri Oct 24 14:00:32 2014<br>
@@ -92,6 +92,77 @@ def HexagonWrapperCombineII :<br>
def HexagonWrapperCombineRR :<br>
SDNode<"HexagonISD::WrapperCombineRR", SDTHexagonI64I32I32>;<br>
<br>
+let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in<br>
+class T_ALU32_3op<string mnemonic, bits<3> MajOp, bits<3> MinOp, bit OpsRev,<br>
+ bit IsComm><br>
+ : ALU32_rr<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),<br>
+ "$Rd = "#mnemonic#"($Rs, $Rt)",<br>
+ [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredRel {<br>
+ let isCommutable = IsComm;<br>
+ let BaseOpcode = mnemonic#_rr;<br>
+ let CextOpcode = mnemonic;<br>
+<br>
+ bits<5> Rs;<br>
+ bits<5> Rt;<br>
+ bits<5> Rd;<br>
+<br>
+ let IClass = 0b1111;<br>
+ let Inst{27} = 0b0;<br>
+ let Inst{26-24} = MajOp;<br>
+ let Inst{23-21} = MinOp;<br>
+ let Inst{20-16} = !if(OpsRev,Rt,Rs);<br>
+ let Inst{12-8} = !if(OpsRev,Rs,Rt);<br>
+ let Inst{4-0} = Rd;<br>
+}<br>
+<br>
+let hasSideEffects = 0, hasNewValue = 1 in<br>
+class T_ALU32_3op_pred<string mnemonic, bits<3> MajOp, bits<3> MinOp,<br>
+ bit OpsRev, bit PredNot, bit PredNew><br>
+ : ALU32_rr<(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, IntRegs:$Rt),<br>
+ "if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") "#<br>
+ "$Rd = "#mnemonic#"($Rs, $Rt)",<br>
+ [], "", ALU32_3op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {<br>
+ let isPredicated = 1;<br>
+ let isPredicatedFalse = PredNot;<br>
+ let isPredicatedNew = PredNew;<br>
+ let BaseOpcode = mnemonic#_rr;<br>
+ let CextOpcode = mnemonic;<br>
+<br>
+ bits<2> Pu;<br>
+ bits<5> Rs;<br>
+ bits<5> Rt;<br>
+ bits<5> Rd;<br>
+<br>
+ let IClass = 0b1111;<br>
+ let Inst{27} = 0b1;<br>
+ let Inst{26-24} = MajOp;<br>
+ let Inst{23-21} = MinOp;<br>
+ let Inst{20-16} = !if(OpsRev,Rt,Rs);<br>
+ let Inst{13} = PredNew;<br>
+ let Inst{12-8} = !if(OpsRev,Rs,Rt);<br>
+ let Inst{7} = PredNot;<br>
+ let Inst{6-5} = Pu;<br>
+ let Inst{4-0} = Rd;<br>
+}<br>
+<br>
+multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,<br>
+ bit OpsRev> {<br>
+ def t : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 0>;<br>
+ def f : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 0>;<br>
+ def tnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 0, 1>;<br>
+ def fnew : T_ALU32_3op_pred<mnemonic, MajOp, MinOp, OpsRev, 1, 1>;<br>
+}<br>
+<br>
+multiclass T_ALU32_3op_A2<string mnemonic, bits<3> MajOp, bits<3> MinOp,<br>
+ bit OpsRev, bit IsComm> {<br>
+ let isPredicable = 1 in<br>
+ def A2_#NAME : T_ALU32_3op <mnemonic, MajOp, MinOp, OpsRev, IsComm>;<br>
+ defm A2_p#NAME : T_ALU32_3op_p<mnemonic, MajOp, MinOp, OpsRev>;<br>
+}<br>
+<br>
+let isCodeGenOnly = 0 in<br>
+defm add : T_ALU32_3op_A2<"add", 0b011, 0b000, 0, 1>;<br>
+<br>
multiclass ALU32_Pbase<string mnemonic, RegisterClass RC, bit isNot,<br>
bit isPredNew> {<br>
let isPredicatedNew = isPredNew in<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/HexagonMCInstLower.cpp Fri Oct 24 14:00:32 2014<br>
@@ -24,8 +24,8 @@<br>
<br>
using namespace llvm;<br>
<br>
-static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol,<br>
- HexagonAsmPrinter& Printer) {<br>
+static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,<br>
+ HexagonAsmPrinter &Printer) {<br>
MCContext &MC = Printer.OutContext;<br>
const MCExpr *ME;<br>
<br>
@@ -39,10 +39,10 @@ static MCOperand GetSymbolRef(const Mach<br>
}<br>
<br>
// Create an MCInst from a MachineInstr<br>
-void llvm::HexagonLowerToMC(const MachineInstr* MI, HexagonMCInst& MCI,<br>
- HexagonAsmPrinter& AP) {<br>
- MCI.setOpcode(MI->getOpcode());<br>
- MCI.setDesc(MI->getDesc());<br>
+void llvm::HexagonLowerToMC(const MachineInstr *MI, HexagonMCInst &MCI,<br>
+ HexagonAsmPrinter &AP) {<br>
+ assert(MCI.getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&<br>
+ "MCI opcode should have been set on construction");<br>
<br>
for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {<br>
const MachineOperand &MO = MI->getOperand(i);<br>
@@ -54,7 +54,8 @@ void llvm::HexagonLowerToMC(const Machin<br>
llvm_unreachable("unknown operand type");<br>
case MachineOperand::MO_Register:<br>
// Ignore all implicit register operands.<br>
- if (MO.isImplicit()) continue;<br>
+ if (MO.isImplicit())<br>
+ continue;<br>
MCO = MCOperand::CreateReg(MO.getReg());<br>
break;<br>
case MachineOperand::MO_FPImmediate: {<br>
@@ -68,16 +69,15 @@ void llvm::HexagonLowerToMC(const Machin<br>
MCO = MCOperand::CreateImm(MO.getImm());<br>
break;<br>
case MachineOperand::MO_MachineBasicBlock:<br>
- MCO = MCOperand::CreateExpr<br>
- (MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(),<br>
- AP.OutContext));<br>
+ MCO = MCOperand::CreateExpr(<br>
+ MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), AP.OutContext));<br>
break;<br>
case MachineOperand::MO_GlobalAddress:<br>
MCO = GetSymbolRef(MO, AP.getSymbol(MO.getGlobal()), AP);<br>
break;<br>
case MachineOperand::MO_ExternalSymbol:<br>
- MCO = GetSymbolRef(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()),<br>
- AP);<br>
+ MCO =<br>
+ GetSymbolRef(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);<br>
break;<br>
case MachineOperand::MO_JumpTableIndex:<br>
MCO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP);<br>
@@ -86,7 +86,8 @@ void llvm::HexagonLowerToMC(const Machin<br>
MCO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP);<br>
break;<br>
case MachineOperand::MO_BlockAddress:<br>
- MCO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP);<br>
+ MCO =<br>
+ GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);<br>
break;<br>
}<br>
<br>
<br>
Removed: llvm/trunk/lib/Target/Hexagon/InstPrinter/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/CMakeLists.txt?rev=220583&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/CMakeLists.txt?rev=220583&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/CMakeLists.txt (removed)<br>
@@ -1,3 +0,0 @@<br>
-add_llvm_library(LLVMHexagonAsmPrinter<br>
- HexagonInstPrinter.cpp<br>
- )<br>
<br>
Removed: llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp?rev=220583&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp?rev=220583&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.cpp (removed)<br>
@@ -1,254 +0,0 @@<br>
-//===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//<br>
-//<br>
-// The LLVM Compiler Infrastructure<br>
-//<br>
-// This file is distributed under the University of Illinois Open Source<br>
-// License. See LICENSE.TXT for details.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-//<br>
-// This class prints an Hexagon MCInst to a .s file.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-<br>
-#include "HexagonAsmPrinter.h"<br>
-#include "Hexagon.h"<br>
-#include "HexagonInstPrinter.h"<br>
-#include "MCTargetDesc/HexagonMCInst.h"<br>
-#include "llvm/ADT/StringExtras.h"<br>
-#include "llvm/MC/MCAsmInfo.h"<br>
-#include "llvm/MC/MCExpr.h"<br>
-#include "llvm/MC/MCInst.h"<br>
-#include "llvm/Support/raw_ostream.h"<br>
-<br>
-using namespace llvm;<br>
-<br>
-#define DEBUG_TYPE "asm-printer"<br>
-<br>
-#define GET_INSTRUCTION_NAME<br>
-#include "HexagonGenAsmWriter.inc"<br>
-<br>
-const char HexagonInstPrinter::PacketPadding = '\t';<br>
-// Return the minimum value that a constant extendable operand can have<br>
-// without being extended.<br>
-static int getMinValue(uint64_t TSFlags) {<br>
- unsigned isSigned =<br>
- (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>
- unsigned bits =<br>
- (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>
-<br>
- if (isSigned)<br>
- return -1U << (bits - 1);<br>
-<br>
- return 0;<br>
-}<br>
-<br>
-// Return the maximum value that a constant extendable operand can have<br>
-// without being extended.<br>
-static int getMaxValue(uint64_t TSFlags) {<br>
- unsigned isSigned =<br>
- (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>
- unsigned bits =<br>
- (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>
-<br>
- if (isSigned)<br>
- return ~(-1U << (bits - 1));<br>
-<br>
- return ~(-1U << bits);<br>
-}<br>
-<br>
-// Return true if the instruction must be extended.<br>
-static bool isExtended(uint64_t TSFlags) {<br>
- return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;<br>
-}<br>
-<br>
-// Currently just used in an assert statement<br>
-static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;<br>
-// Return true if the instruction may be extended based on the operand value.<br>
-static bool isExtendable(uint64_t TSFlags) {<br>
- return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;<br>
-}<br>
-<br>
-StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {<br>
- return MII.getName(Opcode);<br>
-}<br>
-<br>
-StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {<br>
- return getRegisterName(RegNo);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,<br>
- StringRef Annot) {<br>
- printInst((const HexagonMCInst*)(MI), O, Annot);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,<br>
- StringRef Annot) {<br>
- const char startPacket = '{',<br>
- endPacket = '}';<br>
- // TODO: add outer HW loop when it's supported too.<br>
- if (MI->getOpcode() == Hexagon::ENDLOOP0) {<br>
- // Ending a harware loop is different from ending an regular packet.<br>
- assert(MI->isPacketEnd() && "Loop-end must also end the packet");<br>
-<br>
- if (MI->isPacketStart()) {<br>
- // There must be a packet to end a loop.<br>
- // FIXME: when shuffling is always run, this shouldn't be needed.<br>
- HexagonMCInst Nop;<br>
- StringRef NoAnnot;<br>
-<br>
- Nop.setOpcode (Hexagon::NOP);<br>
- Nop.setPacketStart (MI->isPacketStart());<br>
- printInst (&Nop, O, NoAnnot);<br>
- }<br>
-<br>
- // Close the packet.<br>
- if (MI->isPacketEnd())<br>
- O << PacketPadding << endPacket;<br>
-<br>
- printInstruction(MI, O);<br>
- }<br>
- else {<br>
- // Prefix the insn opening the packet.<br>
- if (MI->isPacketStart())<br>
- O << PacketPadding << startPacket << '\n';<br>
-<br>
- printInstruction(MI, O);<br>
-<br>
- // Suffix the insn closing the packet.<br>
- if (MI->isPacketEnd())<br>
- // Suffix the packet in a new line always, since the GNU assembler has<br>
- // issues with a closing brace on the same line as CONST{32,64}.<br>
- O << '\n' << PacketPadding << endPacket;<br>
- }<br>
-<br>
- printAnnotation(O, Annot);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- const MCOperand& MO = MI->getOperand(OpNo);<br>
-<br>
- if (MO.isReg()) {<br>
- O << getRegisterName(MO.getReg());<br>
- } else if(MO.isExpr()) {<br>
- O << *MO.getExpr();<br>
- } else if(MO.isImm()) {<br>
- printImmOperand(MI, OpNo, O);<br>
- } else {<br>
- llvm_unreachable("Unknown operand");<br>
- }<br>
-}<br>
-<br>
-void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- const MCOperand& MO = MI->getOperand(OpNo);<br>
-<br>
- if(MO.isExpr()) {<br>
- O << *MO.getExpr();<br>
- } else if(MO.isImm()) {<br>
- O << MI->getOperand(OpNo).getImm();<br>
- } else {<br>
- llvm_unreachable("Unknown operand");<br>
- }<br>
-}<br>
-<br>
-void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- const MCOperand &MO = MI->getOperand(OpNo);<br>
- const MCInstrDesc &MII = getMII().get(MI->getOpcode());<br>
-<br>
- assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&<br>
- "Expecting an extendable operand");<br>
-<br>
- if (MO.isExpr() || isExtended(MII.TSFlags)) {<br>
- O << "#";<br>
- } else if (MO.isImm()) {<br>
- int ImmValue = MO.getImm();<br>
- if (ImmValue < getMinValue(MII.TSFlags) ||<br>
- ImmValue > getMaxValue(MII.TSFlags))<br>
- O << "#";<br>
- }<br>
- printOperand(MI, OpNo, O);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,<br>
- unsigned OpNo, raw_ostream &O) const {<br>
- O << MI->getOperand(OpNo).getImm();<br>
-}<br>
-<br>
-void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- O << -MI->getOperand(OpNo).getImm();<br>
-}<br>
-<br>
-void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- O << -1;<br>
-}<br>
-<br>
-void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- const MCOperand& MO0 = MI->getOperand(OpNo);<br>
- const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>
-<br>
- O << getRegisterName(MO0.getReg());<br>
- O << " + #" << MO1.getImm();<br>
-}<br>
-<br>
-void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- const MCOperand& MO0 = MI->getOperand(OpNo);<br>
- const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>
-<br>
- O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();<br>
-}<br>
-<br>
-void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>
-<br>
- printOperand(MI, OpNo, O);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>
-<br>
- printOperand(MI, OpNo, O);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>
-<br>
- printOperand(MI, OpNo, O);<br>
-}<br>
-<br>
-void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
- // Branches can take an immediate operand. This is used by the branch<br>
- // selection pass to print $+8, an eight byte displacement from the PC.<br>
- llvm_unreachable("Unknown branch operand.");<br>
-}<br>
-<br>
-void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
-}<br>
-<br>
-void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
-}<br>
-<br>
-void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const {<br>
-}<br>
-<br>
-void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O, bool hi) const {<br>
- assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");<br>
-<br>
- O << '#' << (hi ? "HI" : "LO") << "(#";<br>
- printOperand(MI, OpNo, O);<br>
- O << ')';<br>
-}<br>
<br>
Removed: llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h?rev=220583&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h?rev=220583&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h (removed)<br>
@@ -1,87 +0,0 @@<br>
-//===-- HexagonInstPrinter.h - Convert Hexagon MCInst to assembly syntax --===//<br>
-//<br>
-// The LLVM Compiler Infrastructure<br>
-//<br>
-// This file is distributed under the University of Illinois Open Source<br>
-// License. See LICENSE.TXT for details.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-//<br>
-// This class prints an Hexagon MCInst to a .s file.<br>
-//<br>
-//===----------------------------------------------------------------------===//<br>
-<br>
-#ifndef LLVM_LIB_TARGET_HEXAGON_INSTPRINTER_HEXAGONINSTPRINTER_H<br>
-#define LLVM_LIB_TARGET_HEXAGON_INSTPRINTER_HEXAGONINSTPRINTER_H<br>
-<br>
-#include "llvm/MC/MCInstPrinter.h"<br>
-#include "llvm/MC/MCInstrInfo.h"<br>
-<br>
-namespace llvm {<br>
- class HexagonMCInst;<br>
-<br>
- class HexagonInstPrinter : public MCInstPrinter {<br>
- public:<br>
- explicit HexagonInstPrinter(const MCAsmInfo &MAI,<br>
- const MCInstrInfo &MII,<br>
- const MCRegisterInfo &MRI)<br>
- : MCInstPrinter(MAI, MII, MRI), MII(MII) {}<br>
-<br>
- void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;<br>
- void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);<br>
- virtual StringRef getOpcodeName(unsigned Opcode) const;<br>
- void printInstruction(const MCInst *MI, raw_ostream &O);<br>
- StringRef getRegName(unsigned RegNo) const;<br>
- static const char *getRegisterName(unsigned RegNo);<br>
-<br>
- void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
- void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
- void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
- void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const;<br>
- void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const;<br>
- void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printGlobalOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
- const;<br>
- void printJumpTable(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
-<br>
- void printConstantPool(const MCInst *MI, unsigned OpNo,<br>
- raw_ostream &O) const;<br>
-<br>
- void printSymbolHi(const MCInst *MI, unsigned OpNo, raw_ostream &O) const<br>
- { printSymbol(MI, OpNo, O, true); }<br>
- void printSymbolLo(const MCInst *MI, unsigned OpNo, raw_ostream &O) const<br>
- { printSymbol(MI, OpNo, O, false); }<br>
-<br>
- const MCInstrInfo &getMII() const {<br>
- return MII;<br>
- }<br>
-<br>
- protected:<br>
- void printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi)<br>
- const;<br>
-<br>
- static const char PacketPadding;<br>
-<br>
- private:<br>
- const MCInstrInfo &MII;<br>
-<br>
- };<br>
-<br>
-} // end namespace llvm<br>
-<br>
-#endif<br>
<br>
Removed: llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt?rev=220583&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt?rev=220583&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/LLVMBuild.txt (removed)<br>
@@ -1,23 +0,0 @@<br>
-;===- ./lib/Target/Hexagon/InstPrinter/LLVMBuild.txt -----------*- Conf -*--===;<br>
-;<br>
-; The LLVM Compiler Infrastructure<br>
-;<br>
-; This file is distributed under the University of Illinois Open Source<br>
-; License. See LICENSE.TXT for details.<br>
-;<br>
-;===------------------------------------------------------------------------===;<br>
-;<br>
-; This is an LLVMBuild description file for the components in this subdirectory.<br>
-;<br>
-; For more information on the LLVMBuild system, please see:<br>
-;<br>
-; <a href="http://llvm.org/docs/LLVMBuild.html" target="_blank">http://llvm.org/docs/LLVMBuild.html</a><br>
-;<br>
-;===------------------------------------------------------------------------===;<br>
-<br>
-[component_0]<br>
-type = Library<br>
-name = HexagonAsmPrinter<br>
-parent = Hexagon<br>
-required_libraries = MC Support<br>
-add_to_library_groups = Hexagon<br>
<br>
Removed: llvm/trunk/lib/Target/Hexagon/InstPrinter/Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/Makefile?rev=220583&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/InstPrinter/Makefile?rev=220583&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/InstPrinter/Makefile (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/InstPrinter/Makefile (removed)<br>
@@ -1,15 +0,0 @@<br>
-##===- lib/Target/Hexagon/InstPrinter/Makefile ----------------------------===##<br>
-#<br>
-# The LLVM Compiler Infrastructure<br>
-#<br>
-# This file is distributed under the University of Illinois Open Source<br>
-# License. See LICENSE.TXT for details.<br>
-#<br>
-##===----------------------------------------------------------------------===##<br>
-LEVEL = ../../../..<br>
-LIBRARYNAME = LLVMHexagonAsmPrinter<br>
-<br>
-# Hack: we need to include 'main' Hexagon target directory to grab private headers<br>
-CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..<br>
-<br>
-include $(LEVEL)/Makefile.common<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/LLVMBuild.txt Fri Oct 24 14:00:32 2014<br>
@@ -16,7 +16,7 @@<br>
;===------------------------------------------------------------------------===;<br>
<br>
[common]<br>
-subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo<br>
+subdirectories = Disassembler MCTargetDesc TargetInfo<br>
<br>
[component_0]<br>
type = TargetGroup<br>
@@ -28,5 +28,5 @@ has_asmprinter = 1<br>
type = Library<br>
name = HexagonCodeGen<br>
parent = Hexagon<br>
-required_libraries = Analysis AsmPrinter CodeGen Core HexagonAsmPrinter HexagonDesc HexagonInfo MC SelectionDAG Support Target<br>
+required_libraries = Analysis AsmPrinter CodeGen Core HexagonDesc HexagonInfo MC SelectionDAG Support Target<br>
add_to_library_groups = Hexagon<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/CMakeLists.txt Fri Oct 24 14:00:32 2014<br>
@@ -1,4 +1,5 @@<br>
add_llvm_library(LLVMHexagonDesc<br>
+ HexagonInstPrinter.cpp<br>
HexagonMCAsmInfo.cpp<br>
HexagonMCCodeEmitter.cpp<br>
HexagonMCInst.cpp<br>
<br>
Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp?rev=220584&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp?rev=220584&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp (added)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.cpp Fri Oct 24 14:00:32 2014<br>
@@ -0,0 +1,253 @@<br>
+//===- HexagonInstPrinter.cpp - Convert Hexagon MCInst to assembly syntax -===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This class prints an Hexagon MCInst to a .s file.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "HexagonAsmPrinter.h"<br>
+#include "Hexagon.h"<br>
+#include "HexagonInstPrinter.h"<br>
+#include "MCTargetDesc/HexagonMCInst.h"<br>
+#include "llvm/ADT/StringExtras.h"<br>
+#include "llvm/MC/MCAsmInfo.h"<br>
+#include "llvm/MC/MCExpr.h"<br>
+#include "llvm/MC/MCInst.h"<br>
+#include "llvm/Support/raw_ostream.h"<br>
+<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "asm-printer"<br>
+<br>
+#define GET_INSTRUCTION_NAME<br>
+#include "HexagonGenAsmWriter.inc"<br>
+<br>
+const char HexagonInstPrinter::PacketPadding = '\t';<br>
+// Return the minimum value that a constant extendable operand can have<br>
+// without being extended.<br>
+static int getMinValue(uint64_t TSFlags) {<br>
+ unsigned isSigned =<br>
+ (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>
+ unsigned bits =<br>
+ (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>
+<br>
+ if (isSigned)<br>
+ return -1U << (bits - 1);<br>
+<br>
+ return 0;<br>
+}<br>
+<br>
+// Return the maximum value that a constant extendable operand can have<br>
+// without being extended.<br>
+static int getMaxValue(uint64_t TSFlags) {<br>
+ unsigned isSigned =<br>
+ (TSFlags >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>
+ unsigned bits =<br>
+ (TSFlags >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>
+<br>
+ if (isSigned)<br>
+ return ~(-1U << (bits - 1));<br>
+<br>
+ return ~(-1U << bits);<br>
+}<br>
+<br>
+// Return true if the instruction must be extended.<br>
+static bool isExtended(uint64_t TSFlags) {<br>
+ return (TSFlags >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;<br>
+}<br>
+<br>
+// Currently just used in an assert statement<br>
+static bool isExtendable(uint64_t TSFlags) LLVM_ATTRIBUTE_UNUSED;<br>
+// Return true if the instruction may be extended based on the operand value.<br>
+static bool isExtendable(uint64_t TSFlags) {<br>
+ return (TSFlags >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;<br>
+}<br>
+<br>
+StringRef HexagonInstPrinter::getOpcodeName(unsigned Opcode) const {<br>
+ return MII.getName(Opcode);<br>
+}<br>
+<br>
+StringRef HexagonInstPrinter::getRegName(unsigned RegNo) const {<br>
+ return getRegisterName(RegNo);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O,<br>
+ StringRef Annot) {<br>
+ printInst((const HexagonMCInst*)(MI), O, Annot);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printInst(const HexagonMCInst *MI, raw_ostream &O,<br>
+ StringRef Annot) {<br>
+ const char startPacket = '{',<br>
+ endPacket = '}';<br>
+ // TODO: add outer HW loop when it's supported too.<br>
+ if (MI->getOpcode() == Hexagon::ENDLOOP0) {<br>
+ // Ending a harware loop is different from ending an regular packet.<br>
+ assert(MI->isPacketEnd() && "Loop-end must also end the packet");<br>
+<br>
+ if (MI->isPacketBegin()) {<br>
+ // There must be a packet to end a loop.<br>
+ // FIXME: when shuffling is always run, this shouldn't be needed.<br>
+ HexagonMCInst Nop (Hexagon::NOP);<br>
+ StringRef NoAnnot;<br>
+<br>
+ Nop.setPacketBegin (MI->isPacketBegin());<br>
+ printInst (&Nop, O, NoAnnot);<br>
+ }<br>
+<br>
+ // Close the packet.<br>
+ if (MI->isPacketEnd())<br>
+ O << PacketPadding << endPacket;<br>
+<br>
+ printInstruction(MI, O);<br>
+ }<br>
+ else {<br>
+ // Prefix the insn opening the packet.<br>
+ if (MI->isPacketBegin())<br>
+ O << PacketPadding << startPacket << '\n';<br>
+<br>
+ printInstruction(MI, O);<br>
+<br>
+ // Suffix the insn closing the packet.<br>
+ if (MI->isPacketEnd())<br>
+ // Suffix the packet in a new line always, since the GNU assembler has<br>
+ // issues with a closing brace on the same line as CONST{32,64}.<br>
+ O << '\n' << PacketPadding << endPacket;<br>
+ }<br>
+<br>
+ printAnnotation(O, Annot);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ const MCOperand& MO = MI->getOperand(OpNo);<br>
+<br>
+ if (MO.isReg()) {<br>
+ O << getRegisterName(MO.getReg());<br>
+ } else if(MO.isExpr()) {<br>
+ O << *MO.getExpr();<br>
+ } else if(MO.isImm()) {<br>
+ printImmOperand(MI, OpNo, O);<br>
+ } else {<br>
+ llvm_unreachable("Unknown operand");<br>
+ }<br>
+}<br>
+<br>
+void HexagonInstPrinter::printImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ const MCOperand& MO = MI->getOperand(OpNo);<br>
+<br>
+ if(MO.isExpr()) {<br>
+ O << *MO.getExpr();<br>
+ } else if(MO.isImm()) {<br>
+ O << MI->getOperand(OpNo).getImm();<br>
+ } else {<br>
+ llvm_unreachable("Unknown operand");<br>
+ }<br>
+}<br>
+<br>
+void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ const MCOperand &MO = MI->getOperand(OpNo);<br>
+ const MCInstrDesc &MII = getMII().get(MI->getOpcode());<br>
+<br>
+ assert((isExtendable(MII.TSFlags) || isExtended(MII.TSFlags)) &&<br>
+ "Expecting an extendable operand");<br>
+<br>
+ if (MO.isExpr() || isExtended(MII.TSFlags)) {<br>
+ O << "#";<br>
+ } else if (MO.isImm()) {<br>
+ int ImmValue = MO.getImm();<br>
+ if (ImmValue < getMinValue(MII.TSFlags) ||<br>
+ ImmValue > getMaxValue(MII.TSFlags))<br>
+ O << "#";<br>
+ }<br>
+ printOperand(MI, OpNo, O);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printUnsignedImmOperand(const MCInst *MI,<br>
+ unsigned OpNo, raw_ostream &O) const {<br>
+ O << MI->getOperand(OpNo).getImm();<br>
+}<br>
+<br>
+void HexagonInstPrinter::printNegImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ O << -MI->getOperand(OpNo).getImm();<br>
+}<br>
+<br>
+void HexagonInstPrinter::printNOneImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ O << -1;<br>
+}<br>
+<br>
+void HexagonInstPrinter::printMEMriOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ const MCOperand& MO0 = MI->getOperand(OpNo);<br>
+ const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>
+<br>
+ O << getRegisterName(MO0.getReg());<br>
+ O << " + #" << MO1.getImm();<br>
+}<br>
+<br>
+void HexagonInstPrinter::printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ const MCOperand& MO0 = MI->getOperand(OpNo);<br>
+ const MCOperand& MO1 = MI->getOperand(OpNo + 1);<br>
+<br>
+ O << getRegisterName(MO0.getReg()) << ", #" << MO1.getImm();<br>
+}<br>
+<br>
+void HexagonInstPrinter::printGlobalOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>
+<br>
+ printOperand(MI, OpNo, O);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printJumpTable(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>
+<br>
+ printOperand(MI, OpNo, O);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printConstantPool(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ assert(MI->getOperand(OpNo).isExpr() && "Expecting expression");<br>
+<br>
+ printOperand(MI, OpNo, O);<br>
+}<br>
+<br>
+void HexagonInstPrinter::printBranchOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+ // Branches can take an immediate operand. This is used by the branch<br>
+ // selection pass to print $+8, an eight byte displacement from the PC.<br>
+ llvm_unreachable("Unknown branch operand.");<br>
+}<br>
+<br>
+void HexagonInstPrinter::printCallOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+}<br>
+<br>
+void HexagonInstPrinter::printAbsAddrOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+}<br>
+<br>
+void HexagonInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const {<br>
+}<br>
+<br>
+void HexagonInstPrinter::printSymbol(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O, bool hi) const {<br>
+ assert(MI->getOperand(OpNo).isImm() && "Unknown symbol operand");<br>
+<br>
+ O << '#' << (hi ? "HI" : "LO") << "(#";<br>
+ printOperand(MI, OpNo, O);<br>
+ O << ')';<br>
+}<br>
<br>
Added: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h?rev=220584&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h?rev=220584&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h (added)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonInstPrinter.h Fri Oct 24 14:00:32 2014<br>
@@ -0,0 +1,87 @@<br>
+//===-- HexagonInstPrinter.h - Convert Hexagon MCInst to assembly syntax --===//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This class prints an Hexagon MCInst to a .s file.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#ifndef LLVM_LIB_TARGET_HEXAGON_INSTPRINTER_HEXAGONINSTPRINTER_H<br>
+#define LLVM_LIB_TARGET_HEXAGON_INSTPRINTER_HEXAGONINSTPRINTER_H<br>
+<br>
+#include "llvm/MC/MCInstPrinter.h"<br>
+#include "llvm/MC/MCInstrInfo.h"<br>
+<br>
+namespace llvm {<br>
+ class HexagonMCInst;<br>
+<br>
+ class HexagonInstPrinter : public MCInstPrinter {<br>
+ public:<br>
+ explicit HexagonInstPrinter(const MCAsmInfo &MAI,<br>
+ const MCInstrInfo &MII,<br>
+ const MCRegisterInfo &MRI)<br>
+ : MCInstPrinter(MAI, MII, MRI), MII(MII) {}<br>
+<br>
+ void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;<br>
+ void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);<br>
+ virtual StringRef getOpcodeName(unsigned Opcode) const;<br>
+ void printInstruction(const MCInst *MI, raw_ostream &O);<br>
+ StringRef getRegName(unsigned RegNo) const;<br>
+ static const char *getRegisterName(unsigned RegNo);<br>
+<br>
+ void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
+ void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
+ void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
+ void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const;<br>
+ void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printFrameIndexOperand(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const;<br>
+ void printBranchOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printCallOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printAbsAddrOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printPredicateOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printGlobalOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)<br>
+ const;<br>
+ void printJumpTable(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;<br>
+<br>
+ void printConstantPool(const MCInst *MI, unsigned OpNo,<br>
+ raw_ostream &O) const;<br>
+<br>
+ void printSymbolHi(const MCInst *MI, unsigned OpNo, raw_ostream &O) const<br>
+ { printSymbol(MI, OpNo, O, true); }<br>
+ void printSymbolLo(const MCInst *MI, unsigned OpNo, raw_ostream &O) const<br>
+ { printSymbol(MI, OpNo, O, false); }<br>
+<br>
+ const MCInstrInfo &getMII() const {<br>
+ return MII;<br>
+ }<br>
+<br>
+ protected:<br>
+ void printSymbol(const MCInst *MI, unsigned OpNo, raw_ostream &O, bool hi)<br>
+ const;<br>
+<br>
+ static const char PacketPadding;<br>
+<br>
+ private:<br>
+ const MCInstrInfo &MII;<br>
+<br>
+ };<br>
+<br>
+} // end namespace llvm<br>
+<br>
+#endif<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp Fri Oct 24 14:00:32 2014<br>
@@ -38,7 +38,7 @@ enum class ParseField { duplex = 0x0, la<br>
uint32_t getPacketBits(HexagonMCInst const &HMI) {<br>
unsigned const ParseFieldOffset = 14;<br>
ParseField Field = HMI.isPacketEnd() ? ParseField::end : ParseField::last0;<br>
- return static_cast <uint32_t> (Field) << ParseFieldOffset;<br>
+ return static_cast<uint32_t>(Field) << ParseFieldOffset;<br>
}<br>
void emitLittleEndian(uint64_t Binary, raw_ostream &OS) {<br>
OS << static_cast<uint8_t>((Binary >> 0x00) & 0xff);<br>
@@ -57,8 +57,9 @@ void HexagonMCCodeEmitter::EncodeInstruc<br>
SmallVectorImpl<MCFixup> &Fixups,<br>
MCSubtargetInfo const &STI) const {<br>
HexagonMCInst const &HMB = static_cast<HexagonMCInst const &>(MI);<br>
- uint64_t Binary = getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);<br>
- assert(HMB.getDesc().getSize() == 4 && "All instructions should be 32bit");<br>
+ uint64_t Binary =<br>
+ getBinaryCodeForInstr(HMB, Fixups, STI) | getPacketBits(HMB);<br>
+ Binary |= getPacketBits(HMB);<br>
emitLittleEndian(Binary, OS);<br>
++MCNumEmitted;<br>
}<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp Fri Oct 24 14:00:32 2014<br>
@@ -12,68 +12,52 @@<br>
//===----------------------------------------------------------------------===//<br>
<br>
#include "HexagonInstrInfo.h"<br>
+#include "HexagonTargetMachine.h"<br>
#include "MCTargetDesc/HexagonBaseInfo.h"<br>
#include "MCTargetDesc/HexagonMCInst.h"<br>
#include "MCTargetDesc/HexagonMCTargetDesc.h"<br>
+#include "llvm/Support/TargetRegistry.h"<br>
<br>
using namespace llvm;<br>
<br>
-// Return the slots used by the insn.<br>
-unsigned HexagonMCInst::getUnits(const HexagonTargetMachine* TM) const {<br>
- const HexagonInstrInfo *QII = TM->getSubtargetImpl()->getInstrInfo();<br>
- const InstrItineraryData *II =<br>
- TM->getSubtargetImpl()->getInstrItineraryData();<br>
- const InstrStage*<br>
- IS = II->beginStage(QII->get(this->getOpcode()).getSchedClass());<br>
+HexagonMCInst::HexagonMCInst(unsigned op)<br>
+ : packetBegin(false), packetEnd(false),<br>
+ MCID(llvm::TheHexagonTarget.createMCInstrInfo()->get(op)) {<br>
+ assert(MCID.getSize() == 4 && "All instructions should be 32bit");<br>
+ setOpcode(op);<br>
+}<br>
+<br>
+bool HexagonMCInst::isPacketBegin() const { return packetBegin; }<br>
+bool HexagonMCInst::isPacketEnd() const { return packetEnd; }<br>
+void HexagonMCInst::setPacketEnd(bool Y) { packetEnd = Y; }<br>
+void HexagonMCInst::setPacketBegin(bool Y) { packetBegin = Y; }<br>
+<br>
+unsigned HexagonMCInst::getUnits(HexagonTargetMachine const &TM) const {<br>
+ const HexagonInstrInfo *QII = TM.getSubtargetImpl()->getInstrInfo();<br>
+ const InstrItineraryData *II = TM.getSubtargetImpl()->getInstrItineraryData();<br>
+ const InstrStage *IS =<br>
+ II->beginStage(QII->get(this->getOpcode()).getSchedClass());<br>
<br>
return (IS->getUnits());<br>
}<br>
<br>
-// Return the Hexagon ISA class for the insn.<br>
-unsigned HexagonMCInst::getType() const {<br>
- const uint64_t F = MCID->TSFlags;<br>
-<br>
- return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);<br>
-}<br>
-<br>
-// Return whether the insn is an actual insn.<br>
-bool HexagonMCInst::isCanon() const {<br>
- return (!MCID->isPseudo() &&<br>
- !isPrefix() &&<br>
- getType() != HexagonII::TypeENDLOOP);<br>
-}<br>
-<br>
-// Return whether the insn is a prefix.<br>
-bool HexagonMCInst::isPrefix() const {<br>
- return (getType() == HexagonII::TypePREFIX);<br>
-}<br>
-<br>
-// Return whether the insn is solo, i.e., cannot be in a packet.<br>
-bool HexagonMCInst::isSolo() const {<br>
- const uint64_t F = MCID->TSFlags;<br>
- return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);<br>
-}<br>
-<br>
-// Return whether the insn is a new-value consumer.<br>
bool HexagonMCInst::isNewValue() const {<br>
- const uint64_t F = MCID->TSFlags;<br>
+ const uint64_t F = MCID.TSFlags;<br>
return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);<br>
}<br>
<br>
-// Return whether the instruction is a legal new-value producer.<br>
bool HexagonMCInst::hasNewValue() const {<br>
- const uint64_t F = MCID->TSFlags;<br>
+ const uint64_t F = MCID.TSFlags;<br>
return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);<br>
}<br>
<br>
-// Return the operand that consumes or produces a new value.<br>
-const MCOperand& HexagonMCInst::getNewValue() const {<br>
- const uint64_t F = MCID->TSFlags;<br>
- const unsigned O = (F >> HexagonII::NewValueOpPos) &<br>
- HexagonII::NewValueOpMask;<br>
- const MCOperand& MCO = getOperand(O);<br>
+MCOperand const &HexagonMCInst::getNewValue() const {<br>
+ const uint64_t F = MCID.TSFlags;<br>
+ const unsigned O =<br>
+ (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;<br>
+ const MCOperand &MCO = getOperand(O);<br>
<br>
- assert ((isNewValue() || hasNewValue()) && MCO.isReg());<br>
+ assert((isNewValue() || hasNewValue()) && MCO.isReg());<br>
return (MCO);<br>
}<br>
<br>
@@ -84,7 +68,6 @@ const MCOperand& HexagonMCInst::getNewVa<br>
// 2) For immediate extended operands, return true only if the value is<br>
// out-of-range.<br>
// 3) For global address, always return true.<br>
-<br>
bool HexagonMCInst::isConstExtended(void) const {<br>
if (isExtended())<br>
return true;<br>
@@ -93,9 +76,9 @@ bool HexagonMCInst::isConstExtended(void<br>
return false;<br>
<br>
short ExtOpNum = getCExtOpNum();<br>
- int MinValue = getMinValue();<br>
- int MaxValue = getMaxValue();<br>
- const MCOperand& MO = getOperand(ExtOpNum);<br>
+ int MinValue = getMinValue();<br>
+ int MaxValue = getMaxValue();<br>
+ const MCOperand &MO = getOperand(ExtOpNum);<br>
<br>
// We could be using an instruction with an extendable immediate and shoehorn<br>
// a global address into it. If it is a global address it will be constant<br>
@@ -114,62 +97,51 @@ bool HexagonMCInst::isConstExtended(void<br>
return (ImmValue < MinValue || ImmValue > MaxValue);<br>
}<br>
<br>
-// Return whether the instruction must be always extended.<br>
bool HexagonMCInst::isExtended(void) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
+ const uint64_t F = MCID.TSFlags;<br>
return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;<br>
}<br>
<br>
-// Return true if the instruction may be extended based on the operand value.<br>
bool HexagonMCInst::isExtendable(void) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
+ const uint64_t F = MCID.TSFlags;<br>
return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;<br>
}<br>
<br>
-// Return number of bits in the constant extended operand.<br>
unsigned HexagonMCInst::getBitCount(void) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
+ const uint64_t F = MCID.TSFlags;<br>
return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);<br>
}<br>
<br>
-// Return constant extended operand number.<br>
unsigned short HexagonMCInst::getCExtOpNum(void) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
+ const uint64_t F = MCID.TSFlags;<br>
return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);<br>
}<br>
<br>
-// Return whether the operand can be constant extended.<br>
bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
- return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)<br>
- == OperandNum;<br>
+ const uint64_t F = MCID.TSFlags;<br>
+ return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==<br>
+ OperandNum;<br>
}<br>
<br>
-// Return the min value that a constant extendable operand can have<br>
-// without being extended.<br>
int HexagonMCInst::getMinValue(void) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
- unsigned isSigned = (F >> HexagonII::ExtentSignedPos)<br>
- & HexagonII::ExtentSignedMask;<br>
- unsigned bits = (F >> HexagonII::ExtentBitsPos)<br>
- & HexagonII::ExtentBitsMask;<br>
+ const uint64_t F = MCID.TSFlags;<br>
+ unsigned isSigned =<br>
+ (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>
+ unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>
<br>
- if (isSigned) // if value is signed<br>
+ if (isSigned)<br>
return -1U << (bits - 1);<br>
else<br>
return 0;<br>
}<br>
<br>
-// Return the max value that a constant extendable operand can have<br>
-// without being extended.<br>
int HexagonMCInst::getMaxValue(void) const {<br>
- const uint64_t F = MCID->TSFlags;<br>
- unsigned isSigned = (F >> HexagonII::ExtentSignedPos)<br>
- & HexagonII::ExtentSignedMask;<br>
- unsigned bits = (F >> HexagonII::ExtentBitsPos)<br>
- & HexagonII::ExtentBitsMask;<br>
+ const uint64_t F = MCID.TSFlags;<br>
+ unsigned isSigned =<br>
+ (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;<br>
+ unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;<br>
<br>
- if (isSigned) // if value is signed<br>
+ if (isSigned)<br>
return ~(-1U << (bits - 1));<br>
else<br>
return ~(-1U << bits);<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.h Fri Oct 24 14:00:32 2014<br>
@@ -14,87 +14,55 @@<br>
#ifndef LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINST_H<br>
#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCINST_H<br>
<br>
-#include "HexagonTargetMachine.h"<br>
#include "llvm/MC/MCInst.h"<br>
<br>
namespace llvm {<br>
- class MCOperand;<br>
-<br>
- class HexagonMCInst: public MCInst {<br>
- // MCID is set during instruction lowering.<br>
- // It is needed in order to access TSFlags for<br>
- // use in checking MC instruction properties.<br>
- const MCInstrDesc *MCID;<br>
-<br>
- // Packet start and end markers<br>
- unsigned packetStart: 1, packetEnd: 1;<br>
-<br>
- public:<br>
- explicit HexagonMCInst():<br>
- MCInst(), MCID(nullptr), packetStart(0), packetEnd(0) {};<br>
- HexagonMCInst(const MCInstrDesc& mcid):<br>
- MCInst(), MCID(&mcid), packetStart(0), packetEnd(0) {};<br>
-<br>
- bool isPacketStart() const { return (packetStart); };<br>
- bool isPacketEnd() const { return (packetEnd); };<br>
- void setPacketStart(bool Y) { packetStart = Y; };<br>
- void setPacketEnd(bool Y) { packetEnd = Y; };<br>
- void resetPacket() { setPacketStart(false); setPacketEnd(false); };<br>
-<br>
- // Return the slots used by the insn.<br>
- unsigned getUnits(const HexagonTargetMachine* TM) const;<br>
-<br>
- // Return the Hexagon ISA class for the insn.<br>
- unsigned getType() const;<br>
-<br>
- void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; };<br>
- const MCInstrDesc& getDesc(void) const { return *MCID; };<br>
-<br>
- // Return whether the insn is an actual insn.<br>
- bool isCanon() const;<br>
-<br>
- // Return whether the insn is a prefix.<br>
- bool isPrefix() const;<br>
-<br>
- // Return whether the insn is solo, i.e., cannot be in a packet.<br>
- bool isSolo() const;<br>
-<br>
- // Return whether the instruction needs to be constant extended.<br>
- bool isConstExtended() const;<br>
-<br>
- // Return constant extended operand number.<br>
- unsigned short getCExtOpNum(void) const;<br>
-<br>
- // Return whether the insn is a new-value consumer.<br>
- bool isNewValue() const;<br>
-<br>
- // Return whether the instruction is a legal new-value producer.<br>
- bool hasNewValue() const;<br>
-<br>
- // Return the operand that consumes or produces a new value.<br>
- const MCOperand& getNewValue() const;<br>
-<br>
- // Return number of bits in the constant extended operand.<br>
- unsigned getBitCount(void) const;<br>
-<br>
- private:<br>
- // Return whether the instruction must be always extended.<br>
- bool isExtended() const;<br>
-<br>
- // Return true if the insn may be extended based on the operand value.<br>
- bool isExtendable() const;<br>
-<br>
- // Return true if the operand can be constant extended.<br>
- bool isOperandExtended(const unsigned short OperandNum) const;<br>
-<br>
- // Return the min value that a constant extendable operand can have<br>
- // without being extended.<br>
- int getMinValue() const;<br>
-<br>
- // Return the max value that a constant extendable operand can have<br>
- // without being extended.<br>
- int getMaxValue() const;<br>
- };<br>
+class MCInstrDesc;<br>
+class MCOperand;<br>
+class HexagonTargetMachine;<br>
+<br>
+class HexagonMCInst : public MCInst {<br>
+public:<br>
+ explicit HexagonMCInst(unsigned op);<br>
+<br>
+ /// 10.6 Instruction Packets<br>
+ bool isPacketBegin() const;<br>
+ /// \brief Is this marked as last in packet.<br>
+ bool isPacketEnd() const;<br>
+ void setPacketBegin(bool Y);<br>
+ /// \brief Mark this as last in packet.<br>
+ void setPacketEnd(bool Y);<br>
+ /// \brief Return the slots used.<br>
+ unsigned getUnits(HexagonTargetMachine const &TM) const;<br>
+ bool isConstExtended() const;<br>
+ /// \brief Return constant extended operand number.<br>
+ unsigned short getCExtOpNum(void) const;<br>
+ /// \brief Return whether this is a new-value consumer.<br>
+ bool isNewValue() const;<br>
+ /// \brief Return whether this is a legal new-value producer.<br>
+ bool hasNewValue() const;<br>
+ /// \brief Return the operand that consumes or produces a new value.<br>
+ MCOperand const &getNewValue() const;<br>
+ /// \brief Return number of bits in the constant extended operand.<br>
+ unsigned getBitCount(void) const;<br>
+<br>
+private:<br>
+ /// \brief Return whether this must be always extended.<br>
+ bool isExtended() const;<br>
+ /// \brief Return true if this may be extended based on the operand value.<br>
+ bool isExtendable() const;<br>
+ /// \brief Return if the operand can be constant extended.<br>
+ bool isOperandExtended(unsigned short const OperandNum) const;<br>
+ /// \brief Return the min value that a constant extendable operand can have<br>
+ /// without being extended.<br>
+ int getMinValue() const;<br>
+ /// \brief Return the max value that a constant extendable operand can have<br>
+ /// without being extended.<br>
+ int getMaxValue() const;<br>
+ bool packetBegin;<br>
+ bool packetEnd;<br>
+ MCInstrDesc const &MCID;<br>
+};<br>
}<br>
<br>
#endif<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp Fri Oct 24 14:00:32 2014<br>
@@ -13,7 +13,7 @@<br>
<br>
#include "HexagonMCTargetDesc.h"<br>
#include "HexagonMCAsmInfo.h"<br>
-#include "InstPrinter/HexagonInstPrinter.h"<br>
+#include "MCTargetDesc/HexagonInstPrinter.h"<br>
#include "llvm/MC/MCCodeGenInfo.h"<br>
#include "llvm/MC/MCInstrInfo.h"<br>
#include "llvm/MC/MCRegisterInfo.h"<br>
@@ -34,7 +34,7 @@ using namespace llvm;<br>
#define GET_REGINFO_MC_DESC<br>
#include "HexagonGenRegisterInfo.inc"<br>
<br>
-static MCInstrInfo *createHexagonMCInstrInfo() {<br>
+static llvm::MCInstrInfo *createHexagonMCInstrInfo() {<br>
MCInstrInfo *X = new MCInstrInfo();<br>
InitHexagonMCInstrInfo(X);<br>
return X;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h Fri Oct 24 14:00:32 2014<br>
@@ -15,6 +15,8 @@<br>
#define LLVM_LIB_TARGET_HEXAGON_MCTARGETDESC_HEXAGONMCTARGETDESC_H<br>
<br>
namespace llvm {<br>
+struct InstrItinerary;<br>
+struct InstrStage;<br>
class MCCodeEmitter;<br>
class MCContext;<br>
class MCInstrInfo;<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/LLVMBuild.txt Fri Oct 24 14:00:32 2014<br>
@@ -19,5 +19,5 @@<br>
type = Library<br>
name = HexagonDesc<br>
parent = Hexagon<br>
-required_libraries = HexagonAsmPrinter HexagonInfo MC Support<br>
+required_libraries = HexagonInfo MC Support<br>
add_to_library_groups = Hexagon<br>
<br>
Modified: llvm/trunk/lib/Target/Hexagon/Makefile<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Makefile?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/Makefile?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Hexagon/Makefile (original)<br>
+++ llvm/trunk/lib/Target/Hexagon/Makefile Fri Oct 24 14:00:32 2014<br>
@@ -14,12 +14,13 @@ TARGET = Hexagon<br>
BUILT_SOURCES = HexagonGenRegisterInfo.inc \<br>
HexagonGenInstrInfo.inc \<br>
HexagonGenAsmWriter.inc \<br>
- HexagonGenDAGISel.inc HexagonGenSubtargetInfo.inc \<br>
- HexagonGenCallingConv.inc \<br>
- HexagonGenDFAPacketizer.inc \<br>
- HexagonGenMCCodeEmitter.inc \<br>
- HexagonGenDisassemblerTables.inc<br>
-<br>
-DIRS = InstPrinter TargetInfo MCTargetDesc Disassembler<br>
-<br>
-include $(LEVEL)/Makefile.common<br>
+ HexagonGenDAGISel.inc \<br>
+ HexagonGenSubtargetInfo.inc \<br>
+ HexagonGenCallingConv.inc \<br>
+ HexagonGenDFAPacketizer.inc \<br>
+ HexagonGenMCCodeEmitter.inc \<br>
+ HexagonGenDisassemblerTables.inc<br>
+<br>
+DIRS = TargetInfo MCTargetDesc Disassembler<br>
+<br>
+include $(LEVEL)/Makefile.common<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/Hexagon/alu32.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32.txt?rev=220584&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/alu32.txt?rev=220584&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/Hexagon/alu32.txt (added)<br>
+++ llvm/trunk/test/MC/Disassembler/Hexagon/alu32.txt Fri Oct 24 14:00:32 2014<br>
@@ -0,0 +1,4 @@<br>
+# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s<br>
+<br>
+0x11 0xdf 0x15 0xf3<br>
+# CHECK: r17 = add(r21, r31)<br>
<br>
Added: llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg?rev=220584&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg?rev=220584&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg (added)<br>
+++ llvm/trunk/test/MC/Disassembler/Hexagon/lit.local.cfg Fri Oct 24 14:00:32 2014<br>
@@ -0,0 +1,3 @@<br>
+if 'Hexagon' not in config.root.targets:<br>
+ config.unsupported = True<br>
+<br>
<br>
Modified: llvm/trunk/unittests/MC/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/CMakeLists.txt?rev=220584&r1=220583&r2=220584&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/CMakeLists.txt?rev=220584&r1=220583&r2=220584&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/unittests/MC/CMakeLists.txt (original)<br>
+++ llvm/trunk/unittests/MC/CMakeLists.txt Fri Oct 24 14:00:32 2014<br>
@@ -7,9 +7,3 @@ add_llvm_unittest(MCTests<br>
StringTableBuilderTest.cpp<br>
YAMLTest.cpp<br>
)<br>
-<br>
-foreach(t ${LLVM_TARGETS_TO_BUILD})<br>
- if (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}")<br>
- add_subdirectory(${t})<br>
- endif (IS_DIRECTORY "${CMAKE_CURRENT_LIST_DIR}/${t}")<br>
-endforeach()<br>
<br>
Removed: llvm/trunk/unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp?rev=220583&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp?rev=220583&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp (original)<br>
+++ llvm/trunk/unittests/MC/Hexagon/HexagonMCCodeEmitterTest.cpp (removed)<br>
@@ -1,53 +0,0 @@<br>
-#include "gtest/gtest.h"<br>
-<br>
-#include <memory><br>
-<br>
-#include "llvm/MC/MCCodeEmitter.h"<br>
-#include "llvm/MC/MCContext.h"<br>
-#include "llvm/Support/raw_ostream.h"<br>
-#include "llvm/Support/TargetRegistry.h"<br>
-#include "llvm/Support/TargetSelect.h"<br>
-<br>
-#include "MCTargetDesc/HexagonMCInst.h"<br>
-#include "MCTargetDesc/HexagonMCTargetDesc.h"<br>
-<br>
-namespace {<br>
-class TestEmitter {<br>
-public:<br>
- TestEmitter() : Triple("hexagon-unknown-elf") {<br>
- LLVMInitializeHexagonTargetInfo();<br>
- LLVMInitializeHexagonTarget();<br>
- LLVMInitializeHexagonTargetMC();<br>
- std::string error;<br>
- Target = llvm::TargetRegistry::lookupTarget("hexagon", error);<br>
- assert(Target != nullptr && "Expected to find target");<br>
- assert(error.empty() && "Error should be empty if we have a target");<br>
- RegisterInfo = Target->createMCRegInfo(Triple);<br>
- assert(RegisterInfo != nullptr && "Expecting to find register info");<br>
- AsmInfo = Target->createMCAsmInfo(*RegisterInfo, Triple);<br>
- assert(AsmInfo != nullptr && "Expecting to find asm info");<br>
- Context = new llvm::MCContext(AsmInfo, RegisterInfo, nullptr);<br>
- assert(Context != nullptr && "Expecting to create a context");<br>
- Subtarget = Target->createMCSubtargetInfo(Triple, "hexagonv4", "");<br>
- assert(Subtarget != nullptr && "Expecting to find a subtarget");<br>
- InstrInfo = Target->createMCInstrInfo();<br>
- assert(InstrInfo != nullptr && "Expecting to find instr info");<br>
- Emitter = Target->createMCCodeEmitter(*InstrInfo, *RegisterInfo, *Subtarget,<br>
- *Context);<br>
- assert(Emitter != nullptr);<br>
- }<br>
- std::string Triple;<br>
- llvm::Target const *Target;<br>
- llvm::MCRegisterInfo *RegisterInfo;<br>
- llvm::MCAsmInfo *AsmInfo;<br>
- llvm::MCContext *Context;<br>
- llvm::MCSubtargetInfo *Subtarget;<br>
- llvm::MCInstrInfo *InstrInfo;<br>
- llvm::MCCodeEmitter *Emitter;<br>
-};<br>
-TestEmitter Emitter;<br>
-}<br>
-<br>
-TEST(HexagonMCCodeEmitter, emitter_creation) {<br>
- ASSERT_NE(nullptr, Emitter.Emitter);<br>
-}<br>
<br>
<br>
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</blockquote></div><br></div></div>