<div dir="ltr">One of the main builders hit this:<div><br></div><div><a href="http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/3571/steps/build_Lld/logs/stdio">http://lab.llvm.org:8011/builders/lld-x86_64-darwin13/builds/3571/steps/build_Lld/logs/stdio</a><br></div><div><br></div><div>I suspect using a 2-release old host Clang means you get significantly less useful warnings. In fact, I'm pretty sure that this *exact* issue (and warning) has come up before and we suggested using a more recent compiler in order to get more useful warnings. I've gone ahead and fixed the issue in r219531, but as this is the second time it has come up, please both ingrain the usage of llvm_unreachable into this type of pattern of code, and consider a more recent host compiler.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Oct 10, 2014 at 2:12 PM, reed kotler <span dir="ltr"><<a href="mailto:rkotler@mips.com" target="_blank">rkotler@mips.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div bgcolor="#FFFFFF" text="#000000">
<div>I do build with -werror<br>
<br>
/home/rkotler/workspace/llvm/configure --enable-werror
CXX=/home/rkotler/cla<br>
ng-3.4/bin/clang++ CC=/home/rkotler/clang-3.4/bin/clang
--prefix=/home/rkotler/l<br>
lvmw/install<br>
<br>
I will fix right away.. Can you send me a listing of the errors?<br>
<br>
Sorry about that. I thought my b<div><div class="h5"><br>
On 10/10/2014 02:09 PM, Chandler Carruth wrote:<br>
</div></div></div><div><div class="h5">
<blockquote type="cite">
<div dir="ltr">This is full of uninitialized warnings and breaks
all builds with -Werror. Please fix or revert quickly, thanks!</div>
<div class="gmail_extra"><br>
<div class="gmail_quote">On Fri, Oct 10, 2014 at 1:46 PM, Reed
Kotler <span dir="ltr"><<a href="mailto:rkotler@mips.com" target="_blank">rkotler@mips.com</a>></span>
wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author:
rkotler<br>
Date: Fri Oct 10 15:46:28 2014<br>
New Revision: 219530<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=219530&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=219530&view=rev</a><br>
Log:<br>
Implement floating point compare for mips fast-isel<br>
<br>
Summary: Expand SelectCmp to handle floating point compare<br>
<br>
Test Plan:<br>
fpcmpa.ll<br>
run 4 flavors of test-suite, mips32 r1/r2 O0/O2<br>
<br>
Reviewers: dsanders<br>
<br>
Reviewed By: dsanders<br>
<br>
Subscribers: llvm-commits, rfuhler<br>
<br>
Differential Revision: <a href="http://reviews.llvm.org/D5567" target="_blank">http://reviews.llvm.org/D5567</a><br>
<br>
Added:<br>
llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll<br>
Modified:<br>
llvm/trunk/lib/Target/Mips/MipsFastISel.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/Mips/MipsFastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=219530&r1=219529&r2=219530&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFastISel.cpp?rev=219530&r1=219529&r2=219530&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/Mips/MipsFastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/Mips/MipsFastISel.cpp Fri Oct 10
15:46:28 2014<br>
@@ -578,8 +578,8 @@ bool MipsFastISel::SelectCmp(const Instr<br>
if (RightReg == 0)<br>
return false;<br>
unsigned ResultReg =
createResultReg(&Mips::GPR32RegClass);<br>
-<br>
- switch (CI->getPredicate()) {<br>
+ CmpInst::Predicate P = CI->getPredicate();<br>
+ switch (P) {<br>
default:<br>
return false;<br>
case CmpInst::ICMP_EQ: {<br>
@@ -634,6 +634,60 @@ bool MipsFastISel::SelectCmp(const
Instr<br>
EmitInst(Mips::XORi,
ResultReg).addReg(TempReg).addImm(1);<br>
break;<br>
}<br>
+ case CmpInst::FCMP_OEQ:<br>
+ case CmpInst::FCMP_UNE:<br>
+ case CmpInst::FCMP_OLT:<br>
+ case CmpInst::FCMP_OLE:<br>
+ case CmpInst::FCMP_OGT:<br>
+ case CmpInst::FCMP_OGE: {<br>
+ if (UnsupportedFPMode)<br>
+ return false;<br>
+ bool IsFloat = Left->getType()->isFloatTy();<br>
+ bool IsDouble = Left->getType()->isDoubleTy();<br>
+ if (!IsFloat && !IsDouble)<br>
+ return false;<br>
+ unsigned Opc, CondMovOpc;<br>
+ switch (P) {<br>
+ case CmpInst::FCMP_OEQ:<br>
+ Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;<br>
+ CondMovOpc = Mips::MOVT_I;<br>
+ break;<br>
+ case CmpInst::FCMP_UNE:<br>
+ Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;<br>
+ CondMovOpc = Mips::MOVF_I;<br>
+ break;<br>
+ case CmpInst::FCMP_OLT:<br>
+ Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;<br>
+ CondMovOpc = Mips::MOVT_I;<br>
+ break;<br>
+ case CmpInst::FCMP_OLE:<br>
+ Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;<br>
+ CondMovOpc = Mips::MOVT_I;<br>
+ break;<br>
+ case CmpInst::FCMP_OGT:<br>
+ Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;<br>
+ CondMovOpc = Mips::MOVF_I;<br>
+ break;<br>
+ case CmpInst::FCMP_OGE:<br>
+ Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;<br>
+ CondMovOpc = Mips::MOVF_I;<br>
+ break;<br>
+ default:<br>
+ break;<br>
+ }<br>
+ unsigned RegWithZero =
createResultReg(&Mips::GPR32RegClass);<br>
+ unsigned RegWithOne =
createResultReg(&Mips::GPR32RegClass);<br>
+ EmitInst(Mips::ADDiu,
RegWithZero).addReg(Mips::ZERO).addImm(0);<br>
+ EmitInst(Mips::ADDiu,
RegWithOne).addReg(Mips::ZERO).addImm(1);<br>
+ EmitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg(<br>
+ Mips::FCC0, RegState::ImplicitDefine);<br>
+ MachineInstrBuilder MI = EmitInst(CondMovOpc,
ResultReg)<br>
+ .addReg(RegWithOne)<br>
+ .addReg(Mips::FCC0)<br>
+ .addReg(RegWithZero,
RegState::Implicit);<br>
+ MI->tieOperands(0, 3);<br>
+ break;<br>
+ }<br>
}<br>
updateValueMap(I, ResultReg);<br>
return true;<br>
<br>
Added: llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll?rev=219530&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll?rev=219530&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll (added)<br>
+++ llvm/trunk/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll Fri Oct
10 15:46:28 2014<br>
@@ -0,0 +1,254 @@<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0
-mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \<br>
+; RUN: < %s | FileCheck %s<br>
+; RUN: llc -march=mipsel -relocation-model=pic -O0
-mips-fast-isel -fast-isel-abort -mcpu=mips32 \<br>
+; RUN: < %s | FileCheck %s<br>
+<br>
+@f1 = common global float 0.000000e+00, align 4<br>
+@f2 = common global float 0.000000e+00, align 4<br>
+@b1 = common global i32 0, align 4<br>
+@d1 = common global double 0.000000e+00, align 8<br>
+@d2 = common global double 0.000000e+00, align 8<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @feq1() {<br>
+entry:<br>
+ %0 = load float* @f1, align 4<br>
+ %1 = load float* @f2, align 4<br>
+ %cmp = fcmp oeq float %0, %1<br>
+; CHECK-LABEL: feq1:<br>
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]],
%got(f2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]],
%got(f1)(${{[0-9]+}})<br>
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]],
0($[[REG_F2_GOT]])<br>
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]],
0($[[REG_F1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]<br>
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @fne1() {<br>
+entry:<br>
+ %0 = load float* @f1, align 4<br>
+ %1 = load float* @f2, align 4<br>
+ %cmp = fcmp une float %0, %1<br>
+; CHECK-LABEL: fne1:<br>
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]],
%got(f2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]],
%got(f1)(${{[0-9]+}})<br>
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]],
0($[[REG_F2_GOT]])<br>
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]],
0($[[REG_F1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]<br>
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @flt1() {<br>
+entry:<br>
+ %0 = load float* @f1, align 4<br>
+ %1 = load float* @f2, align 4<br>
+ %cmp = fcmp olt float %0, %1<br>
+; CHECK-LABEL: flt1:<br>
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]],
%got(f2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]],
%got(f1)(${{[0-9]+}})<br>
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]],
0($[[REG_F2_GOT]])<br>
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]],
0($[[REG_F1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]]<br>
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @fgt1() {<br>
+entry:<br>
+ %0 = load float* @f1, align 4<br>
+ %1 = load float* @f2, align 4<br>
+ %cmp = fcmp ogt float %0, %1<br>
+; CHECK-LABEL: fgt1:<br>
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]],
%got(f2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]],
%got(f1)(${{[0-9]+}})<br>
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]],
0($[[REG_F2_GOT]])<br>
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]],
0($[[REG_F1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]]<br>
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @fle1() {<br>
+entry:<br>
+ %0 = load float* @f1, align 4<br>
+ %1 = load float* @f2, align 4<br>
+ %cmp = fcmp ole float %0, %1<br>
+; CHECK-LABEL: fle1:<br>
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]],
%got(f2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]],
%got(f1)(${{[0-9]+}})<br>
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]],
0($[[REG_F2_GOT]])<br>
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]],
0($[[REG_F1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]]<br>
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @fge1() {<br>
+entry:<br>
+ %0 = load float* @f1, align 4<br>
+ %1 = load float* @f2, align 4<br>
+ %cmp = fcmp oge float %0, %1<br>
+; CHECK-LABEL: fge1:<br>
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]],
%got(f2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]],
%got(f1)(${{[0-9]+}})<br>
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]],
0($[[REG_F2_GOT]])<br>
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]],
0($[[REG_F1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]]<br>
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @deq1() {<br>
+entry:<br>
+ %0 = load double* @d1, align 8<br>
+ %1 = load double* @d2, align 8<br>
+ %cmp = fcmp oeq double %0, %1<br>
+; CHECK-LABEL: deq1:<br>
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]],
%got(d2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]],
%got(d1)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]],
0($[[REG_D2_GOT]])<br>
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]],
0($[[REG_D1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]<br>
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @dne1() {<br>
+entry:<br>
+ %0 = load double* @d1, align 8<br>
+ %1 = load double* @d2, align 8<br>
+ %cmp = fcmp une double %0, %1<br>
+; CHECK-LABEL: dne1:<br>
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]],
%got(d2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]],
%got(d1)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]],
0($[[REG_D2_GOT]])<br>
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]],
0($[[REG_D1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]<br>
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @dlt1() {<br>
+entry:<br>
+ %0 = load double* @d1, align 8<br>
+ %1 = load double* @d2, align 8<br>
+ %cmp = fcmp olt double %0, %1<br>
+; CHECK-LABEL: dlt1:<br>
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]],
%got(d2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]],
%got(d1)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]],
0($[[REG_D2_GOT]])<br>
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]],
0($[[REG_D1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]]<br>
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @dgt1() {<br>
+entry:<br>
+ %0 = load double* @d1, align 8<br>
+ %1 = load double* @d2, align 8<br>
+ %cmp = fcmp ogt double %0, %1<br>
+; CHECK-LABEL: dgt1:<br>
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]],
%got(d2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]],
%got(d1)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]],
0($[[REG_D2_GOT]])<br>
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]],
0($[[REG_D1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]]<br>
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @dle1() {<br>
+entry:<br>
+ %0 = load double* @d1, align 8<br>
+ %1 = load double* @d2, align 8<br>
+ %cmp = fcmp ole double %0, %1<br>
+; CHECK-LABEL: dle1:<br>
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]],
%got(d2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]],
%got(d1)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]],
0($[[REG_D2_GOT]])<br>
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]],
0($[[REG_D1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]]<br>
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+; Function Attrs: nounwind<br>
+define void @dge1() {<br>
+entry:<br>
+ %0 = load double* @d1, align 8<br>
+ %1 = load double* @d2, align 8<br>
+ %cmp = fcmp oge double %0, %1<br>
+; CHECK-LABEL: dge1:<br>
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]],
%got(d2)(${{[0-9]+}})<br>
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]],
%got(d1)(${{[0-9]+}})<br>
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]],
0($[[REG_D2_GOT]])<br>
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]],
0($[[REG_D1_GOT]])<br>
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0<br>
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1<br>
+; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]]<br>
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0<br>
+ %conv = zext i1 %cmp to i32<br>
+ store i32 %conv, i32* @b1, align 4<br>
+ ret void<br>
+}<br>
+<br>
+<br>
<br>
<br>
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