<div dir="ltr">While it's reasonable to want to do this, I think checking the encoding is the *wrong* way to do it, and checking the encoding in arbitrary places is definitely the wrong way to do it.<div><br></div><div>So, the first thing is to separate the concerns of what you're trying to test. Have a single test file that is responsible for making sure that EVEX encodings are used where possible even without other AVX-512 features.</div><div><br></div><div>Second, I don't think checking *encodings* is quite the right approach. This isn't really about encodings, its about access to the extra registers. I think you should test that directly. Such a test in turn won't be broken if a pass were added to map back to VEX encodings when the extra registers went unused.</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Oct 5, 2014 at 12:42 AM, Demikhovsky, Elena <span dir="ltr"><<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div lang="EN-US" link="blue" vlink="purple">
<div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Register allocation is done AFTER instruction selection. That’s why I want to be sure that EVEX form is chosen.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">Just think about big code that uses all 32 registers. That’s why Intel duplicates all VEX instructions - to reduce amount of spill/fill, allow loop unrolling
an so on. <u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d">I know that VEX instruction is enough if you use 0-15 registers. And it is shorter. In the future we can think about a pass that will work after register allocator
and remap all EVEX instructions to VEX in order to reduce the code size.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<div>
<p class="MsoNormal" style="margin-left:36.0pt">
<u></u><span style="font-family:"Calibri","sans-serif";color:#31849b"><span>-<span style="font:7.0pt "Times New Roman"">
</span></span></span><u></u><span dir="LTR"></span><b><i><span style="color:#31849b"> Elena<u></u><u></u></span></i></b></p>
</div>
<p class="MsoNormal"><span style="font-size:11.0pt;font-family:"Calibri","sans-serif";color:#1f497d"><u></u> <u></u></span></p>
<div>
<div style="border:none;border-top:solid #b5c4df 1.0pt;padding:3.0pt 0cm 0cm 0cm">
<p class="MsoNormal"><b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif"">From:</span></b><span style="font-size:10.0pt;font-family:"Tahoma","sans-serif""> Adam Nemet [mailto:<a href="mailto:anemet@apple.com" target="_blank">anemet@apple.com</a>]
<br>
<b>Sent:</b> Sunday, October 05, 2014 09:16<br>
<b>To:</b> Demikhovsky, Elena<br>
<b>Cc:</b> Chandler Carruth; Robert Khasanov; LLVM Commits</span></p><div><div class="h5"><br>
<b>Subject:</b> Re: [llvm] r218932 - [x86] Remove some of the --show-mc-encoding flags from avx512 tests that<u></u><u></u></div></div><p></p>
</div>
</div><div><div class="h5">
<p class="MsoNormal"><u></u> <u></u></p>
<p class="MsoNormal"><u></u> <u></u></p>
<div>
<div>
<p class="MsoNormal">On Oct 4, 2014, at 3:16 AM, Demikhovsky, Elena <<a href="mailto:elena.demikhovsky@intel.com" target="_blank">elena.demikhovsky@intel.com</a>> wrote:<u></u><u></u></p>
</div>
<p class="MsoNormal"><br>
<br>
<u></u><u></u></p>
<div>
<p class="MsoNormal"><span style="font-size:8.5pt">I put encoding check to be sure that AVX-512 instruction is taken instead of AVX2.<br>
It is very important because AVX-512 allows more registers with same mnemonic.<u></u><u></u></span></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Sure but what about my example when we only use the low 16 vector registers. Is there any reason why we’d want EVEX encoding? Looks like that the assembler and CodeGen disagree. Assembler will pick VEX and CodeGen EVEX. Intel’s XED
assembler picks VEX as well.<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<div>
<p class="MsoNormal">Adam<u></u><u></u></p>
</div>
<div>
<p class="MsoNormal"><u></u> <u></u></p>
</div>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<div>
<p class="MsoNormal"><span style="font-size:8.5pt">- Elena<br>
<br>
<br>
-----Original Message-----<br>
From: Adam Nemet [<a href="mailto:anemet@apple.com" target="_blank">mailto:anemet@apple.com</a>]<span> </span><br>
Sent: Friday, October 03, 2014 21:57<br>
To: Chandler Carruth; Demikhovsky, Elena; Robert Khasanov<br>
Cc: LLVM Commits<br>
Subject: Re: [llvm] r218932 - [x86] Remove some of the --show-mc-encoding flags from avx512 tests that<br>
<br>
<br>
On Oct 2, 2014, at 9:30 PM, Adam Nemet <<a href="mailto:anemet@apple.com" target="_blank">anemet@apple.com</a>> wrote:<br>
<br>
<br>
<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8.5pt">On Oct 2, 2014, at 5:36 PM, Chandler Carruth <<a href="mailto:chandlerc@gmail.com" target="_blank">chandlerc@gmail.com</a>> wrote:<br>
<br>
<br>
<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8.5pt">Author: chandlerc<br>
Date: Thu Oct 2 19:36:29 2014<br>
New Revision: 218932<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=218932&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=218932&view=rev</a><br>
Log:<br>
[x86] Remove some of the --show-mc-encoding flags from avx512 tests<span> </span><br>
that need to be updated for the new vector shuffle lowering.<br>
<br>
After talking to Adam Nemet, Tim Northover, etc., it seems that<span> </span><br>
testing MC encodings in the same suite as the basic codegen isn't the<span> </span><br>
right approach. Instead, we're going to want dedicated MC tests for<span> </span><br>
the encodings. These encodings are starting to get in my way so I<span> </span><br>
wanted to cut them out early. The total set of instructions that<span> </span><br>
should have encoding tests added is:<br>
<br>
vpaddd<br>
vsqrtss<br>
vsqrtsd<br>
vmovlhps<br>
vmovhlps<br>
valignq<br>
vbroadcastss<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8.5pt"><br>
So the plan is that I will put together a script that will move all the encoding tests from CodeGen to MC.<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8.5pt"><br>
Not that simple :(((. I am pretty confused at this point. Elena, can you please help with this?<br>
<br>
There are some cases of matching encoding here that only checks if we generate the EVEX prefix (0x62). I guess for AVX512 scalar ops we want to generate the AVX512 encoded version even for default rounding rather than the AVX version. Correct?<br>
<br>
Since the mnemonic and operands are the same we need some way to steer this to AVX512. This seems to be working in codegen (perhaps by chance) but not in the assembler. E.g.<br>
<br>
vsqrtsd %xmm0, %xmm0, %xmm0<br>
<br>
is assembled without EVEX with -mcpu=knl. Is this supposed to work? The change that added the encoding checks seems to suggest that it should:
<a href="http://reviews.llvm.org/rL197041" target="_blank">http://reviews.llvm.org/rL197041</a><br>
<br>
So for now, I will probably only move encoding checks that don't fall under this category until we work out the right approach.<br>
<br>
Adam<br>
<br>
<br>
<br>
<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8.5pt">The concern was that we're not testing the assembler when we check the encoding only through CodeGen.<br>
<br>
Adam<br>
<br>
<br>
<br>
<u></u><u></u></span></p>
<p class="MsoNormal"><span style="font-size:8.5pt"><br>
Not too many parts of these tests were even using this. =]<br>
<br>
Modified:<br>
llvm/trunk/test/CodeGen/X86/avx512-arith.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll<br>
llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-arith.ll<br>
URL:<span> </span><br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx51" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx51</a><br>
2-arith.ll?rev=218932&r1=218931&r2=218932&view=diff<br>
=====================================================================<br>
=========<br>
--- llvm/trunk/test/CodeGen/X86/avx512-arith.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-arith.ll Thu Oct 2 19:36:29<span> </span><br>
+++ 2014<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl<span> </span><br>
--show-mc-encoding| FileCheck %s<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck<span> </span><br>
+%s<br>
<br>
; CHECK-LABEL: addpd512<br>
; CHECK: vaddpd<br>
@@ -223,7 +223,7 @@ define <16 x i32> @vpaddd_broadcast_test }<br>
<br>
; CHECK-LABEL: vpaddd_mask_test<br>
-; CHECK: vpaddd {{%zmm[0-9]{1,2}, %zmm[0-9]{1,2}, %zmm[0-9]{1,2}<span> </span><br>
{%k[1-7]} }}<br>
+; CHECK: vpaddd {{%zmm[0-9], %zmm[0-9], %zmm[0-9] {%k[1-7]}}}<br>
; CHECK: ret<br>
define <16 x i32> @vpaddd_mask_test(<16 x i32> %i, <16 x i32> %j, <16<span> </span><br>
x i32> %mask1) nounwind readnone { %mask = icmp ne <16 x i32><span> </span><br>
%mask1, zeroinitializer @@ -233,7 +233,7 @@ define <16 x i32><span> </span><br>
@vpaddd_mask_test(<16 }<br>
<br>
; CHECK-LABEL: vpaddd_maskz_test<br>
-; CHECK: vpaddd {{%zmm[0-9]{1,2}, %zmm[0-9]{1,2}, %zmm[0-9]{1,2}<span> </span><br>
{%k[1-7]} {z} }}<br>
+; CHECK: vpaddd {{%zmm[0-9], %zmm[0-9], %zmm[0-9] {%k[1-7]} {z}}}<br>
; CHECK: ret<br>
define <16 x i32> @vpaddd_maskz_test(<16 x i32> %i, <16 x i32> %j,<span> </span><br>
<16 x i32> %mask1) nounwind readnone { %mask = icmp ne <16 x i32><span> </span><br>
%mask1, zeroinitializer @@ -243,7 +243,7 @@ define <16 x i32><span> </span><br>
@vpaddd_maskz_test(<16 }<br>
<br>
; CHECK-LABEL: vpaddd_mask_fold_test<br>
-; CHECK: vpaddd (%rdi), {{%zmm[0-9]{1,2}, %zmm[0-9]{1,2} {%k[1-7]}<span> </span><br>
}}<br>
+; CHECK: vpaddd (%rdi), {{%zmm[0-9], %zmm[0-9] {%k[1-7]}}}<br>
; CHECK: ret<br>
define <16 x i32> @vpaddd_mask_fold_test(<16 x i32> %i, <16 x i32>*<span> </span><br>
%j.ptr, <16 x i32> %mask1) nounwind readnone { %mask = icmp ne <16 x<span> </span><br>
i32> %mask1, zeroinitializer @@ -254,7 +254,7 @@ define <16 x i32><span> </span><br>
@vpaddd_mask_fold_test }<br>
<br>
; CHECK-LABEL: vpaddd_mask_broadcast_test -; CHECK: vpaddd<span> </span><br>
LCP{{.*}}(%rip){1to16}, {{%zmm[0-9]{1,2}, %zmm[0-9]{1,2} {%k[1-7]} }}<br>
+; CHECK: vpaddd LCP{{.*}}(%rip){1to16}, {{%zmm[0-9], %zmm[0-9]<span> </span><br>
+{%k[1-7]}}}<br>
; CHECK: ret<br>
define <16 x i32> @vpaddd_mask_broadcast_test(<16 x i32> %i, <16 x<span> </span><br>
i32> %mask1) nounwind readnone { %mask = icmp ne <16 x i32> %mask1,<span> </span><br>
zeroinitializer @@ -264,7 +264,7 @@ define <16 x i32><span> </span><br>
@vpaddd_mask_broadcast }<br>
<br>
; CHECK-LABEL: vpaddd_maskz_fold_test -; CHECK: vpaddd (%rdi),<span> </span><br>
{{%zmm[0-9]{1,2}, %zmm[0-9]{1,2} {%k[1-7]}}} {z}<br>
+; CHECK: vpaddd (%rdi), {{%zmm[0-9], %zmm[0-9] {%k[1-7]}}} {z}<br>
; CHECK: ret<br>
define <16 x i32> @vpaddd_maskz_fold_test(<16 x i32> %i, <16 x i32>*<span> </span><br>
%j.ptr, <16 x i32> %mask1) nounwind readnone { %mask = icmp ne <16 x<span> </span><br>
i32> %mask1, zeroinitializer @@ -275,7 +275,7 @@ define <16 x i32><span> </span><br>
@vpaddd_maskz_fold_tes }<br>
<br>
; CHECK-LABEL: vpaddd_maskz_broadcast_test -; CHECK: vpaddd<span> </span><br>
LCP{{.*}}(%rip){1to16}, {{%zmm[0-9]{1,2}, %zmm[0-9]{1,2} {%k[1-7]}}}<span> </span><br>
{z}<br>
+; CHECK: vpaddd LCP{{.*}}(%rip){1to16}, {{%zmm[0-9], %zmm[0-9]<span> </span><br>
+{%k[1-7]}}} {z}<br>
; CHECK: ret<br>
define <16 x i32> @vpaddd_maskz_broadcast_test(<16 x i32> %i, <16 x<span> </span><br>
i32> %mask1) nounwind readnone { %mask = icmp ne <16 x i32> %mask1,<span> </span><br>
zeroinitializer @@ -309,7 +309,7 @@ define <16 x i32><span> </span><br>
@vpmulld_test(<16 x i3 }<br>
<br>
; CHECK-LABEL: sqrtA<br>
-; CHECK: vsqrtss {{.*}} encoding: [0x62<br>
+; CHECK: vsqrtss {{.*}}<br>
; CHECK: ret<br>
declare float @sqrtf(float) readnone<br>
define float @sqrtA(float %a) nounwind uwtable readnone ssp { @@<span> </span><br>
-319,7 +319,7 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: sqrtB<br>
-; CHECK: vsqrtsd {{.*}}## encoding: [0x62<br>
+; CHECK: vsqrtsd {{.*}}<br>
; CHECK: ret<br>
declare double @sqrt(double) readnone define double @sqrtB(double %a)<span> </span><br>
nounwind uwtable readnone ssp { @@ -329,7 +329,7 @@ entry:<br>
}<br>
<br>
; CHECK-LABEL: sqrtC<br>
-; CHECK: vsqrtss {{.*}}## encoding: [0x62<br>
+; CHECK: vsqrtss {{.*}}<br>
; CHECK: ret<br>
declare float @llvm.sqrt.f32(float)<br>
define float @sqrtC(float %a) nounwind {<br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll<br>
URL:<span> </span><br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx51" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx51</a><br>
2-shuffle.ll?rev=218932&r1=218931&r2=218932&view=diff<br>
=====================================================================<br>
=========<br>
--- llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-shuffle.ll Thu Oct 2 19:36:29<span> </span><br>
+++ 2014<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl<span> </span><br>
--show-mc-encoding| FileCheck %s<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck<span> </span><br>
+%s<br>
; CHECK: LCP<br>
; CHECK: .long 2<br>
; CHECK: .long 5<br>
@@ -169,7 +169,7 @@ define <16 x i32> @test11(<16 x i32> %a, }<br>
<br>
; CHECK-LABEL: test12<br>
-; CHECK: vmovlhps {{.*}}## encoding: [0x62<br>
+; CHECK: vmovlhps {{.*}}<br>
; CHECK: ret<br>
define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) nounwind { %c =<span> </span><br>
shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 1,<span> </span><br>
i32 4, i32 5> @@ -226,7 +226,7 @@ define <8 x double> @test16(<8 x<span> </span><br>
double> }<br>
<br>
; CHECK-LABEL: test16k<br>
-; CHECK: valignq $2, %zmm0, %zmm1, %zmm2 {%k1} #<br>
+; CHECK: valignq $2, %zmm0, %zmm1, %zmm2 {%k1}<br>
define <8 x i64> @test16k(<8 x i64> %a, <8 x i64> %b, <8 x i64> %src,<span> </span><br>
i8 %mask) nounwind { %c = shufflevector <8 x i64> %a, <8 x i64> %b,<span> </span><br>
<8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> <br>
%m = bitcast i8 %mask to <8 x i1> @@ -235,7 +235,7 @@ define <8 x<span> </span><br>
i64> @test16k(<8 x i64> %a, }<br>
<br>
; CHECK-LABEL: test16kz<br>
-; CHECK: valignq $2, %zmm0, %zmm1, %zmm0 {%k1} {z} ## encoding:<span> </span><br>
[0x62,0xf3,0xf5,0xc9,0x03,0xc0,0x02]<br>
+; CHECK: valignq $2, %zmm0, %zmm1, %zmm0 {%k1} {z}<br>
define <8 x i64> @test16kz(<8 x i64> %a, <8 x i64> %b, i8 %mask)<span> </span><br>
nounwind { %c = shufflevector <8 x i64> %a, <8 x i64> %b, <8 x i32><span> </span><br>
<i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9> %m =<span> </span><br>
bitcast i8 %mask to <8 x i1> @@ -296,7 +296,7 @@ define <16 x float><span> </span><br>
@test21(<16 x float> }<br>
<br>
; CHECK-LABEL: test22<br>
-; CHECK: vmovhlps {{.*}}## encoding: [0x62<br>
+; CHECK: vmovhlps {{.*}}<br>
; CHECK: ret<br>
define <4 x i32> @test22(<4 x i32> %a, <4 x i32> %b) nounwind { %c =<span> </span><br>
shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 3,<span> </span><br>
i32 6, i32 7><br>
<br>
Modified: llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll<br>
URL:<span> </span><br>
<a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx51" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx51</a><br>
2-vbroadcast.ll?rev=218932&r1=218931&r2=218932&view=diff<br>
=====================================================================<br>
=========<br>
--- llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll (original)<br>
+++ llvm/trunk/test/CodeGen/X86/avx512-vbroadcast.ll Thu Oct 2<span> </span><br>
+++ 19:36:29 2014<br>
@@ -1,4 +1,4 @@<br>
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl<span> </span><br>
--show-mc-encoding| FileCheck %s<br>
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck<span> </span><br>
+%s<br>
<br>
;CHECK-LABEL: _inreg16xi32:<br>
;CHECK: vpbroadcastd {{.*}}, %zmm<br>
@@ -45,7 +45,7 @@ define <16 x i32> @_xmm16xi32(<16 x i3<br>
}<br>
<br>
;CHECK-LABEL: _xmm16xfloat<br>
-;CHECK: vbroadcastss {{.*}}## encoding: [0x62<br>
+;CHECK: vbroadcastss {{.*}}<br>
;CHECK: ret<br>
define <16 x float> @_xmm16xfloat(<16 x float> %a) {<br>
%b = shufflevector <16 x float> %a, <16 x float> undef, <16 x i32><span> </span><br>
zeroinitializer<br>
<br>
<br>
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