<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class="">Hi Serge,<div class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Sep 30, 2014, at 12:04 PM, Serge Pavlov <<a href="mailto:sepavloff@gmail.com" class="">sepavloff@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><div dir="ltr" class="">Hi Pete, Quentin,<div class=""><br class=""></div><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word" class=""><div class="">In the specific example here for the constant 0, i’d have expected to see xor used to create the 0. Any idea why that didn’t happen? That would improve the code size which Quentin mentioned is a plus for this.</div></div></blockquote><div class=""><br class=""></div><div class="">This pass can be modified to load zero in this way. Probably it is better to improve instruction selector properly as loading zero in such way might be useful not only for caching immediates in register.</div><div class=""><br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word" class=""><div class=""><br class=""></div><div class="">Also, i’ve sometimes seen neighboring 0’s being written of different sizes. Would it be possible (perhaps in a future patch), to turn</div><div class=""><br class=""></div><div class="">movq 0, 0x0(%rsi)</div>movl 0, 0x8(%rsi)<div class=""><br class=""></div><div class="">in to</div><div class=""><br class=""></div><div class="">xor %rax, %rax</div><div class="">movq %rax, 0x0(%rsi)</div><div class="">movl %eax, 0x8(%rsi)</div><div class=""><br class=""></div></div></blockquote><div class=""><br class=""></div><div class="">Yes, subregisters are taken into account. For instance instructions:</div><div class=""><br class=""></div><div class="">movw 0x5555, 0x0(%rsi)</div><div class="">movw 0x5555, 0x4(%rsi)</div><div class=""><div class="">movb 0x55, 0x8(%rsi)</div></div><div class=""><br class=""></div><div class="">are transformed into:</div><div class=""><br class=""></div><div class="">movw 0x5555, %ax</div><div class=""><div class="">movw %ax, 0x0(%rsi)</div><div class="">movw %ax, 0x4(%rsi)</div><div class="">movb %al, 0x8(%rsi)</div></div><div class=""><br class=""></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word" class=""><div class=""><div class="h5"><div class=""><div class=""><div class=""><div class=""><blockquote type="cite" class=""><div class=""><span style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;float:none;display:inline!important" class="">The constant hoisting pass does this kind of things. Should we try to teach it to handle this kind of cases?</span></div></blockquote></div></div></div></div></div></div></div></blockquote><div class="">That would be interesting. However this pass is x86 specific and can use processor features (subregister structure, loading 64-bit value with 32-bit move). Can theses features be used by constant hoisting? </div></div></div></div></div></blockquote><div><br class=""></div><div>Maybe. This pass has a bunch of target hooks if I remember correctly. Juergen would know better :).</div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div class="gmail_extra"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left-width:1px;border-left-color:rgb(204,204,204);border-left-style:solid;padding-left:1ex"><div style="word-wrap:break-word" class=""><div class=""><div class="h5"><div class=""><div class=""><div class=""><div class=""><blockquote type="cite" class=""><div class=""><br style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px" class=""><br style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px" class=""><span style="font-family:Helvetica;font-size:12px;font-style:normal;font-variant:normal;font-weight:normal;letter-spacing:normal;line-height:normal;text-align:start;text-indent:0px;text-transform:none;white-space:normal;word-spacing:0px;float:none;display:inline!important" class="">Moreover, this may be beneficial for code size, but I guess it is generally not beneficial for performances. Therefore, I believe this should be done for functions with the Os or Oz attributes only.</span></div></blockquote></div></div></div></div></div></div></div></blockquote><div class="">Just curious, why? Moves from register must be faster than move from memory.</div></div></div></div></div></blockquote><div><br class=""></div><div>Yes, but those are moves from immediate, which does not require memory at all.</div><div>My performance concerns are:</div><div>- Register pressure, like Rafael mentioned.</div><div>- Additional scheduling dependencies.</div><div><br class=""></div><div>Going back to your example:</div><div>This yields two independent chain of computation that can be scheduled independently. Moreover, you need just one register to realize this sequence.</div><div> mov $0, 0x4(%esi)<br class=""> mov $0, 0x8(%esi)<br class=""><br class="">The two sequences of computations have now to wait for the first mov immediate. Moreover, this sequence requires 2 registers.<br class=""> mov $0, %eax<br class=""> mov %eax, 0x4(%esi)<br class=""> mov %eax, 0x8(%esi)</div><div><br class=""></div><br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div class="gmail_extra"><div class="gmail_quote"><div class=""> Both gcc and icc use moves from register when compiling with optimization. </div></div></div></div></div></blockquote><div><br class=""></div><div>Sure. What I am saying is that generally speaking, trading an immediate to register copy against a register to register copy does not sound like beneficial to me. </div><div><br class=""></div><div>Except from code size improvements, what kind of improvements are you seeing?</div><div>Also, how big are those improvements?</div><div><br class=""></div><div>Thanks,</div>-Quentin<br class=""><blockquote type="cite" class=""><div class=""><div dir="ltr" class=""><div class="gmail_extra"><div class="gmail_quote"><div class=""><br class=""></div><div class="">--Serge </div></div></div></div>
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