<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;" class=""><br class=""><div><blockquote type="cite" class=""><div class="">On Sep 30, 2014, at 3:36 PM, Hal Finkel <<a href="mailto:hfinkel@anl.gov" class="">hfinkel@anl.gov</a>> wrote:</div><br class="Apple-interchange-newline"><div class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Andy,</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Can you take a quick look at this? I think that what Sanjin says makes sense; do you agree? Is there a way to add an assert in case something goes wrong?</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Sanjin, if nothing else, please add a comment in the code to this effect.</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""></div></blockquote><div><br class=""></div><div>Thanks Hal, sometimes I need to be copied on commits to notice them.</div><div><br class=""></div><div>Is BasicAA unable to pick up on this because it can't answer queries about aliasing within a single loop iteration? It seems like long term that may be something to revisit. There's no fundamental reason we need to decode machine instructions to figure this case out.</div><div><br class=""></div><div>But given that's a pretty major design issue, I'm OK with checking disjoint access at the MI level.</div><div><br class=""></div><div>As you said, areMemAccessesTriviallyDisjoint is lying if it reports true for physical registers. I don't see the harm in explicitly checking the register type. Otherwise, there does need to be a very bold comment in the function header.</div><div class=""><br class=""></div><div class="">-Andy</div><div class=""><br class=""></div><blockquote type="cite" class=""><div class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Thanks again,</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Hal</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">----- Original Message -----</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><blockquote type="cite" style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class="">From: "Sanjin Sijaric" <<a href="mailto:ssijaric@codeaurora.org" class="">ssijaric@codeaurora.org</a>><br class="">To: <a href="mailto:mcrosier@codeaurora.org" class="">mcrosier@codeaurora.org</a><br class="">Cc: "Hal Finkel" <<a href="mailto:hfinkel@anl.gov" class="">hfinkel@anl.gov</a>>, <a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a>, "Matt Arsenault" <<a href="mailto:arsenm2@gmail.com" class="">arsenm2@gmail.com</a>><br class="">Sent: Monday, September 29, 2014 5:22:47 PM<br class="">Subject: RE: [llvm] r217371 - [AArch64] Improve AA to remove unneeded edges in the<span class="Apple-tab-span" style="white-space: pre;"> </span>AA MI scheduling graph.<br class=""><br class="">Hi Hal,<br class=""><br class="">The original purpose of the function was for discarding trivial chain<br class="">edges<br class="">when constructing the dependence graph for scheduling. If BaseReg is<br class="">a<br class="">physical register that gets modified, then we may have something<br class="">like:<br class=""><br class="">LD R1 = A(BaseReg, Offset1) (1)<br class=""><br class="">BaseReg = .... (2)<br class=""><br class="">ST R2, B(BaseReg, Offset2) (3)<br class=""><br class="">Given the inputs (1) and (3) to areMemAccessesTriviallyDisjoint, it<br class="">may be<br class="">determined that there is no need for an edge between them. There<br class="">will be no<br class="">dependence between (1) and (3), but there will be dependences between<br class="">"(1)<br class="">and (2)" and "(2) and (3)". I think this should be enough to prevent<br class="">any<br class="">bad scheduling from happening.<br class=""><br class="">Thanks,<br class="">Sanjin<br class=""><br class="">-----Original Message-----<br class="">From: Chad Rosier [<a href="mailto:mcrosier@codeaurora.org" class="">mailto:mcrosier@codeaurora.org</a>]<br class="">Sent: Monday, September 29, 2014 6:47 AM<br class="">To: <a href="mailto:ssijaric@codeaurora.org" class="">ssijaric@codeaurora.org</a><br class="">Cc: Hal Finkel; Chad Rosier; <a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a>; Matt Arsenault<br class="">Subject: Re: [llvm] r217371 - [AArch64] Improve AA to remove unneeded<br class="">edges<br class="">in the AA MI scheduling graph.<br class=""><br class="">+Sanjin<br class=""><br class="">Adding Sanjin since this is his work.<br class=""><br class="">Chad<br class=""><br class=""><blockquote type="cite" class="">----- Original Message -----<br class=""><blockquote type="cite" class="">From: "Chad Rosier" <<a href="mailto:mcrosier@codeaurora.org" class="">mcrosier@codeaurora.org</a>><br class="">To: <a href="mailto:llvm-commits@cs.uiuc.edu" class="">llvm-commits@cs.uiuc.edu</a><br class="">Sent: Monday, September 8, 2014 9:43:48 AM<br class="">Subject: [llvm] r217371 - [AArch64] Improve AA to remove unneeded<br class="">edges<br class="">in the<span class="Apple-tab-span" style="white-space: pre;"> </span>AA MI scheduling graph.<br class=""><br class="">Author: mcrosier<br class="">Date: Mon Sep 8 09:43:48 2014<br class="">New Revision: 217371<br class=""><br class="">URL: <a href="http://llvm.org/viewvc/llvm-project?rev=217371&view=rev" class="">http://llvm.org/viewvc/llvm-project?rev=217371&view=rev</a><br class="">Log:<br class="">[AArch64] Improve AA to remove unneeded edges in the AA MI<br class="">scheduling<br class="">graph.<br class=""><br class="">Patch by Sanjin Sijaric <<a href="mailto:ssijaric@codeaurora.org" class="">ssijaric@codeaurora.org</a>>!<br class="">Phabricator Review: <a href="http://reviews.llvm.org/D5103" class="">http://reviews.llvm.org/D5103</a><br class=""><br class="">Added:<br class=""> llvm/trunk/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll<br class="">Modified:<br class=""> llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br class=""> llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br class=""> llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h<br class=""><br class="">Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h<br class="">URL:<br class=""><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Ta" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Ta</a><br class="">rgetInstrInfo.h?rev=217371&r1=217370&r2=217371&view=diff<br class="">=====================================================================<br class="">=========<br class="">--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)<br class="">+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Mon Sep 8<br class="">09:43:48 2014<br class="">@@ -1192,6 +1192,20 @@ public:<br class=""> return nullptr;<br class=""> }<br class=""><br class="">+ // areMemAccessesTriviallyDisjoint - Sometimes, it is possible<br class="">for<br class="">the target<br class="">+ // to tell, even without aliasing information, that two MIs<br class="">access<br class="">different<br class="">+ // memory addresses. This function returns true if two MIs<br class="">access<br class="">different<br class="">+ // memory addresses, and false otherwise.<br class="">+ virtual bool<br class="">+ areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr<br class="">*MIb,<br class="">+ AliasAnalysis *AA = nullptr)<br class="">const<br class="">{<br class="">+ assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&<br class="">+ "MIa must load from or modify a memory location");<br class="">+ assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&<br class="">+ "MIb must load from or modify a memory location");<br class="">+ return false;<br class="">+ }<br class="">+<br class="">private:<br class=""> int CallFrameSetupOpcode, CallFrameDestroyOpcode; };<br class=""><br class="">Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp<br class="">URL:<br class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDA<br class="">GInstrs.cpp?rev=217371&r1=217370&r2=217371&view=diff<br class="">=====================================================================<br class="">=========<br class="">--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)<br class="">+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Mon Sep 8<br class="">09:43:48<br class="">2014<br class="">@@ -511,9 +511,18 @@ static inline bool isUnsafeMemoryObject(<br class="">static<br class="">bool MIsNeedChainEdge(AliasAnalysis *AA, const MachineFrameInfo<br class="">*MFI,<br class=""> MachineInstr *MIa,<br class=""> MachineInstr *MIb) {<br class="">+ const MachineFunction *MF = MIa->getParent()->getParent();<br class="">const<br class="">+ TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();<br class="">+<br class=""> // Cover a trivial case - no edge is need to itself.<br class=""> if (MIa == MIb)<br class=""> return false;<br class="">+<br class="">+ // Let the target decide if memory accesses cannot possibly<br class="">overlap.<br class="">+ if ((MIa->mayLoad() || MIa->mayStore()) &&<br class="">+ (MIb->mayLoad() || MIb->mayStore()))<br class="">+ if (TII->areMemAccessesTriviallyDisjoint(MIa, MIb, AA))<br class="">+ return false;<br class=""><br class=""> // FIXME: Need to handle multiple memory operands to support<br class=""> all<br class=""> targets.<br class=""> if (!MIa->hasOneMemOperand() || !MIb->hasOneMemOperand())<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp<br class="">URL:<br class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AAr<br class="">ch64InstrInfo.cpp?rev=217371&r1=217370&r2=217371&view=diff<br class="">=====================================================================<br class="">=========<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Mon Sep 8<br class="">09:43:48 2014<br class="">@@ -607,6 +607,42 @@ bool AArch64InstrInfo::isCoalescableExtI<br class=""> }<br class="">}<br class=""><br class="">+bool<br class="">+AArch64InstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr<br class="">*MIa,<br class="">+ MachineInstr<br class="">*MIb,<br class="">+ AliasAnalysis<br class="">*AA)<br class="">const {<br class="">+ const TargetRegisterInfo *TRI = &getRegisterInfo(); unsigned<br class="">+ BaseRegA = 0, BaseRegB = 0; int OffsetA = 0, OffsetB = 0; int<br class="">+ WidthA = 0, WidthB = 0;<br class="">+<br class="">+ assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&<br class="">+ "MIa must be a store or a load"); assert(MIb &&<br class="">+ (MIb->mayLoad() || MIb->mayStore()) &&<br class="">+ "MIb must be a store or a load");<br class="">+<br class="">+ if (MIa->hasUnmodeledSideEffects() ||<br class="">MIb->hasUnmodeledSideEffects() ||<br class="">+ MIa->hasOrderedMemoryRef() || MIb->hasOrderedMemoryRef())<br class="">+ return false;<br class="">+<br class="">+ // Retrieve the base register, offset from the base register<br class="">and<br class="">width. Width<br class="">+ // is the size of memory that is being loaded/stored (e.g. 1,<br class="">2,<br class="">4, 8). If<br class="">+ // base registers are identical, and the offset of a lower<br class="">memory<br class="">access +<br class="">+ // the width doesn't overlap the offset of a higher memory<br class="">access,<br class="">+ // then the memory accesses are different.<br class="">+ if (getLdStBaseRegImmOfsWidth(MIa, BaseRegA, OffsetA, WidthA,<br class="">TRI)<br class="">&&<br class="">+ getLdStBaseRegImmOfsWidth(MIb, BaseRegB, OffsetB, WidthB,<br class="">TRI)) {<br class="">+ if (BaseRegA == BaseRegB) {<br class=""></blockquote><br class="">I think that this makes sense only for SSA virtual registers, but<br class="">not<br class="">for physical ones (because the value in a physical register might<br class="">have<br class="">changed in between the two instructions). If I'm right, then you'll<br class="">want to exclude physical registers here (at least any that might be<br class="">modified during the function's execution).<br class=""><br class="">-Hal<br class=""><br class=""><blockquote type="cite" class="">+ int LowOffset = OffsetA < OffsetB ? OffsetA : OffsetB;<br class="">+ int HighOffset = OffsetA < OffsetB ? OffsetB : OffsetA;<br class="">+ int LowWidth = (LowOffset == OffsetA) ? WidthA : WidthB;<br class="">+ if (LowOffset + LowWidth <= HighOffset)<br class="">+ return true;<br class="">+ }<br class="">+ }<br class="">+ return false;<br class="">+}<br class="">+<br class="">/// analyzeCompare - For a comparison instruction, return the<br class="">source<br class="">registers /// in SrcReg and SrcReg2, and the value it compares<br class="">against in CmpValue.<br class="">/// Return true if the comparison instruction can be analyzed.<br class="">@@ -1270,6 +1306,102 @@ AArch64InstrInfo::getLdStBaseRegImmOfs(M<br class=""> };<br class="">}<br class=""><br class="">+bool AArch64InstrInfo::getLdStBaseRegImmOfsWidth(<br class="">+ MachineInstr *LdSt, unsigned &BaseReg, int &Offset, int<br class="">&Width,<br class="">+ const TargetRegisterInfo *TRI) const {<br class="">+ // Handle only loads/stores with base register followed by<br class="">immediate offset.<br class="">+ if (LdSt->getNumOperands() != 3)<br class="">+ return false;<br class="">+ if (!LdSt->getOperand(1).isReg() ||<br class="">!LdSt->getOperand(2).isImm())<br class="">+ return false;<br class="">+<br class="">+ // Offset is calculated as the immediate operand multiplied by<br class="">the<br class="">scaling factor.<br class="">+ // Unscaled instructions have scaling factor set to 1.<br class="">+ int Scale = 0;<br class="">+ switch (LdSt->getOpcode()) {<br class="">+ default:<br class="">+ return false;<br class="">+ case AArch64::LDURQi:<br class="">+ case AArch64::STURQi:<br class="">+ Width = 16;<br class="">+ Scale = 1;<br class="">+ break;<br class="">+ case AArch64::LDURXi:<br class="">+ case AArch64::LDURDi:<br class="">+ case AArch64::STURXi:<br class="">+ case AArch64::STURDi:<br class="">+ Width = 8;<br class="">+ Scale = 1;<br class="">+ break;<br class="">+ case AArch64::LDURWi:<br class="">+ case AArch64::LDURSi:<br class="">+ case AArch64::LDURSWi:<br class="">+ case AArch64::STURWi:<br class="">+ case AArch64::STURSi:<br class="">+ Width = 4;<br class="">+ Scale = 1;<br class="">+ break;<br class="">+ case AArch64::LDURHi:<br class="">+ case AArch64::LDURHHi:<br class="">+ case AArch64::LDURSHXi:<br class="">+ case AArch64::LDURSHWi:<br class="">+ case AArch64::STURHi:<br class="">+ case AArch64::STURHHi:<br class="">+ Width = 2;<br class="">+ Scale = 1;<br class="">+ break;<br class="">+ case AArch64::LDURBi:<br class="">+ case AArch64::LDURBBi:<br class="">+ case AArch64::LDURSBXi:<br class="">+ case AArch64::LDURSBWi:<br class="">+ case AArch64::STURBi:<br class="">+ case AArch64::STURBBi:<br class="">+ Width = 1;<br class="">+ Scale = 1;<br class="">+ break;<br class="">+ case AArch64::LDRXui:<br class="">+ case AArch64::STRXui:<br class="">+ Scale = Width = 8;<br class="">+ break;<br class="">+ case AArch64::LDRWui:<br class="">+ case AArch64::STRWui:<br class="">+ Scale = Width = 4;<br class="">+ break;<br class="">+ case AArch64::LDRBui:<br class="">+ case AArch64::STRBui:<br class="">+ Scale = Width = 1;<br class="">+ break;<br class="">+ case AArch64::LDRHui:<br class="">+ case AArch64::STRHui:<br class="">+ Scale = Width = 2;<br class="">+ break;<br class="">+ case AArch64::LDRSui:<br class="">+ case AArch64::STRSui:<br class="">+ Scale = Width = 4;<br class="">+ break;<br class="">+ case AArch64::LDRDui:<br class="">+ case AArch64::STRDui:<br class="">+ Scale = Width = 8;<br class="">+ break;<br class="">+ case AArch64::LDRQui:<br class="">+ case AArch64::STRQui:<br class="">+ Scale = Width = 16;<br class="">+ break;<br class="">+ case AArch64::LDRBBui:<br class="">+ case AArch64::STRBBui:<br class="">+ Scale = Width = 1;<br class="">+ break;<br class="">+ case AArch64::LDRHHui:<br class="">+ case AArch64::STRHHui:<br class="">+ Scale = Width = 2;<br class="">+ break;<br class="">+ };<br class="">+<br class="">+ BaseReg = LdSt->getOperand(1).getReg();<br class="">+ Offset = LdSt->getOperand(2).getImm() * Scale;<br class="">+ return true;<br class="">+}<br class="">+<br class="">/// Detect opportunities for ldp/stp formation.<br class="">///<br class="">/// Only called for LdSt for which getLdStBaseRegImmOfs returns<br class="">true.<br class=""><br class="">Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h<br class="">URL:<br class=""><a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AAr" class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AAr</a><br class="">ch64InstrInfo.h?rev=217371&r1=217370&r2=217371&view=diff<br class="">=====================================================================<br class="">=========<br class="">--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h (original)<br class="">+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h Mon Sep 8<br class="">09:43:48 2014<br class="">@@ -52,6 +52,10 @@ public:<br class=""> bool isCoalescableExtInstr(const MachineInstr &MI, unsigned<br class=""> &SrcReg,<br class=""> unsigned &DstReg, unsigned &SubIdx)<br class=""> const override;<br class=""><br class="">+ bool<br class="">+ areMemAccessesTriviallyDisjoint(MachineInstr *MIa, MachineInstr<br class="">*MIb,<br class="">+ AliasAnalysis *AA = nullptr)<br class="">const<br class="">override;<br class="">+<br class=""> unsigned isLoadFromStackSlot(const MachineInstr *MI,<br class=""> int &FrameIndex) const override;<br class=""> unsigned isStoreToStackSlot(const MachineInstr *MI, @@ -90,6<br class="">+94,10 @@ public:<br class=""> unsigned &Offset,<br class=""> const TargetRegisterInfo *TRI) const<br class=""> override;<br class=""><br class="">+ bool getLdStBaseRegImmOfsWidth(MachineInstr *LdSt, unsigned<br class="">&BaseReg,<br class="">+ int &Offset, int &Width,<br class="">+ const TargetRegisterInfo *TRI)<br class="">const;<br class="">+<br class=""> bool enableClusterLoads() const override { return true; }<br class=""><br class=""> bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr<br class=""> *SecondLdSt,<br class=""><br class="">Added:<br class="">llvm/trunk/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll<br class="">URL:<br class="">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/a<br class="">rm64-triv-disjoint-mem-access.ll?rev=217371&view=auto<br class="">=====================================================================<br class="">=========<br class="">---<br class="">llvm/trunk/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll<br class="">(added)<br class="">+++<br class="">llvm/trunk/test/CodeGen/AArch64/arm64-triv-disjoint-mem-access.ll<br class="">Mon Sep 8 09:43:48 2014<br class="">@@ -0,0 +1,31 @@<br class="">+; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53<br class="">-enable-aa-sched-mi | FileCheck %s<br class="">+; Check that the scheduler moves the load from a[1] past the<br class="">store<br class="">into a[2].<br class="">+@a = common global i32* null, align 8 @m = common global i32 0,<br class="">+align 4<br class="">+<br class="">+; Function Attrs: nounwind<br class="">+define i32 @func(i32 %i, i32 %j, i32 %k) #0 {<br class="">+entry:<br class="">+; CHECK: ldr {{w[0-9]+}}, [x[[REG:[0-9]+]], #4] ; CHECK: str<br class="">+{{w[0-9]+}}, [x[[REG]], #8]<br class="">+ %0 = load i32** @a, align 8, !tbaa !1<br class="">+ %arrayidx = getelementptr inbounds i32* %0, i64 2<br class="">+ store i32 %i, i32* %arrayidx, align 4, !tbaa !5<br class="">+ %arrayidx1 = getelementptr inbounds i32* %0, i64 1<br class="">+ %1 = load i32* %arrayidx1, align 4, !tbaa !5<br class="">+ %add = add nsw i32 %k, %i<br class="">+ store i32 %add, i32* @m, align 4, !tbaa !5<br class="">+ ret i32 %1<br class="">+}<br class="">+<br class="">+attributes #0 = { nounwind "less-precise-fpmad"="false"<br class="">"no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"<br class="">"no-infs-fp-math"="true" "no-nans-fp-math"="true"<br class="">"stack-protector-buffer-size"="8" "unsafe-fp-math"="true"<br class="">"use-soft-float"="false" }<br class="">+<br class="">+!llvm.ident = !{!0}<br class="">+<br class="">+!0 = metadata !{metadata !"clang version 3.6.0 "}<br class="">+!1 = metadata !{metadata !2, metadata !2, i64 0}<br class="">+!2 = metadata !{metadata !"any pointer", metadata !3, i64 0}<br class="">+!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}<br class="">+!4 = metadata !{metadata !"Simple C/C++ TBAA"}<br class="">+!5 = metadata !{metadata !6, metadata !6, i64 0}<br class="">+!6 = metadata !{metadata !"int", metadata !3, i64 0}<br class=""><br class=""><br class="">_______________________________________________<br class="">llvm-commits mailing list<br class="">llvm-commits@cs.uiuc.edu<br class="">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br class=""><br class=""></blockquote><br class="">--<br class="">Hal Finkel<br class="">Assistant Computational Scientist<br class="">Leadership Computing Facility<br class="">Argonne National Laboratory<br class=""><br class=""></blockquote><br class=""><br class=""><br class=""><br class=""></blockquote><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">--<span class="Apple-converted-space"> </span></span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Hal Finkel</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Assistant Computational Scientist</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Leadership Computing Facility</span><br style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px;" class=""><span style="font-family: Helvetica; font-size: 12px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; orphans: auto; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: auto; word-spacing: 0px; -webkit-text-stroke-width: 0px; float: none; display: inline !important;" class="">Argonne National Laboratory</span></div></blockquote></div><br class=""></body></html>