diff --git a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
index df1aa1a..e7e0550 100644
--- a/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
+++ b/llvm/lib/Target/MSP430/MCTargetDesc/MSP430MCAsmInfo.cpp
@@ -24,4 +24,7 @@ MSP430MCAsmInfo::MSP430MCAsmInfo(StringRef TT) {
 
   AlignmentIsInBytes = false;
   UsesELFSectionDirectiveForBSS = true;
+
+  SupportsDebugInformation = true;
+  ExceptionsType = ExceptionHandling::DwarfCFI;
 }
diff --git a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td
index b5a6ed0..03e02ec 100644
--- a/llvm/lib/Target/MSP430/MSP430RegisterInfo.td
+++ b/llvm/lib/Target/MSP430/MSP430RegisterInfo.td
@@ -26,42 +26,42 @@ class MSP430RegWithSubregs<bits<4> num, string n, list<Register> subregs>
 //  Registers
 //===----------------------------------------------------------------------===//
 
-def PCB  : MSP430Reg<0,  "r0">;
-def SPB  : MSP430Reg<1,  "r1">;
-def SRB  : MSP430Reg<2,  "r2">;
-def CGB  : MSP430Reg<3,  "r3">;
-def FPB  : MSP430Reg<4,  "r4">;
-def R5B  : MSP430Reg<5,  "r5">;
-def R6B  : MSP430Reg<6,  "r6">;
-def R7B  : MSP430Reg<7,  "r7">;
-def R8B  : MSP430Reg<8,  "r8">;
-def R9B  : MSP430Reg<9,  "r9">;
-def R10B : MSP430Reg<10, "r10">;
-def R11B : MSP430Reg<11, "r11">;
-def R12B : MSP430Reg<12, "r12">;
-def R13B : MSP430Reg<13, "r13">;
-def R14B : MSP430Reg<14, "r14">;
-def R15B : MSP430Reg<15, "r15">;
+def PCB  : MSP430Reg< 0,  "r0">, DwarfRegNum<[16]>;
+def SPB  : MSP430Reg< 1,  "r1">, DwarfRegNum<[17]>;
+def SRB  : MSP430Reg< 2,  "r2">, DwarfRegNum<[18]>;
+def CGB  : MSP430Reg< 3,  "r3">, DwarfRegNum<[19]>;
+def FPB  : MSP430Reg< 4,  "r4">, DwarfRegNum<[20]>;
+def R5B  : MSP430Reg< 5,  "r5">, DwarfRegNum<[21]>;
+def R6B  : MSP430Reg< 6,  "r6">, DwarfRegNum<[22]>;
+def R7B  : MSP430Reg< 7,  "r7">, DwarfRegNum<[23]>;
+def R8B  : MSP430Reg< 8,  "r8">, DwarfRegNum<[24]>;
+def R9B  : MSP430Reg< 9,  "r9">, DwarfRegNum<[25]>;
+def R10B : MSP430Reg<10, "r10">, DwarfRegNum<[26]>;
+def R11B : MSP430Reg<11, "r11">, DwarfRegNum<[27]>;
+def R12B : MSP430Reg<12, "r12">, DwarfRegNum<[28]>;
+def R13B : MSP430Reg<13, "r13">, DwarfRegNum<[29]>;
+def R14B : MSP430Reg<14, "r14">, DwarfRegNum<[30]>;
+def R15B : MSP430Reg<15, "r15">, DwarfRegNum<[31]>;
 
 def subreg_8bit : SubRegIndex<8> { let Namespace = "MSP430"; }
 
 let SubRegIndices = [subreg_8bit] in {
-def PC  : MSP430RegWithSubregs<0,  "r0",  [PCB]>;
-def SP  : MSP430RegWithSubregs<1,  "r1",  [SPB]>;
-def SR  : MSP430RegWithSubregs<2,  "r2",  [SRB]>;
-def CG  : MSP430RegWithSubregs<3,  "r3",  [CGB]>;
-def FP  : MSP430RegWithSubregs<4,  "r4",  [FPB]>;
-def R5  : MSP430RegWithSubregs<5,  "r5",  [R5B]>;
-def R6  : MSP430RegWithSubregs<6,  "r6",  [R6B]>;
-def R7  : MSP430RegWithSubregs<7,  "r7",  [R7B]>;
-def R8  : MSP430RegWithSubregs<8,  "r8",  [R8B]>;
-def R9  : MSP430RegWithSubregs<9,  "r9",  [R9B]>;
-def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>;
-def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>;
-def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>;
-def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>;
-def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>;
-def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>;
+def PC  : MSP430RegWithSubregs< 0,  "r0",  [PCB]>, DwarfRegNum<[ 0]>;
+def SP  : MSP430RegWithSubregs< 1,  "r1",  [SPB]>, DwarfRegNum<[ 1]>;
+def SR  : MSP430RegWithSubregs< 2,  "r2",  [SRB]>, DwarfRegNum<[ 2]>;
+def CG  : MSP430RegWithSubregs< 3,  "r3",  [CGB]>, DwarfRegNum<[ 3]>;
+def FP  : MSP430RegWithSubregs< 4,  "r4",  [FPB]>, DwarfRegNum<[ 4]>;
+def R5  : MSP430RegWithSubregs< 5,  "r5",  [R5B]>, DwarfRegNum<[ 5]>;
+def R6  : MSP430RegWithSubregs< 6,  "r6",  [R6B]>, DwarfRegNum<[ 6]>;
+def R7  : MSP430RegWithSubregs< 7,  "r7",  [R7B]>, DwarfRegNum<[ 7]>;
+def R8  : MSP430RegWithSubregs< 8,  "r8",  [R8B]>, DwarfRegNum<[ 8]>;
+def R9  : MSP430RegWithSubregs< 9,  "r9",  [R9B]>, DwarfRegNum<[ 9]>;
+def R10 : MSP430RegWithSubregs<10, "r10", [R10B]>, DwarfRegNum<[10]>;
+def R11 : MSP430RegWithSubregs<11, "r11", [R11B]>, DwarfRegNum<[11]>;
+def R12 : MSP430RegWithSubregs<12, "r12", [R12B]>, DwarfRegNum<[12]>;
+def R13 : MSP430RegWithSubregs<13, "r13", [R13B]>, DwarfRegNum<[13]>;
+def R14 : MSP430RegWithSubregs<14, "r14", [R14B]>, DwarfRegNum<[14]>;
+def R15 : MSP430RegWithSubregs<15, "r15", [R15B]>, DwarfRegNum<[15]>;
 }
 
 def GR8 : RegisterClass<"MSP430", [i8], 8,