<div dir="ltr">Cool, thanks!<div><br></div><div>-eric</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Mon, Sep 15, 2014 at 12:40 PM, Juergen Ributzka <span dir="ltr"><<a href="mailto:juergen@apple.com" target="_blank">juergen@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div style="word-wrap:break-word"><div>Originally I wanted to avoid the additional redundant opcode check and source code lines, but I think I will undo this part in a future refactor commit.</div><span class="HOEnZb"><font color="#888888"><div><br></div><div>-Juergen</div></font></span><div><div class="h5"><br><div><blockquote type="cite"><div>On Sep 13, 2014, at 7:06 PM, Eric Christopher <<a href="mailto:echristo@gmail.com" target="_blank">echristo@gmail.com</a>> wrote:</div><br><div><div dir="ltr">Probably missing something, but why the extra argument on selectLogicalOp? You're just grabbing it from the instruction yes?<div><br></div><div>-eric</div></div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Sep 13, 2014 at 4:46 PM, Juergen Ributzka <span dir="ltr"><<a href="mailto:juergen@apple.com" target="_blank">juergen@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: ributzka<br>
Date: Sat Sep 13 18:46:28 2014<br>
New Revision: 217732<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=217732&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=217732&view=rev</a><br>
Log:<br>
[FastISel][AArch64] Add support for non-native types for logical ops.<br>
<br>
Extend the logical ops selection to also support non-native types such as i1,<br>
i8, and i16.<br>
<br>
Fixes <a>rdar://problem/18330589</a>.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br>
llvm/trunk/test/CodeGen/AArch64/fast-isel-logic-op.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=217732&r1=217731&r2=217732&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp?rev=217732&r1=217731&r2=217732&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64FastISel.cpp Sat Sep 13 18:46:28 2014<br>
@@ -114,7 +114,7 @@ class AArch64FastISel : public FastISel<br>
private:<br>
// Selection routines.<br>
bool selectAddSub(const Instruction *I);<br>
- bool selectLogicalOp(const Instruction *I);<br>
+ bool selectLogicalOp(const Instruction *I, unsigned ISDOpcode);<br>
bool SelectLoad(const Instruction *I);<br>
bool SelectStore(const Instruction *I);<br>
bool SelectBranch(const Instruction *I);<br>
@@ -1235,9 +1235,6 @@ unsigned AArch64FastISel::emitSubs_rs(MV<br>
<br>
unsigned AArch64FastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT,<br>
const Value *LHS, const Value *RHS) {<br>
- if (RetVT != MVT::i32 && RetVT != MVT::i64)<br>
- return 0;<br>
-<br>
// Canonicalize immediates to the RHS first.<br>
if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS))<br>
std::swap(LHS, RHS);<br>
@@ -1281,8 +1278,13 @@ unsigned AArch64FastISel::emitLogicalOp(<br>
return 0;<br>
bool RHSIsKill = hasTrivialKill(RHS);<br>
<br>
- return fastEmit_rr(RetVT, RetVT, ISDOpc, LHSReg, LHSIsKill, RHSReg,<br>
- RHSIsKill);<br>
+ MVT VT = std::max(MVT::i32, RetVT.SimpleTy);<br>
+ ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, LHSIsKill, RHSReg, RHSIsKill);<br>
+ if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {<br>
+ uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;<br>
+ ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);<br>
+ }<br>
+ return ResultReg;<br>
}<br>
<br>
unsigned AArch64FastISel::emitLogicalOp_ri(unsigned ISDOpc, MVT RetVT,<br>
@@ -1301,6 +1303,9 @@ unsigned AArch64FastISel::emitLogicalOp_<br>
switch (RetVT.SimpleTy) {<br>
default:<br>
return 0;<br>
+ case MVT::i1:<br>
+ case MVT::i8:<br>
+ case MVT::i16:<br>
case MVT::i32: {<br>
unsigned Idx = ISDOpc - ISD::AND;<br>
Opc = OpcTable[Idx][0];<br>
@@ -1318,8 +1323,14 @@ unsigned AArch64FastISel::emitLogicalOp_<br>
if (!AArch64_AM::isLogicalImmediate(Imm, RegSize))<br>
return 0;<br>
<br>
- return fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,<br>
- AArch64_AM::encodeLogicalImmediate(Imm, RegSize));<br>
+ unsigned ResultReg =<br>
+ fastEmitInst_ri(Opc, RC, LHSReg, LHSIsKill,<br>
+ AArch64_AM::encodeLogicalImmediate(Imm, RegSize));<br>
+ if (RetVT >= MVT::i8 && RetVT <= MVT::i16 && ISDOpc != ISD::AND) {<br>
+ uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;<br>
+ ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);<br>
+ }<br>
+ return ResultReg;<br>
}<br>
<br>
unsigned AArch64FastISel::emitLogicalOp_rs(unsigned ISDOpc, MVT RetVT,<br>
@@ -1336,19 +1347,28 @@ unsigned AArch64FastISel::emitLogicalOp_<br>
const TargetRegisterClass *RC;<br>
unsigned Opc;<br>
switch (RetVT.SimpleTy) {<br>
- default:<br>
- return 0;<br>
- case MVT::i32:<br>
- Opc = OpcTable[ISDOpc - ISD::AND][0];<br>
- RC = &AArch64::GPR32RegClass;<br>
- break;<br>
- case MVT::i64:<br>
- Opc = OpcTable[ISDOpc - ISD::AND][1];<br>
- RC = &AArch64::GPR64RegClass;<br>
- break;<br>
+ default:<br>
+ return 0;<br>
+ case MVT::i1:<br>
+ case MVT::i8:<br>
+ case MVT::i16:<br>
+ case MVT::i32:<br>
+ Opc = OpcTable[ISDOpc - ISD::AND][0];<br>
+ RC = &AArch64::GPR32RegClass;<br>
+ break;<br>
+ case MVT::i64:<br>
+ Opc = OpcTable[ISDOpc - ISD::AND][1];<br>
+ RC = &AArch64::GPR64RegClass;<br>
+ break;<br>
}<br>
- return fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,<br>
- AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));<br>
+ unsigned ResultReg =<br>
+ fastEmitInst_rri(Opc, RC, LHSReg, LHSIsKill, RHSReg, RHSIsKill,<br>
+ AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));<br>
+ if (RetVT >= MVT::i8 && RetVT <= MVT::i16) {<br>
+ uint64_t Mask = (RetVT == MVT::i8) ? 0xff : 0xffff;<br>
+ ResultReg = emitAnd_ri(MVT::i32, ResultReg, /*IsKill=*/true, Mask);<br>
+ }<br>
+ return ResultReg;<br>
}<br>
<br>
unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,<br>
@@ -1447,25 +1467,11 @@ bool AArch64FastISel::selectAddSub(const<br>
return true;<br>
}<br>
<br>
-bool AArch64FastISel::selectLogicalOp(const Instruction *I) {<br>
+bool AArch64FastISel::selectLogicalOp(const Instruction *I, unsigned ISDOpc) {<br>
MVT VT;<br>
if (!isTypeSupported(I->getType(), VT))<br>
return false;<br>
<br>
- unsigned ISDOpc;<br>
- switch (I->getOpcode()) {<br>
- default:<br>
- llvm_unreachable("Unexpected opcode.");<br>
- case Instruction::And:<br>
- ISDOpc = ISD::AND;<br>
- break;<br>
- case Instruction::Or:<br>
- ISDOpc = ISD::OR;<br>
- break;<br>
- case Instruction::Xor:<br>
- ISDOpc = ISD::XOR;<br>
- break;<br>
- }<br>
unsigned ResultReg =<br>
emitLogicalOp(ISDOpc, VT, I->getOperand(0), I->getOperand(1));<br>
if (!ResultReg)<br>
@@ -3578,9 +3584,15 @@ bool AArch64FastISel::fastSelectInstruct<br>
return true;<br>
break;<br>
case Instruction::And:<br>
+ if (selectLogicalOp(I, ISD::AND))<br>
+ return true;<br>
+ break;<br>
case Instruction::Or:<br>
+ if (selectLogicalOp(I, ISD::OR))<br>
+ return true;<br>
+ break;<br>
case Instruction::Xor:<br>
- if (selectLogicalOp(I))<br>
+ if (selectLogicalOp(I, ISD::XOR))<br>
return true;<br>
break;<br>
case Instruction::Br:<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/fast-isel-logic-op.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-logic-op.ll?rev=217732&r1=217731&r2=217732&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fast-isel-logic-op.ll?rev=217732&r1=217731&r2=217732&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/fast-isel-logic-op.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/fast-isel-logic-op.ll Sat Sep 13 18:46:28 2014<br>
@@ -2,6 +2,29 @@<br>
; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s<br>
<br>
; AND<br>
+define zeroext i1 @and_rr_i1(i1 signext %a, i1 signext %b) {<br>
+; CHECK-LABEL: and_rr_i1<br>
+; CHECK: and [[REG:w[0-9]+]], w0, w1<br>
+ %1 = and i1 %a, %b<br>
+ ret i1 %1<br>
+}<br>
+<br>
+define zeroext i8 @and_rr_i8(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: and_rr_i8<br>
+; CHECK: and [[REG:w[0-9]+]], w0, w1<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff<br>
+ %1 = and i8 %a, %b<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define zeroext i16 @and_rr_i16(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: and_rr_i16<br>
+; CHECK: and [[REG:w[0-9]+]], w0, w1<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff<br>
+ %1 = and i16 %a, %b<br>
+ ret i16 %1<br>
+}<br>
+<br>
define i32 @and_rr_i32(i32 %a, i32 %b) {<br>
; CHECK-LABEL: and_rr_i32<br>
; CHECK: and w0, w0, w1<br>
@@ -16,6 +39,27 @@ define i64 @and_rr_i64(i64 %a, i64 %b) {<br>
ret i64 %1<br>
}<br>
<br>
+define zeroext i1 @and_ri_i1(i1 signext %a) {<br>
+; CHECK-LABEL: and_ri_i1<br>
+; CHECK: and {{w[0-9]+}}, w0, #0x1<br>
+ %1 = and i1 %a, 1<br>
+ ret i1 %1<br>
+}<br>
+<br>
+define zeroext i8 @and_ri_i8(i8 signext %a) {<br>
+; CHECK-LABEL: and_ri_i8<br>
+; CHECK: and {{w[0-9]+}}, w0, #0xf<br>
+ %1 = and i8 %a, 15<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define zeroext i16 @and_ri_i16(i16 signext %a) {<br>
+; CHECK-LABEL: and_ri_i16<br>
+; CHECK: and {{w[0-9]+}}, w0, #0xff<br>
+ %1 = and i16 %a, 255<br>
+ ret i16 %1<br>
+}<br>
+<br>
define i32 @and_ri_i32(i32 %a) {<br>
; CHECK-LABEL: and_ri_i32<br>
; CHECK: and w0, w0, #0xff<br>
@@ -30,6 +74,24 @@ define i64 @and_ri_i64(i64 %a) {<br>
ret i64 %1<br>
}<br>
<br>
+define zeroext i8 @and_rs_i8(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: and_rs_i8<br>
+; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #4<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}<br>
+ %1 = shl i8 %b, 4<br>
+ %2 = and i8 %a, %1<br>
+ ret i8 %2<br>
+}<br>
+<br>
+define zeroext i16 @and_rs_i16(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: and_rs_i16<br>
+; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #8<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}<br>
+ %1 = shl i16 %b, 8<br>
+ %2 = and i16 %a, %1<br>
+ ret i16 %2<br>
+}<br>
+<br>
define i32 @and_rs_i32(i32 %a, i32 %b) {<br>
; CHECK-LABEL: and_rs_i32<br>
; CHECK: and w0, w0, w1, lsl #8<br>
@@ -47,6 +109,29 @@ define i64 @and_rs_i64(i64 %a, i64 %b) {<br>
}<br>
<br>
; OR<br>
+define zeroext i1 @or_rr_i1(i1 signext %a, i1 signext %b) {<br>
+; CHECK-LABEL: or_rr_i1<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, w1<br>
+ %1 = or i1 %a, %b<br>
+ ret i1 %1<br>
+}<br>
+<br>
+define zeroext i8 @or_rr_i8(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: or_rr_i8<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, w1<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff<br>
+ %1 = or i8 %a, %b<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define zeroext i16 @or_rr_i16(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: or_rr_i16<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, w1<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff<br>
+ %1 = or i16 %a, %b<br>
+ ret i16 %1<br>
+}<br>
+<br>
define i32 @or_rr_i32(i32 %a, i32 %b) {<br>
; CHECK-LABEL: or_rr_i32<br>
; CHECK: orr w0, w0, w1<br>
@@ -61,6 +146,22 @@ define i64 @or_rr_i64(i64 %a, i64 %b) {<br>
ret i64 %1<br>
}<br>
<br>
+define zeroext i8 @or_ri_i8(i8 %a) {<br>
+; CHECK-LABEL: or_ri_i8<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, #0xf<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff<br>
+ %1 = or i8 %a, 15<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define zeroext i16 @or_ri_i16(i16 %a) {<br>
+; CHECK-LABEL: or_ri_i16<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, #0xff<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff<br>
+ %1 = or i16 %a, 255<br>
+ ret i16 %1<br>
+}<br>
+<br>
define i32 @or_ri_i32(i32 %a) {<br>
; CHECK-LABEL: or_ri_i32<br>
; CHECK: orr w0, w0, #0xff<br>
@@ -75,6 +176,24 @@ define i64 @or_ri_i64(i64 %a) {<br>
ret i64 %1<br>
}<br>
<br>
+define zeroext i8 @or_rs_i8(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: or_rs_i8<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #4<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}<br>
+ %1 = shl i8 %b, 4<br>
+ %2 = or i8 %a, %1<br>
+ ret i8 %2<br>
+}<br>
+<br>
+define zeroext i16 @or_rs_i16(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: or_rs_i16<br>
+; CHECK: orr [[REG:w[0-9]+]], w0, w1, lsl #8<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}<br>
+ %1 = shl i16 %b, 8<br>
+ %2 = or i16 %a, %1<br>
+ ret i16 %2<br>
+}<br>
+<br>
define i32 @or_rs_i32(i32 %a, i32 %b) {<br>
; CHECK-LABEL: or_rs_i32<br>
; CHECK: orr w0, w0, w1, lsl #8<br>
@@ -92,6 +211,29 @@ define i64 @or_rs_i64(i64 %a, i64 %b) {<br>
}<br>
<br>
; XOR<br>
+define zeroext i1 @xor_rr_i1(i1 signext %a, i1 signext %b) {<br>
+; CHECK-LABEL: xor_rr_i1<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, w1<br>
+ %1 = xor i1 %a, %b<br>
+ ret i1 %1<br>
+}<br>
+<br>
+define zeroext i8 @xor_rr_i8(i8 signext %a, i8 signext %b) {<br>
+; CHECK-LABEL: xor_rr_i8<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, w1<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff<br>
+ %1 = xor i8 %a, %b<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define zeroext i16 @xor_rr_i16(i16 signext %a, i16 signext %b) {<br>
+; CHECK-LABEL: xor_rr_i16<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, w1<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff<br>
+ %1 = xor i16 %a, %b<br>
+ ret i16 %1<br>
+}<br>
+<br>
define i32 @xor_rr_i32(i32 %a, i32 %b) {<br>
; CHECK-LABEL: xor_rr_i32<br>
; CHECK: eor w0, w0, w1<br>
@@ -106,6 +248,22 @@ define i64 @xor_rr_i64(i64 %a, i64 %b) {<br>
ret i64 %1<br>
}<br>
<br>
+define zeroext i8 @xor_ri_i8(i8 signext %a) {<br>
+; CHECK-LABEL: xor_ri_i8<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, #0xf<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xff<br>
+ %1 = xor i8 %a, 15<br>
+ ret i8 %1<br>
+}<br>
+<br>
+define zeroext i16 @xor_ri_i16(i16 signext %a) {<br>
+; CHECK-LABEL: xor_ri_i16<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, #0xff<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], #0xffff<br>
+ %1 = xor i16 %a, 255<br>
+ ret i16 %1<br>
+}<br>
+<br>
define i32 @xor_ri_i32(i32 %a) {<br>
; CHECK-LABEL: xor_ri_i32<br>
; CHECK: eor w0, w0, #0xff<br>
@@ -120,6 +278,24 @@ define i64 @xor_ri_i64(i64 %a) {<br>
ret i64 %1<br>
}<br>
<br>
+define zeroext i8 @xor_rs_i8(i8 %a, i8 %b) {<br>
+; CHECK-LABEL: xor_rs_i8<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #4<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xff|#0xf0}}<br>
+ %1 = shl i8 %b, 4<br>
+ %2 = xor i8 %a, %1<br>
+ ret i8 %2<br>
+}<br>
+<br>
+define zeroext i16 @xor_rs_i16(i16 %a, i16 %b) {<br>
+; CHECK-LABEL: xor_rs_i16<br>
+; CHECK: eor [[REG:w[0-9]+]], w0, w1, lsl #8<br>
+; CHECK-NEXT: and {{w[0-9]+}}, [[REG]], {{#0xffff|#0xff00}}<br>
+ %1 = shl i16 %b, 8<br>
+ %2 = xor i16 %a, %1<br>
+ ret i16 %2<br>
+}<br>
+<br>
define i32 @xor_rs_i32(i32 %a, i32 %b) {<br>
; CHECK-LABEL: xor_rs_i32<br>
; CHECK: eor w0, w0, w1, lsl #8<br>
<br>
<br>
_______________________________________________<br>
llvm-commits mailing list<br>
<a href="mailto:llvm-commits@cs.uiuc.edu" target="_blank">llvm-commits@cs.uiuc.edu</a><br>
<a href="http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits" target="_blank">http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits</a><br>
</blockquote></div><br></div>
</div></blockquote></div><br></div></div></div></blockquote></div><br></div>