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<p class="MsoNormal">Hi Renato,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">This patch is a small bugfix for the load/store optimizer. If the CPSR is live, we can’t safely materialize a base register + offset in Thumb-1.<o:p></o:p></p>
<p class="MsoNormal">There is no test case because I haven’t actually seen this cause problems in real code – but theoretically, it’s possible to get spill code inserted between e.g. a CMP + Bcc, which would then be a candidate for merging.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">OK to commit?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Cheers<o:p></o:p></p>
<p class="MsoNormal">Moritz<o:p></o:p></p>
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