<html><head><meta http-equiv="Content-Type" content="text/html charset=us-ascii"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hi Chandler,<div><br></div><div>Sorry for the late reply I was on holiday this past weekend. No problem backing this out and top of tree works fine with the test cases I have for the original problem I was trying to address. Your test looked like you had to chase down quite a rabbit hole. Thanks for the much better fix!</div><div><br></div><div>Kev</div><div><br><div><div>On Sep 6, 2014, at 3:17 AM, Chandler Carruth <<a href="mailto:chandlerc@gmail.com">chandlerc@gmail.com</a>> wrote:</div><br class="Apple-interchange-newline"><blockquote type="cite">Hey Kevin,<br><br><div>Sorry for the commit mail necromancy, but I just backed this out and reworked it in r217310 to return support for forms that actually used negative immediate operands on these instructions. I kept all of the added tests and they continue to pass in addition to new tests, but wanted you to have a chance to check it against any internal thing sooner rather than later in case there is a subtle problem here.</div><div><br></div><div>Thanks,</div><div>-Chandler</div><br><div class="gmail_quote">On Wed Jul 27 2011 at 4:04:24 PM Kevin Enderby <<a href="mailto:enderby@apple.com" target="_blank">enderby@apple.com</a>> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: enderby<br>
Date: Wed Jul 27 18:01:50 2011<br>
New Revision: 136287<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=136287&view=rev" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject?rev=136287&view=rev</a><br>
Log:<br>
Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.<br>
<br>
llvm-mc gives an "invalid operand" error for instructions that take an unsigned<br>
immediate which have the high bit set such as:<br>
pblendw $0xc5, %xmm2, %xmm1<br>
llvm-mc treats all x86 immediates as signed values and range checks them.<br>
A small number of x86 instructions use the imm8 field as a set of bits.<br>
This change only changes those instructions and where the high bit is not<br>
ignored. The others remain unchanged.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/X86/<u></u>AsmP<u></u>arser/X86AsmParser.cpp<br>
llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrInfo.td<br>
llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrSSE.td<br>
llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>avx.s<br>
llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>coverage.s<br>
llvm/trunk/utils/TableGen/<u></u>EDEm<u></u>itter.cpp<br>
llvm/trunk/utils/TableGen/<u></u>X86R<u></u>ecognizableInstr.cpp<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>AsmP<u></u>arser/X86AsmParser.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/lib/Target/<u></u>X8<u></u>6/AsmParser/X86AsmParser.<u></u>cpp?<u></u>rev=136287&r1=136286&r2=<u></u>136287<u></u>&view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>AsmP<u></u>arser/X86AsmParser.cpp (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>AsmP<u></u>arser/X86AsmParser.cpp Wed Jul 27 18:01:50 2011<br>
@@ -226,6 +226,21 @@<br>
(0x00000000FFFFFF80ULL <= Value && Value <= 0x00000000FFFFFFFFULL)||<br>
(0xFFFFFFFFFFFFFF80ULL <= Value && Value <= 0xFFFFFFFFFFFFFFFFULL));<br>
}<br>
+ bool isImmZExtu32u8() const {<br>
+ if (!isImm())<br>
+ return false;<br>
+<br>
+ // If this isn't a constant expr, just assume it fits and let relaxation<br>
+ // handle it.<br>
+ const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(<u></u>getIm<u></u>m());<br>
+ if (!CE)<br>
+ return true;<br>
+<br>
+ // Otherwise, check the value is in a range that makes sense for this<br>
+ // extension.<br>
+ uint64_t Value = CE->getValue();<br>
+ return (Value <= 0x00000000000000FFULL);<br>
+ }<br>
bool isImmSExti64i8() const {<br>
if (!isImm())<br>
return false;<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrInfo.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/lib/Target/<u></u>X8<u></u>6/X86InstrInfo.td?rev=<u></u>136287&<u></u>r1=136286&r2=136287&<u></u>view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrInfo.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrInfo.td Wed Jul 27 18:01:50 2011<br>
@@ -331,6 +331,11 @@<br>
let RenderMethod = "addImmOperands";<br>
}<br>
<br>
+class ImmZExtAsmOperandClass : AsmOperandClass {<br>
+ let SuperClasses = [ImmAsmOperand];<br>
+ let RenderMethod = "addImmOperands";<br>
+}<br>
+<br>
// Sign-extended immediate classes. We don't need to define the full lattice<br>
// here because there is no instruction with an ambiguity between ImmSExti64i32<br>
// and ImmSExti32i8.<br>
@@ -358,6 +363,12 @@<br>
let Name = "ImmSExti32i8";<br>
}<br>
<br>
+// [0, 0x000000FF]<br>
+def ImmZExtu32u8AsmOperand : ImmZExtAsmOperandClass {<br>
+ let Name = "ImmZExtu32u8";<br>
+}<br>
+<br>
+<br>
// [0, 0x0000007F] |<br>
// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF]<br>
def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass {<br>
@@ -377,6 +388,11 @@<br>
let ParserMatchClass = ImmSExti32i8AsmOperand;<br>
let OperandType = "OPERAND_IMMEDIATE";<br>
}<br>
+// 32-bits but only 8 bits are significant, and those 8 bits are unsigned.<br>
+def u32u8imm : Operand<i32> {<br>
+ let ParserMatchClass = ImmZExtu32u8AsmOperand;<br>
+ let OperandType = "OPERAND_IMMEDIATE";<br>
+}<br>
<br>
// 64-bits but only 32 bits are significant.<br>
def i64i32imm : Operand<i64> {<br>
<br>
Modified: llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrSSE.td<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/lib/Target/<u></u>X8<u></u>6/X86InstrSSE.td?rev=136287&<u></u>r1<u></u>=136286&r2=136287&view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrSSE.td (original)<br>
+++ llvm/trunk/lib/Target/X86/<u></u>X86I<u></u>nstrSSE.td Wed Jul 27 18:01:50 2011<br>
@@ -4298,7 +4298,7 @@<br>
// in the target vector.<br>
multiclass SS41I_insertf32<bits<8> opc, string asm, bit Is2Addr = 1> {<br>
def rr : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),<br>
- (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),<br>
+ (ins VR128:$src1, VR128:$src2, u32u8imm:$src3),<br>
!if(Is2Addr,<br>
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),<br>
!strconcat(asm,<br>
@@ -4307,7 +4307,7 @@<br>
(X86insrtps VR128:$src1, VR128:$src2, imm:$src3))]>,<br>
OpSize;<br>
def rm : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),<br>
- (ins VR128:$src1, f32mem:$src2, i32i8imm:$src3),<br>
+ (ins VR128:$src1, f32mem:$src2, u32u8imm:$src3),<br>
!if(Is2Addr,<br>
!strconcat(asm, "\t{$src3, $src2, $dst|$dst, $src2, $src3}"),<br>
!strconcat(asm,<br>
@@ -4721,7 +4721,7 @@<br>
X86MemOperand x86memop, bit Is2Addr = 1> {<br>
let isCommutable = 1 in<br>
def rri : SS4AIi8<opc, MRMSrcReg, (outs RC:$dst),<br>
- (ins RC:$src1, RC:$src2, i32i8imm:$src3),<br>
+ (ins RC:$src1, RC:$src2, u32u8imm:$src3),<br>
!if(Is2Addr,<br>
!strconcat(OpcodeStr,<br>
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),<br>
@@ -4730,7 +4730,7 @@<br>
[(set RC:$dst, (IntId RC:$src1, RC:$src2, imm:$src3))]>,<br>
OpSize;<br>
def rmi : SS4AIi8<opc, MRMSrcMem, (outs RC:$dst),<br>
- (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),<br>
+ (ins RC:$src1, x86memop:$src2, u32u8imm:$src3),<br>
!if(Is2Addr,<br>
!strconcat(OpcodeStr,<br>
"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),<br>
<br>
Modified: llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>avx.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-avx.s?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/test/MC/<u></u>X86/<u></u>x86-32-avx.s?rev=136287&<u></u>r1=<u></u>136286&r2=136287&view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>avx.s (original)<br>
+++ llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>avx.s Wed Jul 27 18:01:50 2011<br>
@@ -3281,3 +3281,25 @@<br>
// CHECK: encoding: [0xc4,0xe3,0x51,0x44,0x18,<u></u>0x11<u></u>]<br>
vpclmulqdq $17, (%eax), %xmm5, %xmm3<br>
<br>
+// <a href="rdar://9795008">rdar://9795008</a><br>
+// These instructions take a mask not an 8-bit sign extended value.<br>
+// CHECK: vblendps $129, %ymm2, %ymm5, %ymm1<br>
+ vblendps $0x81, %ymm2, %ymm5, %ymm1<br>
+// CHECK: vblendps $129, (%eax), %ymm5, %ymm1<br>
+ vblendps $0x81, (%eax), %ymm5, %ymm1<br>
+// CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1<br>
+ vblendpd $0x81, %ymm2, %ymm5, %ymm1<br>
+// CHECK: vblendpd $129, (%eax), %ymm5, %ymm1<br>
+ vblendpd $0x81, (%eax), %ymm5, %ymm1<br>
+// CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1<br>
+ vpblendw $0x81, %xmm2, %xmm5, %xmm1<br>
+// CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1<br>
+ vmpsadbw $0x81, %xmm2, %xmm5, %xmm1<br>
+// CHECK: vdpps $129, %ymm2, %ymm5, %ymm1<br>
+ vdpps $0x81, %ymm2, %ymm5, %ymm1<br>
+// CHECK: vdpps $129, (%eax), %ymm5, %ymm1<br>
+ vdpps $0x81, (%eax), %ymm5, %ymm1<br>
+// CHECK: vdppd $129, %xmm2, %xmm5, %xmm1<br>
+ vdppd $0x81, %xmm2, %xmm5, %xmm1<br>
+// CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1<br>
+ vinsertps $0x81, %xmm3, %xmm2, %xmm1<br>
<br>
Modified: llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>coverage.s<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/test/MC/<u></u>X86/<u></u>x86-32-coverage.s?rev=<u></u>136287&<u></u>r1=136286&r2=136287&<u></u>view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>coverage.s (original)<br>
+++ llvm/trunk/test/MC/X86/x86-32-<u></u><u></u>coverage.s Wed Jul 27 18:01:50 2011<br>
@@ -19575,3 +19575,20 @@<br>
blendvps (%rax), %xmm1<br>
// CHECK: blendvps %xmm2, %xmm1 # encoding: [0x66,0x0f,0x38,0x14,0xca]<br>
blendvps %xmm2, %xmm1<br>
+<br>
+// <a href="rdar://9795008">rdar://9795008</a><br>
+// These instructions take a mask not an 8-bit sign extended value.<br>
+// CHECK: blendps $129, %xmm2, %xmm1<br>
+ blendps $0x81, %xmm2, %xmm1<br>
+// CHECK: blendpd $129, %xmm2, %xmm1<br>
+ blendpd $0x81, %xmm2, %xmm1<br>
+// CHECK: pblendw $129, %xmm2, %xmm1<br>
+ pblendw $0x81, %xmm2, %xmm1<br>
+// CHECK: mpsadbw $129, %xmm2, %xmm1<br>
+ mpsadbw $0x81, %xmm2, %xmm1<br>
+// CHECK: dpps $129, %xmm2, %xmm1<br>
+ dpps $0x81, %xmm2, %xmm1<br>
+// CHECK: dppd $129, %xmm2, %xmm1<br>
+ dppd $0x81, %xmm2, %xmm1<br>
+// CHECK: insertps $129, %xmm2, %xmm1<br>
+ insertps $0x81, %xmm2, %xmm1<br>
<br>
Modified: llvm/trunk/utils/TableGen/<u></u>EDEm<u></u>itter.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/utils/<u></u>TableGe<u></u>n/EDEmitter.cpp?rev=<u></u>136287&r1=<u></u>136286&r2=136287&<u></u>view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/utils/TableGen/<u></u>EDEm<u></u>itter.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<u></u>EDEm<u></u>itter.cpp Wed Jul 27 18:01:50 2011<br>
@@ -279,6 +279,7 @@<br>
IMM("i16i8imm");<br>
IMM("i32imm");<br>
IMM("i32i8imm");<br>
+ IMM("u32u8imm");<br>
IMM("i64imm");<br>
IMM("i64i8imm");<br>
IMM("i64i32imm");<br>
<br>
Modified: llvm/trunk/utils/TableGen/<u></u>X86R<u></u>ecognizableInstr.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=136287&r1=136286&r2=136287&view=diff" target="_blank">http://llvm.org/viewvc/llvm-<u></u>pr<u></u>oject/llvm/trunk/utils/<u></u>TableGe<u></u>n/X86RecognizableInstr.<u></u>cpp?<u></u>rev=136287&r1=136286&r2=<u></u>136287<u></u>&view=diff</a><br>
==============================<u></u><u></u>==============================<u></u><u></u>==================<br>
--- llvm/trunk/utils/TableGen/<u></u>X86R<u></u>ecognizableInstr.cpp (original)<br>
+++ llvm/trunk/utils/TableGen/<u></u>X86R<u></u>ecognizableInstr.cpp Wed Jul 27 18:01:50 2011<br>
@@ -984,6 +984,7 @@<br>
TYPE("i32mem", TYPE_Mv)<br>
TYPE("i32imm", TYPE_IMMv)<br>
TYPE("i32i8imm", TYPE_IMM32)<br>
+ TYPE("u32u8imm", TYPE_IMM32)<br>
TYPE("GR32", TYPE_Rv)<br>
TYPE("i64mem", TYPE_Mv)<br>
TYPE("i64i32imm", TYPE_IMM64)<br>
@@ -1044,6 +1045,7 @@<br>
ENCODING("i16imm", ENCODING_IW)<br>
}<br>
ENCODING("i32i8imm", ENCODING_IB)<br>
+ ENCODING("u32u8imm", ENCODING_IB)<br>
ENCODING("SSECC", ENCODING_IB)<br>
ENCODING("i16imm", ENCODING_Iv)<br>
ENCODING("i16i8imm", ENCODING_IB)<br>
<br>
<br>
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</blockquote></div>
</blockquote></div><br></div></body></html>