<div dir="ltr">Hi Sergey,<div><br></div><div>This looks great! I have a couple of extra review comments though.</div><div><br></div><div> * Copy-pasto here?</div><div><span style="font-family:arial,sans-serif;font-size:13px">+ DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n</span></div><div><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div><div><span style="font-family:arial,sans-serif;font-size:13px"> * Please can you remove the surrounding braces for one-liner if/for statements.</span></div><div><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div><div><span style="font-family:arial,sans-serif;font-size:13px">Cheers,</span></div><div><span style="font-family:arial,sans-serif;font-size:13px"><br></span></div><div><span style="font-family:arial,sans-serif;font-size:13px">James</span></div></div><div class="gmail_extra"><br><br><div class="gmail_quote">On 5 September 2014 03:55, Jiangning Liu <span dir="ltr"><<a href="mailto:jiangning.liu@arm.com" target="_blank">jiangning.liu@arm.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Author: jiangning<br>
Date: Thu Sep 4 21:55:24 2014<br>
New Revision: 217220<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=217220&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=217220&view=rev</a><br>
Log:<br>
[AArch64] Add pass to enable additional comparison optimizations by CSE.<br>
<br>
Patched by Sergey Dmitrouk.<br>
<br>
This pass tries to make consecutive compares of values use same operands to<br>
allow CSE pass to remove duplicated instructions. For this it analyzes<br>
branches and adjusts comparisons with immediate values by converting:<br>
<br>
GE -> GT<br>
GT -> GE<br>
LT -> LE<br>
LE -> LT<br>
<br>
and adjusting immediate values appropriately. It basically corrects two<br>
immediate values towards each other to make them equal.<br>
<br>
<br>
Added:<br>
llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp<br>
llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64.h<br>
llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp<br>
llvm/trunk/lib/Target/AArch64/CMakeLists.txt<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64.h<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.h?rev=217220&r1=217219&r2=217220&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64.h?rev=217220&r1=217219&r2=217220&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64.h (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64.h Thu Sep 4 21:55:24 2014<br>
@@ -36,6 +36,7 @@ FunctionPass *createAArch64StorePairSupp<br>
FunctionPass *createAArch64ExpandPseudoPass();<br>
FunctionPass *createAArch64LoadStoreOptimizationPass();<br>
ModulePass *createAArch64PromoteConstantPass();<br>
+FunctionPass *createAArch64ConditionOptimizerPass();<br>
FunctionPass *createAArch64AddressTypePromotionPass();<br>
FunctionPass *createAArch64A57FPLoadBalancing();<br>
/// \brief Creates an ARM-specific Target Transformation Info pass.<br>
<br>
Added: llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp?rev=217220&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp?rev=217220&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp (added)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp Thu Sep 4 21:55:24 2014<br>
@@ -0,0 +1,405 @@<br>
+//=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//<br>
+//<br>
+// The LLVM Compiler Infrastructure<br>
+//<br>
+// This file is distributed under the University of Illinois Open Source<br>
+// License. See LICENSE.TXT for details.<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+//<br>
+// This pass tries to make consecutive compares of values use same operands to<br>
+// allow CSE pass to remove duplicated instructions. For this it analyzes<br>
+// branches and adjusts comparisons with immediate values by converting:<br>
+// * GE -> GT<br>
+// * GT -> GE<br>
+// * LT -> LE<br>
+// * LE -> LT<br>
+// and adjusting immediate values appropriately. It basically corrects two<br>
+// immediate values towards each other to make them equal.<br>
+//<br>
+// Consider the following example in C:<br>
+//<br>
+// if ((a < 5 && ...) || (a > 5 && ...)) {<br>
+// ~~~~~ ~~~~~<br>
+// ^ ^<br>
+// x y<br>
+//<br>
+// Here both "x" and "y" expressions compare "a" with "5". When "x" evaluates<br>
+// to "false", "y" can just check flags set by the first comparison. As a<br>
+// result of the canonicalization employed by<br>
+// SelectionDAGBuilder::visitSwitchCase, DAGCombine, and other target-specific<br>
+// code, assembly ends up in the form that is not CSE friendly:<br>
+//<br>
+// ...<br>
+// cmp w8, #4<br>
+// <a href="http://b.gt" target="_blank">b.gt</a> .LBB0_3<br>
+// ...<br>
+// .LBB0_3:<br>
+// cmp w8, #6<br>
+// <a href="http://b.lt" target="_blank">b.lt</a> .LBB0_6<br>
+// ...<br>
+//<br>
+// Same assembly after the pass:<br>
+//<br>
+// ...<br>
+// cmp w8, #5<br>
+// <a href="http://b.ge" target="_blank">b.ge</a> .LBB0_3<br>
+// ...<br>
+// .LBB0_3:<br>
+// cmp w8, #5 // <-- CSE pass removes this instruction<br>
+// b.le .LBB0_6<br>
+// ...<br>
+//<br>
+// Currently only SUBS and ADDS followed by b.?? are supported.<br>
+//<br>
+// TODO: maybe handle TBNZ/TBZ the same way as CMP when used instead for "a < 0"<br>
+// TODO: handle other conditional instructions (e.g. CSET)<br>
+// TODO: allow second branching to be anything if it doesn't require adjusting<br>
+//<br>
+//===----------------------------------------------------------------------===//<br>
+<br>
+#include "AArch64.h"<br>
+#include "llvm/ADT/DepthFirstIterator.h"<br>
+#include "llvm/ADT/SmallVector.h"<br>
+#include "llvm/ADT/Statistic.h"<br>
+#include "llvm/CodeGen/MachineDominators.h"<br>
+#include "llvm/CodeGen/MachineFunction.h"<br>
+#include "llvm/CodeGen/MachineFunctionPass.h"<br>
+#include "llvm/CodeGen/MachineInstrBuilder.h"<br>
+#include "llvm/CodeGen/Passes.h"<br>
+#include "llvm/Support/CommandLine.h"<br>
+#include "llvm/Support/Debug.h"<br>
+#include "llvm/Support/raw_ostream.h"<br>
+#include "llvm/Target/TargetInstrInfo.h"<br>
+#include "llvm/Target/TargetSubtargetInfo.h"<br>
+#include <cstdlib><br>
+#include <tuple><br>
+<br>
+using namespace llvm;<br>
+<br>
+#define DEBUG_TYPE "aarch64-condopt"<br>
+<br>
+STATISTIC(NumConditionsAdjusted, "Number of conditions adjusted");<br>
+<br>
+namespace {<br>
+class AArch64ConditionOptimizer : public MachineFunctionPass {<br>
+ const TargetInstrInfo *TII;<br>
+ MachineDominatorTree *DomTree;<br>
+<br>
+public:<br>
+ // Stores immediate, compare instruction opcode and branch condition (in this<br>
+ // order) of adjusted comparison.<br>
+ typedef std::tuple<int, int, AArch64CC::CondCode> CmpInfo;<br>
+<br>
+ static char ID;<br>
+ AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}<br>
+ void getAnalysisUsage(AnalysisUsage &AU) const override;<br>
+ MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);<br>
+ CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);<br>
+ void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);<br>
+ bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,<br>
+ int ToImm);<br>
+ bool runOnMachineFunction(MachineFunction &MF) override;<br>
+ const char *getPassName() const override {<br>
+ return "AArch64 Condition Optimizer";<br>
+ }<br>
+};<br>
+} // end anonymous namespace<br>
+<br>
+char AArch64ConditionOptimizer::ID = 0;<br>
+<br>
+namespace llvm {<br>
+void initializeAArch64ConditionOptimizerPass(PassRegistry &);<br>
+}<br>
+<br>
+INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt",<br>
+ "AArch64 CondOpt Pass", false, false)<br>
+INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)<br>
+INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt",<br>
+ "AArch64 CondOpt Pass", false, false)<br>
+<br>
+FunctionPass *llvm::createAArch64ConditionOptimizerPass() {<br>
+ return new AArch64ConditionOptimizer();<br>
+}<br>
+<br>
+void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const {<br>
+ AU.addRequired<MachineDominatorTree>();<br>
+ AU.addPreserved<MachineDominatorTree>();<br>
+ MachineFunctionPass::getAnalysisUsage(AU);<br>
+}<br>
+<br>
+// Finds compare instruction that corresponds to supported types of branching.<br>
+// Returns the instruction or nullptr on failures or detecting unsupported<br>
+// instructions.<br>
+MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(<br>
+ MachineBasicBlock *MBB) {<br>
+ MachineBasicBlock::iterator I = MBB->getFirstTerminator();<br>
+ if (I == MBB->end()) {<br>
+ return nullptr;<br>
+ }<br>
+<br>
+ if (I->getOpcode() != AArch64::Bcc) {<br>
+ return nullptr;<br>
+ }<br>
+<br>
+ // Now find the instruction controlling the terminator.<br>
+ for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {<br>
+ --I;<br>
+ assert(!I->isTerminator() && "Spurious terminator");<br>
+ switch (I->getOpcode()) {<br>
+ // cmp is an alias for subs with a dead destination register.<br>
+ case AArch64::SUBSWri:<br>
+ case AArch64::SUBSXri:<br>
+ // cmn is an alias for adds with a dead destination register.<br>
+ case AArch64::ADDSWri:<br>
+ case AArch64::ADDSXri:<br>
+ return I;<br>
+<br>
+ case AArch64::SUBSWrr:<br>
+ case AArch64::SUBSXrr:<br>
+ case AArch64::ADDSWrr:<br>
+ case AArch64::ADDSXrr:<br>
+ case AArch64::FCMPSrr:<br>
+ case AArch64::FCMPDrr:<br>
+ case AArch64::FCMPESrr:<br>
+ case AArch64::FCMPEDrr:<br>
+ // Skip comparison instructions without immediate operands.<br>
+ return nullptr;<br>
+ }<br>
+ }<br>
+ DEBUG(dbgs() << "Flags not defined in BB#" << MBB->getNumber() << '\n');<br>
+ return nullptr;<br>
+}<br>
+<br>
+// Changes opcode adds <-> subs considering register operand width.<br>
+static int getComplementOpc(int Opc) {<br>
+ switch (Opc) {<br>
+ case AArch64::ADDSWri: return AArch64::SUBSWri;<br>
+ case AArch64::ADDSXri: return AArch64::SUBSXri;<br>
+ case AArch64::SUBSWri: return AArch64::ADDSWri;<br>
+ case AArch64::SUBSXri: return AArch64::ADDSXri;<br>
+ default:<br>
+ llvm_unreachable("Unexpected opcode");<br>
+ }<br>
+}<br>
+<br>
+// Changes form of comparison inclusive <-> exclusive.<br>
+static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {<br>
+ switch (Cmp) {<br>
+ case AArch64CC::GT: return AArch64CC::GE;<br>
+ case AArch64CC::GE: return AArch64CC::GT;<br>
+ case AArch64CC::LT: return AArch64CC::LE;<br>
+ case AArch64CC::LE: return AArch64CC::LT;<br>
+ default:<br>
+ llvm_unreachable("Unexpected condition code");<br>
+ }<br>
+}<br>
+<br>
+// Transforms GT -> GE, GE -> GT, LT -> LE, LE -> LT by updating comparison<br>
+// operator and condition code.<br>
+AArch64ConditionOptimizer::CmpInfo AArch64ConditionOptimizer::adjustCmp(<br>
+ MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {<br>
+ int Opc = CmpMI->getOpcode();<br>
+<br>
+ // CMN (compare with negative immediate) is an alias to ADDS (as<br>
+ // "operand - negative" == "operand + positive")<br>
+ bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);<br>
+<br>
+ int Correction = (Cmp == AArch64CC::GT) ? 1 : -1;<br>
+ // Negate Correction value for comparison with negative immediate (CMN).<br>
+ if (Negative) {<br>
+ Correction = -Correction;<br>
+ }<br>
+<br>
+ const int OldImm = (int)CmpMI->getOperand(2).getImm();<br>
+ const int NewImm = std::abs(OldImm + Correction);<br>
+<br>
+ // Handle +0 -> -1 and -0 -> +1 (CMN with 0 immediate) transitions by<br>
+ // adjusting compare instruction opcode.<br>
+ if (OldImm == 0 && ((Negative && Correction == 1) ||<br>
+ (!Negative && Correction == -1))) {<br>
+ Opc = getComplementOpc(Opc);<br>
+ }<br>
+<br>
+ return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));<br>
+}<br>
+<br>
+// Applies changes to comparison instruction suggested by adjustCmp().<br>
+void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,<br>
+ const CmpInfo &Info) {<br>
+ int Imm;<br>
+ int Opc;<br>
+ AArch64CC::CondCode Cmp;<br>
+ std::tie(Imm, Opc, Cmp) = Info;<br>
+<br>
+ MachineBasicBlock *const MBB = CmpMI->getParent();<br>
+<br>
+ // Change immediate in comparison instruction (ADDS or SUBS).<br>
+ BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))<br>
+ .addOperand(CmpMI->getOperand(0))<br>
+ .addOperand(CmpMI->getOperand(1))<br>
+ .addImm(Imm)<br>
+ .addOperand(CmpMI->getOperand(3));<br>
+ CmpMI->eraseFromParent();<br>
+<br>
+ // The fact that this comparison was picked ensures that it's related to the<br>
+ // first terminator instruction.<br>
+ MachineInstr *BrMI = MBB->getFirstTerminator();<br>
+<br>
+ // Change condition in branch instruction.<br>
+ BuildMI(*MBB, BrMI, BrMI->getDebugLoc(), TII->get(AArch64::Bcc))<br>
+ .addImm(Cmp)<br>
+ .addOperand(BrMI->getOperand(1));<br>
+ BrMI->eraseFromParent();<br>
+<br>
+ MBB->updateTerminator();<br>
+<br>
+ ++NumConditionsAdjusted;<br>
+}<br>
+<br>
+// Parse a condition code returned by AnalyzeBranch, and compute the CondCode<br>
+// corresponding to TBB.<br>
+// Returns true if parsing was successful, otherwise false is returned.<br>
+static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {<br>
+ // A normal br.cond simply has the condition code.<br>
+ if (Cond[0].getImm() != -1) {<br>
+ assert(Cond.size() == 1 && "Unknown Cond array format");<br>
+ CC = (AArch64CC::CondCode)(int)Cond[0].getImm();<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+// Adjusts one cmp instruction to another one if result of adjustment will allow<br>
+// CSE. Returns true if compare instruction was changed, otherwise false is<br>
+// returned.<br>
+bool AArch64ConditionOptimizer::adjustTo(MachineInstr *CmpMI,<br>
+ AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm)<br>
+{<br>
+ CmpInfo Info = adjustCmp(CmpMI, Cmp);<br>
+ if (std::get<0>(Info) == ToImm && std::get<1>(Info) == To->getOpcode()) {<br>
+ modifyCmp(CmpMI, Info);<br>
+ return true;<br>
+ }<br>
+ return false;<br>
+}<br>
+<br>
+bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {<br>
+ DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"<br>
+ << "********** Function: " << MF.getName() << '\n');<br>
+ TII = MF.getTarget().getSubtargetImpl()->getInstrInfo();<br>
+ DomTree = &getAnalysis<MachineDominatorTree>();<br>
+<br>
+ bool Changed = false;<br>
+<br>
+ // Visit blocks in dominator tree pre-order. The pre-order enables multiple<br>
+ // cmp-conversions from the same head block.<br>
+ // Note that updateDomTree() modifies the children of the DomTree node<br>
+ // currently being visited. The df_iterator supports that; it doesn't look at<br>
+ // child_begin() / child_end() until after a node has been visited.<br>
+ for (MachineDomTreeNode *I : depth_first(DomTree)) {<br>
+ MachineBasicBlock *HBB = I->getBlock();<br>
+<br>
+ SmallVector<MachineOperand, 4> HeadCond;<br>
+ MachineBasicBlock *TBB = nullptr, *FBB = nullptr;<br>
+ if (TII->AnalyzeBranch(*HBB, TBB, FBB, HeadCond)) {<br>
+ continue;<br>
+ }<br>
+<br>
+ // Equivalence check is to skip loops.<br>
+ if (!TBB || TBB == HBB) {<br>
+ continue;<br>
+ }<br>
+<br>
+ SmallVector<MachineOperand, 4> TrueCond;<br>
+ MachineBasicBlock *TBB_TBB = nullptr, *TBB_FBB = nullptr;<br>
+ if (TII->AnalyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) {<br>
+ continue;<br>
+ }<br>
+<br>
+ MachineInstr *HeadCmpMI = findSuitableCompare(HBB);<br>
+ if (!HeadCmpMI) {<br>
+ continue;<br>
+ }<br>
+<br>
+ MachineInstr *TrueCmpMI = findSuitableCompare(TBB);<br>
+ if (!TrueCmpMI) {<br>
+ continue;<br>
+ }<br>
+<br>
+ AArch64CC::CondCode HeadCmp;<br>
+ if (HeadCond.empty() || !parseCond(HeadCond, HeadCmp)) {<br>
+ continue;<br>
+ }<br>
+<br>
+ AArch64CC::CondCode TrueCmp;<br>
+ if (TrueCond.empty() || !parseCond(TrueCond, TrueCmp)) {<br>
+ continue;<br>
+ }<br>
+<br>
+ const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm();<br>
+ const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm();<br>
+<br>
+ DEBUG(dbgs() << "Head branch:\n");<br>
+ DEBUG(dbgs() << "\tcondition: "<br>
+ << AArch64CC::getCondCodeName(HeadCmp) << '\n');<br>
+ DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n');<br>
+<br>
+ DEBUG(dbgs() << "True branch:\n");<br>
+ DEBUG(dbgs() << "\tcondition: "<br>
+ << AArch64CC::getCondCodeName(TrueCmp) << '\n');<br>
+ DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n');<br>
+<br>
+ if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::LT) ||<br>
+ (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::GT)) &&<br>
+ std::abs(TrueImm - HeadImm) == 2) {<br>
+ // This branch transforms machine instructions that correspond to<br>
+ //<br>
+ // 1) (a > {TrueImm} && ...) || (a < {HeadImm} && ...)<br>
+ // 2) (a < {TrueImm} && ...) || (a > {HeadImm} && ...)<br>
+ //<br>
+ // into<br>
+ //<br>
+ // 1) (a >= {NewImm} && ...) || (a <= {NewImm} && ...)<br>
+ // 2) (a <= {NewImm} && ...) || (a >= {NewImm} && ...)<br>
+<br>
+ CmpInfo HeadCmpInfo = adjustCmp(HeadCmpMI, HeadCmp);<br>
+ CmpInfo TrueCmpInfo = adjustCmp(TrueCmpMI, TrueCmp);<br>
+ if (std::get<0>(HeadCmpInfo) == std::get<0>(TrueCmpInfo) &&<br>
+ std::get<1>(HeadCmpInfo) == std::get<1>(TrueCmpInfo)) {<br>
+ modifyCmp(HeadCmpMI, HeadCmpInfo);<br>
+ modifyCmp(TrueCmpMI, TrueCmpInfo);<br>
+ Changed = true;<br>
+ }<br>
+ } else if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::GT) ||<br>
+ (HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::LT)) &&<br>
+ std::abs(TrueImm - HeadImm) == 1) {<br>
+ // This branch transforms machine instructions that correspond to<br>
+ //<br>
+ // 1) (a > {TrueImm} && ...) || (a > {HeadImm} && ...)<br>
+ // 2) (a < {TrueImm} && ...) || (a < {HeadImm} && ...)<br>
+ //<br>
+ // into<br>
+ //<br>
+ // 1) (a <= {NewImm} && ...) || (a > {NewImm} && ...)<br>
+ // 2) (a < {NewImm} && ...) || (a >= {NewImm} && ...)<br>
+<br>
+ // GT -> GE transformation increases immediate value, so picking the<br>
+ // smaller one; LT -> LE decreases immediate value so invert the choice.<br>
+ bool adjustHeadCond = (HeadImm < TrueImm);<br>
+ if (HeadCmp == AArch64CC::LT) {<br>
+ adjustHeadCond = !adjustHeadCond;<br>
+ }<br>
+<br>
+ if (adjustHeadCond) {<br>
+ Changed |= adjustTo(HeadCmpMI, HeadCmp, TrueCmpMI, TrueImm);<br>
+ } else {<br>
+ Changed |= adjustTo(TrueCmpMI, TrueCmp, HeadCmpMI, HeadImm);<br>
+ }<br>
+ }<br>
+ // Other transformation cases almost never occur due to generation of < or ><br>
+ // comparisons instead of <= and >=.<br>
+ }<br>
+<br>
+ return Changed;<br>
+}<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=217220&r1=217219&r2=217220&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp?rev=217220&r1=217219&r2=217220&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64TargetMachine.cpp Thu Sep 4 21:55:24 2014<br>
@@ -68,6 +68,11 @@ EnableEarlyIfConversion("aarch64-enable-<br>
cl::desc("Run early if-conversion"),<br>
cl::init(true));<br>
<br>
+static cl::opt<bool><br>
+EnableCondOpt("aarch64-condopt",<br>
+ cl::desc("Enable the condition optimizer pass"),<br>
+ cl::init(true), cl::Hidden);<br>
+<br>
<br>
extern "C" void LLVMInitializeAArch64Target() {<br>
// Register the target.<br>
@@ -182,6 +187,8 @@ bool AArch64PassConfig::addInstSelector(<br>
}<br>
<br>
bool AArch64PassConfig::addILPOpts() {<br>
+ if (EnableCondOpt)<br>
+ addPass(createAArch64ConditionOptimizerPass());<br>
if (EnableCCMP)<br>
addPass(createAArch64ConditionalCompares());<br>
if (EnableMCR)<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/CMakeLists.txt<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=217220&r1=217219&r2=217220&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/CMakeLists.txt?rev=217220&r1=217219&r2=217220&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/CMakeLists.txt (original)<br>
+++ llvm/trunk/lib/Target/AArch64/CMakeLists.txt Thu Sep 4 21:55:24 2014<br>
@@ -27,6 +27,7 @@ add_llvm_target(AArch64CodeGen<br>
AArch64ExpandPseudoInsts.cpp<br>
AArch64FastISel.cpp<br>
AArch64FrameLowering.cpp<br>
+ AArch64ConditionOptimizer.cpp<br>
AArch64ISelDAGToDAG.cpp<br>
AArch64ISelLowering.cpp<br>
AArch64InstrInfo.cpp<br>
<br>
Added: llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll?rev=217220&view=auto" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll?rev=217220&view=auto</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll (added)<br>
+++ llvm/trunk/test/CodeGen/AArch64/combine-comparisons-by-cse.ll Thu Sep 4 21:55:24 2014<br>
@@ -0,0 +1,349 @@<br>
+; RUN: llc < %s -march=aarch64 -mtriple=aarch64-linux-gnu | FileCheck %s<br>
+<br>
+; marked as external to prevent possible optimizations<br>
+@a = external global i32<br>
+@b = external global i32<br>
+@c = external global i32<br>
+@d = external global i32<br>
+<br>
+; (a > 10 && b == c) || (a >= 10 && b == d)<br>
+define i32 @combine_gt_ge_10() #0 {<br>
+; CHECK-LABEL: combine_gt_ge_10<br>
+; CHECK: cmp<br>
+; CHECK: b.le<br>
+; CHECK: ret<br>
+; CHECK-NOT: cmp<br>
+; CHECK: <a href="http://b.lt" target="_blank">b.lt</a><br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp = icmp sgt i32 %0, 10<br>
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false<br>
+<br>
+land.lhs.true: ; preds = %entry<br>
+ %1 = load i32* @b, align 4<br>
+ %2 = load i32* @c, align 4<br>
+ %cmp1 = icmp eq i32 %1, %2<br>
+ br i1 %cmp1, label %return, label %land.lhs.true3<br>
+<br>
+lor.lhs.false: ; preds = %entry<br>
+ %cmp2 = icmp sgt i32 %0, 9<br>
+ br i1 %cmp2, label %land.lhs.true3, label %if.end<br>
+<br>
+land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true<br>
+ %3 = load i32* @b, align 4<br>
+ %4 = load i32* @d, align 4<br>
+ %cmp4 = icmp eq i32 %3, %4<br>
+ br i1 %cmp4, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+; (a > 5 && b == c) || (a < 5 && b == d)<br>
+define i32 @combine_gt_lt_5() #0 {<br>
+; CHECK-LABEL: combine_gt_lt_5<br>
+; CHECK: cmp<br>
+; CHECK: b.le<br>
+; CHECK: ret<br>
+; CHECK-NOT: cmp<br>
+; CHECK: <a href="http://b.ge" target="_blank">b.ge</a><br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp = icmp sgt i32 %0, 5<br>
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false<br>
+<br>
+land.lhs.true: ; preds = %entry<br>
+ %1 = load i32* @b, align 4<br>
+ %2 = load i32* @c, align 4<br>
+ %cmp1 = icmp eq i32 %1, %2<br>
+ br i1 %cmp1, label %return, label %if.end<br>
+<br>
+lor.lhs.false: ; preds = %entry<br>
+ %cmp2 = icmp slt i32 %0, 5<br>
+ br i1 %cmp2, label %land.lhs.true3, label %if.end<br>
+<br>
+land.lhs.true3: ; preds = %lor.lhs.false<br>
+ %3 = load i32* @b, align 4<br>
+ %4 = load i32* @d, align 4<br>
+ %cmp4 = icmp eq i32 %3, %4<br>
+ br i1 %cmp4, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+; (a < 5 && b == c) || (a <= 5 && b == d)<br>
+define i32 @combine_lt_ge_5() #0 {<br>
+; CHECK-LABEL: combine_lt_ge_5<br>
+; CHECK: cmp<br>
+; CHECK: <a href="http://b.ge" target="_blank">b.ge</a><br>
+; CHECK: ret<br>
+; CHECK-NOT: cmp<br>
+; CHECK: <a href="http://b.gt" target="_blank">b.gt</a><br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp = icmp slt i32 %0, 5<br>
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false<br>
+<br>
+land.lhs.true: ; preds = %entry<br>
+ %1 = load i32* @b, align 4<br>
+ %2 = load i32* @c, align 4<br>
+ %cmp1 = icmp eq i32 %1, %2<br>
+ br i1 %cmp1, label %return, label %land.lhs.true3<br>
+<br>
+lor.lhs.false: ; preds = %entry<br>
+ %cmp2 = icmp slt i32 %0, 6<br>
+ br i1 %cmp2, label %land.lhs.true3, label %if.end<br>
+<br>
+land.lhs.true3: ; preds = %lor.lhs.false, %land.lhs.true<br>
+ %3 = load i32* @b, align 4<br>
+ %4 = load i32* @d, align 4<br>
+ %cmp4 = icmp eq i32 %3, %4<br>
+ br i1 %cmp4, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+; (a < 5 && b == c) || (a > 5 && b == d)<br>
+define i32 @combine_lt_gt_5() #0 {<br>
+; CHECK-LABEL: combine_lt_gt_5<br>
+; CHECK: cmp<br>
+; CHECK: <a href="http://b.ge" target="_blank">b.ge</a><br>
+; CHECK: ret<br>
+; CHECK-NOT: cmp<br>
+; CHECK: b.le<br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp = icmp slt i32 %0, 5<br>
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false<br>
+<br>
+land.lhs.true: ; preds = %entry<br>
+ %1 = load i32* @b, align 4<br>
+ %2 = load i32* @c, align 4<br>
+ %cmp1 = icmp eq i32 %1, %2<br>
+ br i1 %cmp1, label %return, label %if.end<br>
+<br>
+lor.lhs.false: ; preds = %entry<br>
+ %cmp2 = icmp sgt i32 %0, 5<br>
+ br i1 %cmp2, label %land.lhs.true3, label %if.end<br>
+<br>
+land.lhs.true3: ; preds = %lor.lhs.false<br>
+ %3 = load i32* @b, align 4<br>
+ %4 = load i32* @d, align 4<br>
+ %cmp4 = icmp eq i32 %3, %4<br>
+ br i1 %cmp4, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+; (a > -5 && b == c) || (a < -5 && b == d)<br>
+define i32 @combine_gt_lt_n5() #0 {<br>
+; CHECK-LABEL: combine_gt_lt_n5<br>
+; CHECK: cmn<br>
+; CHECK: b.le<br>
+; CHECK: ret<br>
+; CHECK-NOT: cmn<br>
+; CHECK: <a href="http://b.ge" target="_blank">b.ge</a><br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp = icmp sgt i32 %0, -5<br>
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false<br>
+<br>
+land.lhs.true: ; preds = %entry<br>
+ %1 = load i32* @b, align 4<br>
+ %2 = load i32* @c, align 4<br>
+ %cmp1 = icmp eq i32 %1, %2<br>
+ br i1 %cmp1, label %return, label %if.end<br>
+<br>
+lor.lhs.false: ; preds = %entry<br>
+ %cmp2 = icmp slt i32 %0, -5<br>
+ br i1 %cmp2, label %land.lhs.true3, label %if.end<br>
+<br>
+land.lhs.true3: ; preds = %lor.lhs.false<br>
+ %3 = load i32* @b, align 4<br>
+ %4 = load i32* @d, align 4<br>
+ %cmp4 = icmp eq i32 %3, %4<br>
+ br i1 %cmp4, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+; (a < -5 && b == c) || (a > -5 && b == d)<br>
+define i32 @combine_lt_gt_n5() #0 {<br>
+; CHECK-LABEL: combine_lt_gt_n5<br>
+; CHECK: cmn<br>
+; CHECK: <a href="http://b.ge" target="_blank">b.ge</a><br>
+; CHECK: ret<br>
+; CHECK-NOT: cmn<br>
+; CHECK: b.le<br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp = icmp slt i32 %0, -5<br>
+ br i1 %cmp, label %land.lhs.true, label %lor.lhs.false<br>
+<br>
+land.lhs.true: ; preds = %entry<br>
+ %1 = load i32* @b, align 4<br>
+ %2 = load i32* @c, align 4<br>
+ %cmp1 = icmp eq i32 %1, %2<br>
+ br i1 %cmp1, label %return, label %if.end<br>
+<br>
+lor.lhs.false: ; preds = %entry<br>
+ %cmp2 = icmp sgt i32 %0, -5<br>
+ br i1 %cmp2, label %land.lhs.true3, label %if.end<br>
+<br>
+land.lhs.true3: ; preds = %lor.lhs.false<br>
+ %3 = load i32* @b, align 4<br>
+ %4 = load i32* @d, align 4<br>
+ %cmp4 = icmp eq i32 %3, %4<br>
+ br i1 %cmp4, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true3, %lor.lhs.false, %land.lhs.true<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true3, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 1, %land.lhs.true3 ], [ 1, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+%struct.Struct = type { i64, i64 }<br>
+<br>
+@glob = internal unnamed_addr global %struct.Struct* null, align 8<br>
+<br>
+declare %struct.Struct* @Update(%struct.Struct*) #1<br>
+<br>
+; no checks for this case, it just should be processed without errors<br>
+define void @combine_non_adjacent_cmp_br(%struct.Struct* nocapture readonly %hdCall) #0 {<br>
+entry:<br>
+ %size = getelementptr inbounds %struct.Struct* %hdCall, i64 0, i32 0<br>
+ %0 = load i64* %size, align 8<br>
+ br label %land.rhs<br>
+<br>
+land.rhs:<br>
+ %rp.06 = phi i64 [ %0, %entry ], [ %sub, %while.body ]<br>
+ %1 = load i64* inttoptr (i64 24 to i64*), align 8<br>
+ %cmp2 = icmp sgt i64 %1, 0<br>
+ br i1 %cmp2, label %while.body, label %while.end<br>
+<br>
+while.body:<br>
+ %2 = load %struct.Struct** @glob, align 8<br>
+ %call = tail call %struct.Struct* @Update(%struct.Struct* %2) #2<br>
+ %sub = add nsw i64 %rp.06, -2<br>
+ %cmp = icmp slt i64 %0, %rp.06<br>
+ br i1 %cmp, label %land.rhs, label %while.end<br>
+<br>
+while.end:<br>
+ ret void<br>
+}<br>
+<br>
+; undefined external to prevent possible optimizations<br>
+declare void @do_something() #1<br>
+<br>
+define i32 @do_nothing_if_resultant_opcodes_would_differ() #0 {<br>
+; CHECK-LABEL: do_nothing_if_resultant_opcodes_would_differ<br>
+; CHECK: cmn<br>
+; CHECK: <a href="http://b.gt" target="_blank">b.gt</a><br>
+; CHECK: cmp<br>
+; CHECK: <a href="http://b.gt" target="_blank">b.gt</a><br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp4 = icmp slt i32 %0, -1<br>
+ br i1 %cmp4, label %while.body.preheader, label %while.end<br>
+<br>
+while.body.preheader: ; preds = %entry<br>
+ br label %while.body<br>
+<br>
+while.body: ; preds = %while.body, %while.body.preheader<br>
+ %i.05 = phi i32 [ %inc, %while.body ], [ %0, %while.body.preheader ]<br>
+ tail call void @do_something() #2<br>
+ %inc = add nsw i32 %i.05, 1<br>
+ %cmp = icmp slt i32 %i.05, 0<br>
+ br i1 %cmp, label %while.body, label %while.cond.while.end_crit_edge<br>
+<br>
+while.cond.while.end_crit_edge: ; preds = %while.body<br>
+ %.pre = load i32* @a, align 4<br>
+ br label %while.end<br>
+<br>
+while.end: ; preds = %while.cond.while.end_crit_edge, %entry<br>
+ %1 = phi i32 [ %.pre, %while.cond.while.end_crit_edge ], [ %0, %entry ]<br>
+ %cmp1 = icmp slt i32 %1, 2<br>
+ br i1 %cmp1, label %land.lhs.true, label %if.end<br>
+<br>
+land.lhs.true: ; preds = %while.end<br>
+ %2 = load i32* @b, align 4<br>
+ %3 = load i32* @d, align 4<br>
+ %cmp2 = icmp eq i32 %2, %3<br>
+ br i1 %cmp2, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true, %while.end<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 123, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
+<br>
+define i32 @do_nothing_if_compares_can_not_be_adjusted_to_each_other() #0 {<br>
+; CHECK-LABEL: do_nothing_if_compares_can_not_be_adjusted_to_each_other<br>
+; CHECK: cmp<br>
+; CHECK: <a href="http://b.gt" target="_blank">b.gt</a><br>
+; CHECK: cmn<br>
+; CHECK: <a href="http://b.lt" target="_blank">b.lt</a><br>
+entry:<br>
+ %0 = load i32* @a, align 4<br>
+ %cmp4 = icmp slt i32 %0, 1<br>
+ br i1 %cmp4, label %while.body.preheader, label %while.end<br>
+<br>
+while.body.preheader: ; preds = %entry<br>
+ br label %while.body<br>
+<br>
+while.body: ; preds = %while.body, %while.body.preheader<br>
+ %i.05 = phi i32 [ %inc, %while.body ], [ %0, %while.body.preheader ]<br>
+ tail call void @do_something() #2<br>
+ %inc = add nsw i32 %i.05, 1<br>
+ %cmp = icmp slt i32 %i.05, 0<br>
+ br i1 %cmp, label %while.body, label %while.end.loopexit<br>
+<br>
+while.end.loopexit: ; preds = %while.body<br>
+ br label %while.end<br>
+<br>
+while.end: ; preds = %while.end.loopexit, %entry<br>
+ %1 = load i32* @c, align 4<br>
+ %cmp1 = icmp sgt i32 %1, -3<br>
+ br i1 %cmp1, label %land.lhs.true, label %if.end<br>
+<br>
+land.lhs.true: ; preds = %while.end<br>
+ %2 = load i32* @b, align 4<br>
+ %3 = load i32* @d, align 4<br>
+ %cmp2 = icmp eq i32 %2, %3<br>
+ br i1 %cmp2, label %return, label %if.end<br>
+<br>
+if.end: ; preds = %land.lhs.true, %while.end<br>
+ br label %return<br>
+<br>
+return: ; preds = %if.end, %land.lhs.true<br>
+ %retval.0 = phi i32 [ 0, %if.end ], [ 123, %land.lhs.true ]<br>
+ ret i32 %retval.0<br>
+}<br>
<br>
<br>
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</blockquote></div><br></div>