<div dir="ltr">Hi Tim,<div><br></div><div>This patch has just triggered regressions in emperor:</div><div><br></div>Value type is non-standard value, Other.<br>UNREACHABLE executed at /home/llvm-test/slave/continuous/build/include/llvm/CodeGen/MachineValueType.h:368!<br>
0 clang-3.6 0x00000000010559a5 llvm::sys::PrintStackTrace(_IO_FILE*) + 37<br>1 clang-3.6 0x0000000001055e63<br>2 libpthread.so.0 0x00007fc9e5978cb0<br>3 libc.so.6 0x00007fc9e4bb2425 gsignal + 53<br>4 libc.so.6 0x00007fc9e4bb5b8b abort + 379<br>
5 clang-3.6 0x0000000001023de3 llvm::llvm_unreachable_internal(char const*, char const*, unsigned int) + 451<br>6 clang-3.6 0x00000000006d9868<br>7 clang-3.6 0x00000000008477e5 llvm::AArch64TargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const + 6773<br>
8 clang-3.6 0x00000000012a9bce<br>9 clang-3.6 0x00000000012a923c llvm::SelectionDAG::Combine(llvm::CombineLevel, llvm::AliasAnalysis&, llvm::CodeGenOpt::Level) + 2252<br>10 clang-3.6 0x00000000013b175e llvm::SelectionDAGISel::CodeGenAndEmitDAG() + 910<br>
11 clang-3.6 0x00000000013b0998 llvm::SelectionDAGISel::SelectAllBasicBlocks(llvm::Function const&) + 7112<br>12 clang-3.6 0x00000000013ae034 llvm::SelectionDAGISel::runOnMachineFunction(llvm::MachineFunction&) + 1364<br>
13 clang-3.6 0x00000000007f364b<br>14 clang-3.6 0x0000000000b7402c llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 124<br>15 clang-3.6 0x0000000000db397a llvm::FPPassManager::runOnFunction(llvm::Function&) + 362<br>
16 clang-3.6 0x0000000000db3c0b llvm::FPPassManager::runOnModule(llvm::Module&) + 43<br>17 clang-3.6 0x0000000000db41a7 llvm::legacy::PassManagerImpl::run(llvm::Module&) + 999<br>18 clang-3.6 0x0000000001474c3d clang::EmitBackendOutput(clang::DiagnosticsEngine&, clang::CodeGenOptions const&, clang::TargetOptions const&, clang::LangOptions const&, llvm::StringRef, llvm::Module*, clang::BackendAction, llvm::raw_ostream*) + 7197<br>
19 clang-3.6 0x000000000146b45a<br>20 clang-3.6 0x00000000019fe5b3 clang::ParseAST(clang::Sema&, bool, bool) + 467<br>21 clang-3.6 0x000000000146a19c clang::CodeGenAction::ExecuteAction() + 204<br>22 clang-3.6 0x00000000011df48e clang::FrontendAction::Execute() + 62<br>
23 clang-3.6 0x00000000011b2b3c clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 892<br>24 clang-3.6 0x000000000125d58a clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 3050<br>
25 clang-3.6 0x000000000064dc99 cc1_main(llvm::ArrayRef<char const*>, char const*, void*) + 569<br>26 clang-3.6 0x000000000064cb92 main + 12290<br>27 libc.so.6 0x00007fc9e4b9d76d __libc_start_main + 237<br>
28 clang-3.6 0x0000000000649a69<br><br><br>Do you need a reproducer or is this enough for you to work out what's gone on?<div><br></div><div>Cheers,</div><div><br></div><div>James</div></div><div class="gmail_extra">
<br><br><div class="gmail_quote">On 29 August 2014 14:05, Tim Northover <span dir="ltr"><<a href="mailto:tnorthover@apple.com" target="_blank">tnorthover@apple.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
Author: tnorthover<br>
Date: Fri Aug 29 08:05:18 2014<br>
New Revision: 216725<br>
<br>
URL: <a href="http://llvm.org/viewvc/llvm-project?rev=216725&view=rev" target="_blank">http://llvm.org/viewvc/llvm-project?rev=216725&view=rev</a><br>
Log:<br>
AArch64: skip select/setcc combine in complex case.<br>
<br>
In an llvm-stress generated test, we were trying to create a v0iN type and<br>
asserting when that failed. This case could probably be handled by the<br>
function, but not without added complexity and the situation it arises in is<br>
sufficiently odd that there's probably no benefit anyway.<br>
<br>
Should fix PR20775.<br>
<br>
Modified:<br>
llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
llvm/trunk/test/CodeGen/AArch64/cond-sel.ll<br>
<br>
Modified: llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=216725&r1=216724&r2=216725&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp?rev=216725&r1=216724&r2=216725&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp (original)<br>
+++ llvm/trunk/lib/Target/AArch64/AArch64ISelLowering.cpp Fri Aug 29 08:05:18 2014<br>
@@ -7994,22 +7994,24 @@ static SDValue performVSelectCombine(SDN<br>
static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {<br>
SDValue N0 = N->getOperand(0);<br>
EVT ResVT = N->getValueType(0);<br>
+ EVT SrcVT = N0.getOperand(0).getValueType();<br>
+ int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();<br>
<br>
- if (!N->getOperand(1).getValueType().isVector())<br>
+ // If NumMaskElts == 0, the comparison is larger than select result. The<br>
+ // largest real NEON comparison is 64-bits per lane, which means the result is<br>
+ // at most 32-bits and an illegal vector. Just bail out for now.<br>
+ if (!ResVT.isVector() || NumMaskElts == 0)<br>
return SDValue();<br>
<br>
if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)<br>
return SDValue();<br>
<br>
- SDLoc DL(N0);<br>
-<br>
- EVT SrcVT = N0.getOperand(0).getValueType();<br>
- SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,<br>
- ResVT.getSizeInBits() / SrcVT.getSizeInBits());<br>
+ SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumMaskElts);<br>
EVT CCVT = SrcVT.changeVectorElementTypeToInteger();<br>
<br>
// First perform a vector comparison, where lane 0 is the one we're interested<br>
// in.<br>
+ SDLoc DL(N0);<br>
SDValue LHS =<br>
DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));<br>
SDValue RHS =<br>
@@ -8019,8 +8021,8 @@ static SDValue performSelectCombine(SDNo<br>
// Now duplicate the comparison mask we want across all other lanes.<br>
SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);<br>
SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());<br>
- Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),<br>
- Mask);<br>
+ Mask = DAG.getNode(ISD::BITCAST, DL,<br>
+ ResVT.changeVectorElementTypeToInteger(), Mask);<br>
<br>
return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));<br>
}<br>
<br>
Modified: llvm/trunk/test/CodeGen/AArch64/cond-sel.ll<br>
URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cond-sel.ll?rev=216725&r1=216724&r2=216725&view=diff" target="_blank">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/cond-sel.ll?rev=216725&r1=216724&r2=216725&view=diff</a><br>
==============================================================================<br>
--- llvm/trunk/test/CodeGen/AArch64/cond-sel.ll (original)<br>
+++ llvm/trunk/test/CodeGen/AArch64/cond-sel.ll Fri Aug 29 08:05:18 2014<br>
@@ -214,3 +214,13 @@ define void @test_csetm(i32 %lhs, i32 %r<br>
ret void<br>
; CHECK: ret<br>
}<br>
+<br>
+define <1 x i1> @test_wide_comparison(i32 %in) {<br>
+; CHECK-LABEL: test_wide_comparison:<br>
+; CHECK: cmp w0, #1234<br>
+; CHECK: cset<br>
+<br>
+ %tmp = icmp sgt i32 %in, 1234<br>
+ %res = select i1 %tmp, <1 x i1> <i1 1>, <1 x i1> zeroinitializer<br>
+ ret <1 x i1> %res<br>
+}<br>
<br>
<br>
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</blockquote></div><br></div>