<html><head><meta http-equiv="Content-Type" content="text/html charset=utf-8"></head><body style="word-wrap: break-word; -webkit-nbsp-mode: space; -webkit-line-break: after-white-space;">Hey Tim,<div><br></div><div>llvm-stress tracked down a crasher input for this optimization. Filed <a href="http://llvm.org/bugs/show_bug.cgi?id=20775">http://llvm.org/bugs/show_bug.cgi?id=20775</a> with a reduced testcase. “llvm-stress —seed=18027 | llc -mtriple=arm64-apple-ios” produced the original.</div><div><br></div><div>-Jim</div><div><br><div><blockquote type="cite"><div>On May 7, 2014, at 7:10 AM, Tim Northover <<a href="mailto:tnorthover@apple.com">tnorthover@apple.com</a>> wrote:</div><br class="Apple-interchange-newline"><div>Author: tnorthover<br>Date: Wed May 7 09:10:27 2014<br>New Revision: 208210<br><br>URL: <a href="http://llvm.org/viewvc/llvm-project?rev=208210&view=rev">http://llvm.org/viewvc/llvm-project?rev=208210&view=rev</a><br>Log:<br>AArch64/ARM64: optimise vector selects & enable test<br><br>When performing a scalar comparison that feeds into a vector select,<br>it's actually better to do the comparison on the vector side: the<br>scalar route would be "CMP -> CSEL -> DUP", the vector is "CM -> DUP"<br>since the vector comparisons are all mask based.<br><br>Added:<br> llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll<br> - copied, changed from r208209, llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll<br>Modified:<br> llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp<br> llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll<br><br>Modified: llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=208210&r1=208209&r2=208210&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp?rev=208210&r1=208209&r2=208210&view=diff</a><br>==============================================================================<br>--- llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp (original)<br>+++ llvm/trunk/lib/Target/ARM64/ARM64ISelLowering.cpp Wed May 7 09:10:27 2014<br>@@ -366,6 +366,7 @@ ARM64TargetLowering::ARM64TargetLowering<br><br> setTargetDAGCombine(ISD::MUL);<br><br>+ setTargetDAGCombine(ISD::SELECT);<br> setTargetDAGCombine(ISD::VSELECT);<br><br> MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 8;<br>@@ -7121,6 +7122,44 @@ static SDValue performVSelectCombine(SDN<br> IfTrue, IfFalse);<br> }<br><br>+/// A vector select: "(select vL, vR, (setcc LHS, RHS))" is best performed with<br>+/// the compare-mask instructions rather than going via NZCV, even if LHS and<br>+/// RHS are really scalar. This replaces any scalar setcc in the above pattern<br>+/// with a vector one followed by a DUP shuffle on the result.<br>+static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {<br>+ SDValue N0 = N->getOperand(0);<br>+ EVT ResVT = N->getValueType(0);<br>+<br>+ if (!N->getOperand(1).getValueType().isVector())<br>+ return SDValue();<br>+<br>+ if (N0.getOpcode() != ISD::SETCC || N0.getValueType() != MVT::i1)<br>+ return SDValue();<br>+<br>+ SDLoc DL(N0);<br>+<br>+ EVT SrcVT = N0.getOperand(0).getValueType();<br>+ SrcVT = EVT::getVectorVT(*DAG.getContext(), SrcVT,<br>+ ResVT.getSizeInBits() / SrcVT.getSizeInBits());<br>+ EVT CCVT = SrcVT.changeVectorElementTypeToInteger();<br>+<br>+ // First perform a vector comparison, where lane 0 is the one we're interested<br>+ // in.<br>+ SDValue LHS =<br>+ DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(0));<br>+ SDValue RHS =<br>+ DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, SrcVT, N0.getOperand(1));<br>+ SDValue SetCC = DAG.getNode(ISD::SETCC, DL, CCVT, LHS, RHS, N0.getOperand(2));<br>+<br>+ // Now duplicate the comparison mask we want across all other lanes.<br>+ SmallVector<int, 8> DUPMask(CCVT.getVectorNumElements(), 0);<br>+ SDValue Mask = DAG.getVectorShuffle(CCVT, DL, SetCC, SetCC, DUPMask.data());<br>+ Mask = DAG.getNode(ISD::BITCAST, DL, ResVT.changeVectorElementTypeToInteger(),<br>+ Mask);<br>+<br>+ return DAG.getSelect(DL, ResVT, Mask, N->getOperand(1), N->getOperand(2));<br>+}<br>+<br> SDValue ARM64TargetLowering::PerformDAGCombine(SDNode *N,<br> DAGCombinerInfo &DCI) const {<br> SelectionDAG &DAG = DCI.DAG;<br>@@ -7149,6 +7188,8 @@ SDValue ARM64TargetLowering::PerformDAGC<br> return performBitcastCombine(N, DCI, DAG);<br> case ISD::CONCAT_VECTORS:<br> return performConcatVectorsCombine(N, DCI, DAG);<br>+ case ISD::SELECT:<br>+ return performSelectCombine(N, DAG);<br> case ISD::VSELECT:<br> return performVSelectCombine(N, DCI.DAG);<br> case ISD::STORE:<br><br>Modified: llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll?rev=208210&r1=208209&r2=208210&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll?rev=208210&r1=208209&r2=208210&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll (original)<br>+++ llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll Wed May 7 09:10:27 2014<br>@@ -1,5 +1,5 @@<br> ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s<br>-<br>+; arm64 has separate copy of this test due to different codegen.<br> define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v8i8_i8:<br> ; CHECK: and<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w0, #0xff<br><br>Copied: llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll (from r208209, llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll)<br>URL: <a href="http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll?p2=llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll&p1=llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll&r1=208209&r2=208210&rev=208210&view=diff">http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll?p2=llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll&p1=llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll&r1=208209&r2=208210&rev=208210&view=diff</a><br>==============================================================================<br>--- llvm/trunk/test/CodeGen/AArch64/neon-select_cc.ll (original)<br>+++ llvm/trunk/test/CodeGen/ARM64/aarch64-neon-select_cc.ll Wed May 7 09:10:27 2014<br>@@ -1,12 +1,12 @@<br>-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s<br>+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s<br><br> define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v8i8_i8:<br>-; CHECK: and<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w0, #0xff<br>-; CHECK-NEXT: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxtb<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v0.8b, v1.8b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].8b, [[MASK]].b[0]<br>+; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b<br> %cmp31 = icmp eq i8 %a, %b<br> %e = select i1 %cmp31, <8x i8> %c, <8x i8> %d<br> ret <8x i8> %e<br>@@ -14,9 +14,9 @@ define <8x i8> @test_select_cc_v8i8_i8(i<br><br> define <8x i8> @test_select_cc_v8i8_f32(float %a, float %b, <8x i8> %c, <8x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v8i8_f32:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, v0.4s, v1.4s<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v2.8b, v3.8b<br>+; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s<br>+; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]<br>+; CHECK-NEXT: bsl [[DUPMASK]].8b, v2.8b, v3.8b<br> %cmp31 = fcmp oeq float %a, %b<br> %e = select i1 %cmp31, <8x i8> %c, <8x i8> %d<br> ret <8x i8> %e<br>@@ -24,8 +24,8 @@ define <8x i8> @test_select_cc_v8i8_f32(<br><br> define <8x i8> @test_select_cc_v8i8_f64(double %a, double %b, <8x i8> %c, <8x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v8i8_f64:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, v0.2d, v1.2d<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v2.8b, v3.8b<br>+; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1<br>+; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b<br> %cmp31 = fcmp oeq double %a, %b<br> %e = select i1 %cmp31, <8x i8> %c, <8x i8> %d<br> ret <8x i8> %e<br>@@ -33,11 +33,11 @@ define <8x i8> @test_select_cc_v8i8_f64(<br><br> define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v16i8_i8:<br>-; CHECK: and<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w0, #0xff<br>-; CHECK-NEXT: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxtb<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v0.16b, v1.16b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].16b, [[MASK]].b[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b<br> %cmp31 = icmp eq i8 %a, %b<br> %e = select i1 %cmp31, <16x i8> %c, <16x i8> %d<br> ret <16x i8> %e<br>@@ -45,9 +45,9 @@ define <16x i8> @test_select_cc_v16i8_i8<br><br> define <16x i8> @test_select_cc_v16i8_f32(float %a, float %b, <16x i8> %c, <16x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v16i8_f32:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, v0.4s, v1.4s<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, v{{[0-9]+}}.s[0]<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v2.16b, v3.16b<br>+; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s<br>+; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]<br>+; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b<br> %cmp31 = fcmp oeq float %a, %b<br> %e = select i1 %cmp31, <16x i8> %c, <16x i8> %d<br> ret <16x i8> %e<br>@@ -55,9 +55,9 @@ define <16x i8> @test_select_cc_v16i8_f3<br><br> define <16x i8> @test_select_cc_v16i8_f64(double %a, double %b, <16x i8> %c, <16x i8> %d ) {<br> ; CHECK-LABEL: test_select_cc_v16i8_f64:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, v0.2d, v1.2d<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, v{{[0-9]+}}.d[0]<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v2.16b, v3.16b<br>+; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d<br>+; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]<br>+; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b<br> %cmp31 = fcmp oeq double %a, %b<br> %e = select i1 %cmp31, <16x i8> %c, <16x i8> %d<br> ret <16x i8> %e<br>@@ -65,11 +65,11 @@ define <16x i8> @test_select_cc_v16i8_f6<br><br> define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d ) {<br> ; CHECK-LABEL: test_select_cc_v4i16:<br>-; CHECK: and<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w0, #0xffff<br>-; CHECK-NEXT: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxth<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4h, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v0.8b, v1.8b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].4h, v[[LHS]].4h, v[[RHS]].4h<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].4h, [[MASK]].h[0]<br>+; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b<br> %cmp31 = icmp eq i16 %a, %b<br> %e = select i1 %cmp31, <4x i16> %c, <4x i16> %d<br> ret <4x i16> %e<br>@@ -77,11 +77,11 @@ define <4x i16> @test_select_cc_v4i16(i1<br><br> define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d ) {<br> ; CHECK-LABEL: test_select_cc_v8i16:<br>-; CHECK: and<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w0, #0xffff<br>-; CHECK-NEXT: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxth<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8h, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v0.16b, v1.16b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].8h, v[[LHS]].8h, v[[RHS]].8h<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].8h, [[MASK]].h[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b<br> %cmp31 = icmp eq i16 %a, %b<br> %e = select i1 %cmp31, <8x i16> %c, <8x i16> %d<br> ret <8x i16> %e<br>@@ -89,10 +89,11 @@ define <8x i16> @test_select_cc_v8i16(i1<br><br> define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) {<br> ; CHECK-LABEL: test_select_cc_v2i32:<br>-; CHECK: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxtw<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2s, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v0.8b, v1.8b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].2s, v[[LHS]].2s, v[[RHS]].2s<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]<br>+; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b<br> %cmp31 = icmp eq i32 %a, %b<br> %e = select i1 %cmp31, <2x i32> %c, <2x i32> %d<br> ret <2x i32> %e<br>@@ -100,10 +101,11 @@ define <2x i32> @test_select_cc_v2i32(i3<br><br> define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) {<br> ; CHECK-LABEL: test_select_cc_v4i32:<br>-; CHECK: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxtw<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v0.16b, v1.16b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b<br> %cmp31 = icmp eq i32 %a, %b<br> %e = select i1 %cmp31, <4x i32> %c, <4x i32> %d<br> ret <4x i32> %e<br>@@ -111,10 +113,10 @@ define <4x i32> @test_select_cc_v4i32(i3<br><br> define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) {<br> ; CHECK-LABEL: test_select_cc_v1i64:<br>-; CHECK: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>x0, x1<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>x0, xzr, xzr, ne<br>-; CHECK-NEXT: fmov<span class="Apple-tab-span" style="white-space:pre"> </span>d{{[0-9]+}}, x0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v0.8b, v1.8b<br>+; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0<br>+; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1<br>+; CHECK: cmeq d[[MASK:[0-9]+]], d[[LHS]], d[[RHS]]<br>+; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b<br> %cmp31 = icmp eq i64 %a, %b<br> %e = select i1 %cmp31, <1x i64> %c, <1x i64> %d<br> ret <1x i64> %e<br>@@ -122,10 +124,11 @@ define <1x i64> @test_select_cc_v1i64(i6<br><br> define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) {<br> ; CHECK-LABEL: test_select_cc_v2i64:<br>-; CHECK: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>x0, x1<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>x0, xzr, xzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, x0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v0.16b, v1.16b<br>+; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0<br>+; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].2d, v[[LHS]].2d, v[[RHS]].2d<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b<br> %cmp31 = icmp eq i64 %a, %b<br> %e = select i1 %cmp31, <2x i64> %c, <2x i64> %d<br> ret <2x i64> %e<br>@@ -133,18 +136,18 @@ define <2x i64> @test_select_cc_v2i64(i6<br><br> define <1 x float> @test_select_cc_v1f32(float %a, float %b, <1 x float> %c, <1 x float> %d ) {<br> ; CHECK-LABEL: test_select_cc_v1f32:<br>-; CHECK: fcmp<span class="Apple-tab-span" style="white-space:pre"> </span>s0, s1<br>-; CHECK-NEXT: fcsel<span class="Apple-tab-span" style="white-space:pre"> </span>s0, s2, s3, eq<br>+; CHECK: fcmp s0, s1<br>+; CHECK-NEXT: fcsel s0, s2, s3, eq<br> %cmp31 = fcmp oeq float %a, %b<br> %e = select i1 %cmp31, <1 x float> %c, <1 x float> %d<br> ret <1 x float> %e<br> }<br>- <br>+<br> define <2 x float> @test_select_cc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d ) {<br> ; CHECK-LABEL: test_select_cc_v2f32:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, v0.4s, v1.4s<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2s, v{{[0-9]+}}.s[0]<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v2.8b, v3.8b<br>+; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]<br>+; CHECK: bsl [[DUPMASK]].8b, v2.8b, v3.8b<br> %cmp31 = fcmp oeq float %a, %b<br> %e = select i1 %cmp31, <2 x float> %c, <2 x float> %d<br> ret <2 x float> %e<br>@@ -152,9 +155,9 @@ define <2 x float> @test_select_cc_v2f32<br><br> define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x float> %d ) {<br> ; CHECK-LABEL: test_select_cc_v4f32:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, v0.4s, v1.4s<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, v{{[0-9]+}}.s[0]<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v2.16b, v3.16b<br>+; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b<br> %cmp31 = fcmp oeq float %a, %b<br> %e = select i1 %cmp31, <4x float> %c, <4x float> %d<br> ret <4x float> %e<br>@@ -162,10 +165,11 @@ define <4x float> @test_select_cc_v4f32(<br><br> define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x float> %d ) {<br> ; CHECK-LABEL: test_select_cc_v4f32_icmp:<br>-; CHECK: cmp<span class="Apple-tab-span" style="white-space:pre"> </span>w0, w1, uxtw<br>-; CHECK: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>w0, wzr, wzr, ne<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.4s, w0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v0.16b, v1.16b<br>+; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0<br>+; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1<br>+; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b<br> %cmp31 = icmp eq i32 %a, %b<br> %e = select i1 %cmp31, <4x float> %c, <4x float> %d<br> ret <4x float> %e<br>@@ -173,8 +177,8 @@ define <4x float> @test_select_cc_v4f32_<br><br> define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c, <1 x double> %d ) {<br> ; CHECK-LABEL: test_select_cc_v1f64:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, v0.2d, v1.2d<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v2.8b, v3.8b<br>+; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1<br>+; CHECK: bsl v[[MASK]].8b, v2.8b, v3.8b<br> %cmp31 = fcmp oeq double %a, %b<br> %e = select i1 %cmp31, <1 x double> %c, <1 x double> %d<br> ret <1 x double> %e<br>@@ -182,10 +186,10 @@ define <1 x double> @test_select_cc_v1f6<br><br> define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, <1 x double> %d ) {<br> ; CHECK-LABEL: test_select_cc_v1f64_icmp:<br>-; CHECK: cmp<span class="Apple-tab-span" style="white-space:pre"> </span> x0, x1<br>-; CHECK-NEXT: csinv<span class="Apple-tab-span" style="white-space:pre"> </span>x0, xzr, xzr, ne<br>-; CHECK-NEXT: fmov<span class="Apple-tab-span" style="white-space:pre"> </span>d{{[0-9]+}}, x0<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.8b, v0.8b, v1.8b<br>+; CHECK-DAG: fmov [[LHS:d[0-9]+]], x0<br>+; CHECK-DAG: fmov [[RHS:d[0-9]+]], x1<br>+; CHECK: cmeq d[[MASK:[0-9]+]], [[LHS]], [[RHS]]<br>+; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b<br> %cmp31 = icmp eq i64 %a, %b<br> %e = select i1 %cmp31, <1 x double> %c, <1 x double> %d<br> ret <1 x double> %e<br>@@ -193,9 +197,9 @@ define <1 x double> @test_select_cc_v1f6<br><br> define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d ) {<br> ; CHECK-LABEL: test_select_cc_v2f64:<br>-; CHECK: fcmeq<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, v0.2d, v1.2d<br>-; CHECK-NEXT: dup<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.2d, v{{[0-9]+}}.d[0]<br>-; CHECK-NEXT:<span class="Apple-tab-span" style="white-space:pre"> </span>bsl<span class="Apple-tab-span" style="white-space:pre"> </span>v{{[0-9]+}}.16b, v2.16b, v3.16b<br>+; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d<br>+; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]<br>+; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b<br> %cmp31 = fcmp oeq double %a, %b<br> %e = select i1 %cmp31, <2 x double> %c, <2 x double> %d<br> ret <2 x double> %e<br><br><br>_______________________________________________<br>llvm-commits mailing list<br><a href="mailto:llvm-commits@cs.uiuc.edu">llvm-commits@cs.uiuc.edu</a><br>http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits<br></div></blockquote></div><br></div></body></html>